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Xinmiao Zhang 0001
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Publications
- 2023
- [j56]Weihang Tan
, Antian Wang
, Xinmiao Zhang
, Yingjie Lao
, Keshab K. Parhi
:
High-Speed VLSI Architectures for Modular Polynomial Multiplication via Fast Filtering and Applications to Lattice-Based Cryptography. IEEE Trans. Computers 72(9): 2454-2466 (2023) - 2022
- [j46]Xinmiao Zhang
, Zheang Huai
, Keshab K. Parhi
:
Polynomial Multiplication Architecture with Integrated Modular Reduction for R-LWE Cryptosystems. J. Signal Process. Syst. 94(8): 799-809 (2022) - 2021
- [c60]Weihang Tan, Antian Wang
, Yingjie Lao, Xinmiao Zhang, Keshab K. Parhi
:
Pipelined High-Throughput NTT Architecture for Lattice-Based Cryptography. AsianHOST 2021: 1-4 - [c59]Xinmiao Zhang, Keshab K. Parhi
:
Reduced-Complexity Modular Polynomial Multiplication for R-LWE Cryptosystems. ICASSP 2021: 7853-7857 - [c55]Zheang Huai
, Keshab K. Parhi
, Xinmiao Zhang:
Efficient Architecture for Long Integer Modular Multiplication over Solinas Prime. SiPS 2021: 146-151 - [i3]Weihang Tan, Antian Wang, Yingjie Lao, Xinmiao Zhang, Keshab K. Parhi:
Low-Latency VLSI Architectures for Modular Polynomial Multiplication via Fast Filtering and Applications to Lattice-Based Cryptography. CoRR abs/2110.12127 (2021) - 2006
- [j5]Xinmiao Zhang, Keshab K. Parhi
:
On the Optimum Constructions of Composite Field for the AES Algorithm. IEEE Trans. Circuits Syst. II Express Briefs 53-II(10): 1153-1157 (2006) - 2005
- [j3]Xinmiao Zhang, Keshab K. Parhi
:
Fast factorization architecture in soft-decision Reed-Solomon decoding. IEEE Trans. Very Large Scale Integr. Syst. 13(4): 413-426 (2005) - [j2]Xinmiao Zhang, Keshab K. Parhi
:
High-Speed Architectures for Parallel Long BCH Encoders. IEEE Trans. Very Large Scale Integr. Syst. 13(7): 872-877 (2005) - 2004
- [j1]Xinmiao Zhang, Keshab K. Parhi
:
High-speed VLSI architectures for the AES algorithm. IEEE Trans. Very Large Scale Integr. Syst. 12(9): 957-967 (2004) - [c1]Xinmiao Zhang, Keshab K. Parhi
:
High-speed architectures for parallel long BCH encoders. ACM Great Lakes Symposium on VLSI 2004: 1-6
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