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Yunsup Lee
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Books and Theses
- 2016
- [b1]Yunsup Lee:
Decoupled Vector-Fetch Architecture with a Scalarizing Compiler. University of California, Berkeley, USA, 2016
Journal Articles
- 2017
- [j7]Ben Keller
, Martin Cochet, Brian Zimmer
A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI. IEEE J. Solid State Circuits 52(7): 1863-1875 (2017) - 2016
- [j6]Brian Zimmer, Yunsup Lee, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic
A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI. IEEE J. Solid State Circuits 51(4): 930-942 (2016) - [j5]Yunsup Lee, Andrew Waterman, Henry Cook, Brian Zimmer, Ben Keller, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic
An Agile Approach to Building RISC-V Microprocessors. IEEE Micro 36(2): 8-20 (2016) - 2015
- [j4]Chen Sun, Mark T. Wade, Yunsup Lee, Jason S. Orcutt
Single-chip microprocessor that communicates directly using light. Nat. 528(7581): 534-538 (2015) - 2013
- [j3]Yunsup Lee, Rimas Avizienis, Alex Bishara, Richard Xia, Derek Lockhart, Christopher Batten, Krste Asanovic:
Exploring the Tradeoffs between Programmability and Efficiency in Data-Parallel Accelerators. ACM Trans. Comput. Syst. 31(3): 6 (2013) - 2012
- [j2]Andreas Klöckner
PyCUDA and PyOpenCL: A scripting-based approach to GPU run-time code generation. Parallel Comput. 38(3): 157-174 (2012) - [j1]Brian Zimmer, Seng Oon Toh, Huy Vo, Yunsup Lee, Olivier Thomas, Krste Asanovic, Borivoje Nikolic
SRAM Assist Techniques for Operation in a Wide Voltage Range in 28-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 59-II(12): 853-857 (2012)
Conference and Workshop Papers
- 2020
- [c18]Yunsup Lee, Andrew Waterman:
Managing Chip Design Complexity in the Domain-Specific SoC Era. VLSI Circuits 2020: 1-2 - 2017
- [c17]Chen Sun, Mark T. Wade, Yunsup Lee, Jason S. Orcutt, Luca Alloatti, Michael S. Georgas, Andrew S. Waterman, Jeffrey M. Shainline, Rimas R. Avizienis, Sen Lin, Benjamin R. Moss, Rajesh Kumar, Fabio Pavanello, Amir H. Atabaki, Henry M. Cook, Albert J. Ou, Jonathan C. Leu, Yu-Hsin Chen, Krste Asanovic, Rajeev J. Ram, Milos A. Popovic, Vladimir Marko Stojanovic:
Microprocessor chip with photonic I/O. OFC 2017: 1-3 - 2016
- [c16]Ben Keller, Martin Cochet, Brian Zimmer, Yunsup Lee, Milovan Blagojevic, Jaehwa Kwak, Alberto Puggelli, Stevo Bailey, Pi-Feng Chiu, Daniel Palmer Dabbelt, Colin Schmidt, Elad Alon, Krste Asanovic, Borivoje Nikolic
Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC. ESSCIRC 2016: 269-272 - [c15]Donggyu Kim, Adam M. Izraelevitz, Christopher Celio, Hokeun Kim
Strober: Fast and Accurate Sample-Based Energy Simulation for Arbitrary RTL. ISCA 2016: 128-139 - 2015
- [c14]Yunsup Lee, Brian Zimmer, Andrew Waterman, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic
Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking. Hot Chips Symposium 2015: 1-45 - [c13]Mark Stephenson, Siva Kumar Sastry Hari, Yunsup Lee, Eiman Ebrahimi, Daniel R. Johnson, David W. Nellans, Mike O'Connor
Flexible software profiling of GPU architectures. ISCA 2015: 185-197 - [c12]Brian Zimmer, Yunsup Lee, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic
A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI. VLSIC 2015: 316- - 2014
- [c11]Yunsup Lee, Andrew Waterman, Rimas Avizienis, Henry Cook, Chen Sun, Vladimir Stojanovic, Krste Asanovic:
A 45nm 1.3GHz 16.7 double-precision GFLOPS/W RISC-V processor with vector accelerators. ESSCIRC 2014: 199-202 - [c10]Yunsup Lee, Vinod Grover, Ronny Krashinsky, Mark Stephenson, Stephen W. Keckler, Krste Asanovic:
Exploring the Design Space of SPMD Divergence Management on Data-Parallel Architectures. MICRO 2014: 101-113 - 2013
- [c9]Yunsup Lee, Ronny Krashinsky, Vinod Grover, Stephen W. Keckler, Krste Asanovic:
Convergence and scalarization for data-parallel architectures. CGO 2013: 32:1-32:11 - [c8]Yunsup Lee, David Sheffield, Andrew Waterman, Michael J. Anderson, Kurt Keutzer, Krste Asanovic:
Measuring the gap between programmable and fixed-function accelerators: A case study on speech recognition. Hot Chips Symposium 2013: 1-2 - [c7]Andrew Waterman, Yunsup Lee, Rimas Avizienis, Henry Cook, David A. Patterson, Krste Asanovic:
The RISC-V instruction set. Hot Chips Symposium 2013: 1 - [c6]David Sheffield, Michael J. Anderson, Yunsup Lee, Kurt Keutzer:
Hardware/software codesign for mobile speech recognition. INTERSPEECH 2013: 627-631 - 2012
- [c5]Jonathan Bachrach, Huy Vo, Brian C. Richards, Yunsup Lee, Andrew Waterman, Rimas Avizienis, John Wawrzynek, Krste Asanovic:
Chisel: constructing hardware in a Scala embedded language. DAC 2012: 1216-1225 - 2011
- [c4]Yunsup Lee, Rimas Avizienis, Alex Bishara, Richard Xia, Derek Lockhart, Christopher Batten, Krste Asanovic:
The Maven vector-thread architecture. Hot Chips Symposium 2011: 1 - [c3]Yunsup Lee, Rimas Avizienis, Alex Bishara, Richard Xia, Derek Lockhart, Christopher Batten, Krste Asanovic:
Exploring the tradeoffs between programmability and efficiency in data-parallel accelerators. ISCA 2011: 129-140 - 2010
- [c2]Zhangxi Tan, Andrew Waterman, Rimas Avizienis, Yunsup Lee, Henry Cook, David A. Patterson, Krste Asanovic:
RAMP gold: an FPGA-based architecture simulator for multiprocessors. DAC 2010: 463-468 - 2009
- [c1]Bryan Catanzaro, Bor-Yiing Su, Narayanan Sundaram, Yunsup Lee, Mark Murphy, Kurt Keutzer:
Efficient, high-quality image contour detection. ICCV 2009: 2381-2388
Informal and Other Publications
- 2013
- [i2]Andreas Klöckner, Nicolas Pinto, Bryan Catanzaro, Yunsup Lee, Paul Ivanov, Ahmed Fasih:
GPU Scripting and Code Generation with PyCUDA. CoRR abs/1304.5553 (2013) - 2009
- [i1]Andreas Klöckner, Nicolas Pinto, Yunsup Lee, Bryan Catanzaro, Paul Ivanov, Ahmed Fasih:
PyCUDA: GPU Run-Time Code Generation for High-Performance Computing. CoRR abs/0911.3456 (2009)
Coauthor Index
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