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Kanak Agarwal 0001
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Publications
- 2012
- [c51]Vivek Joshi, Kanak Agarwal, Dennis Sylvester:
Design-patterning co-optimization of SRAM robustness for double patterning lithography. ASP-DAC 2012: 713-718 - 2010
- [j11]Vivek Joshi, Brian Cline, Dennis Sylvester, David T. Blaauw, Kanak Agarwal:
Mechanical Stress Aware Optimization for Leakage Power Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(5): 722-736 (2010) - [j10]Harmander Singh, Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown:
Dynamically Pulsed MTCMOS With Bus Encoding for Reduction of Total Power and Crosstalk Noise. IEEE Trans. Very Large Scale Integr. Syst. 18(1): 166-170 (2010) - [c40]Vivek Joshi, Kanak Agarwal, Dennis Sylvester, David T. Blaauw:
Analyzing electrical effects of RTA-driven local anneal temperature variation. ASP-DAC 2010: 739-744 - [c37]Vivek Joshi, Valeriy Sukharev
, Andres Torres, Kanak Agarwal, Dennis Sylvester, David T. Blaauw:
Closed-form modeling of layout-dependent mechanical stress. DAC 2010: 673-678 - [c34]Vivek Joshi, Kanak Agarwal, David T. Blaauw, Dennis Sylvester:
Analysis and optimization of SRAM robustness for double patterning lithography. ICCAD 2010: 25-31 - [c32]Cheng Zhuo, Kanak Agarwal, David T. Blaauw, Dennis Sylvester:
Active learning framework for post-silicon variation extraction and test cost reduction. ICCAD 2010: 508-515 - [c31]Vivek Joshi, Kanak Agarwal, Dennis Sylvester:
Simultaneous extraction of effective gate length and low-field mobility in non-uniform devices. ISQED 2010: 158-162 - 2008
- [j9]Dennis Sylvester, Kanak Agarwal, Saumil Shah:
Variability in nanometer CMOS: Impact, analysis, and minimization. Integr. 41(3): 319-339 (2008) - [c26]Vivek Joshi, Brian Cline, Dennis Sylvester, David T. Blaauw, Kanak Agarwal:
Leakage power reduction using stress-enhanced layouts. DAC 2008: 912-917 - [c25]Vivek Joshi, Brian Cline, Dennis Sylvester, David T. Blaauw, Kanak Agarwal:
Stress aware layout optimization. ISPD 2008: 168-174 - 2007
- [j7]Kanak Agarwal, Rahul M. Rao, Dennis Sylvester, Richard B. Brown:
Parametric Yield Analysis and Optimization in Leakage Dominated Technologies. IEEE Trans. Very Large Scale Integr. Syst. 15(6): 613-623 (2007) - [j6]Harmander Singh, Kanak Agarwal, Dennis Sylvester, Kevin J. Nowka
Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating. IEEE Trans. Very Large Scale Integr. Syst. 15(11): 1215-1224 (2007) - 2006
- [j5]Kanak Agarwal, Dennis Sylvester, David T. Blaauw:
Modeling and analysis of crosstalk noise in coupled RLC interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(5): 892-901 (2006) - [j4]Kanak Agarwal, Mridul Agarwal, Dennis Sylvester, David T. Blaauw:
Statistical interconnect metrics for physical-design optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(7): 1273-1288 (2006) - [c16]Kanak Agarwal, Kevin J. Nowka
Power Gating with Multiple Sleep Modes. ISQED 2006: 633-637 - 2005
- [c15]Kanak Agarwal, Dennis Sylvester, David T. Blaauw, Anirudh Devgan:
Achieving continuous VT performance in a dual VT process. ASP-DAC 2005: 393-398 - [c14]Mridul Agarwal, Kanak Agarwal, Dennis Sylvester, David T. Blaauw:
Statistical modeling of cross-coupling effects in VLSI interconnects. ASP-DAC 2005: 503-506 - [c13]Ashish Srivastava, Saumil Shah, Kanak Agarwal, Dennis Sylvester, David T. Blaauw, Stephen W. Director:
Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance. DAC 2005: 535-540 - [c12]Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Himanshu Kaul, Richard B. Brown, Sani R. Nassif:
Power-aware global signaling strategies. ISCAS (1) 2005: 604-607 - [c11]Rahul M. Rao, Kanak Agarwal, Anirudh Devgan, Kevin J. Nowka
Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization. ISQED 2005: 284-290 - 2004
- [j3]Kanak Agarwal, Dennis Sylvester, David T. Blaauw:
A library compatible driver output model for on-chip RLC transmission lines. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(1): 128-136 (2004) - [j2]Kanak Agarwal, Dennis Sylvester, David T. Blaauw:
A simple metric for slew rate of RC circuits based on two circuit moments. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(9): 1346-1354 (2004) - [c10]Kanak Agarwal, Dennis Sylvester, David T. Blaauw:
A simplified transmission-line based crosstalk noise model for on-chip RLC wiring. ASP-DAC 2004: 858-864 - [c9]Kanak Agarwal, Dennis Sylvester, David T. Blaauw, Frank Liu, Sani R. Nassif, Sarma B. K. Vrudhula:
Variational delay metrics for interconnect timing analysis. DAC 2004: 381-384 - [c8]Saumil Shah, Kanak Agarwal, Dennis Sylvester:
A New Threshold Voltage Assignment Scheme for Runtime Leakage Reduction in On-Chip Repeaters. ICCD 2004: 138-143 - [c7]Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka
Approaches to run-time and standby mode leakage reduction in global buses. ISLPED 2004: 188-193 - 2003
- [j1]Takashi Sato
Bidirectional closed-form transformation between on-chip coupling noise waveforms and interconnect delay-change curves. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(5): 560-572 (2003) - [c6]Kanak Agarwal, Dennis Sylvester, David T. Blaauw:
An effective capacitance based driver output model for on-chip RLC interconnects. DAC 2003: 376-381 - [c5]Kanak Agarwal, Dennis Sylvester, David T. Blaauw:
Simple metrics for slew rate of RC circuits based on two circuit moments. DAC 2003: 950-953 - [c4]Shidhartha Das, Kanak Agarwal, David T. Blaauw, Dennis Sylvester:
Optimal Inductance for On-chip RLC Interconnections. ICCD 2003: 264- - [c3]Kanak Agarwal, Dennis Sylvester, David T. Blaauw:
Dynamic clamping: on-chip dynamic shielding and termination for high-speed RLC buses. SoC 2003: 97-100 - 2002
- [c2]Kanak Agarwal, Dennis Sylvester, David T. Blaauw:
A library compatible driving point model for on-chip RLC interconnects. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 63-69 - [c1]Kanak Agarwal, Yu Cao, Takashi Sato
Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis. ASP-DAC/VLSI Design 2002: 77-
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