+

WO2019007228A1 - 薄膜晶体管及其制备方法、阵列基板和显示装置 - Google Patents

薄膜晶体管及其制备方法、阵列基板和显示装置 Download PDF

Info

Publication number
WO2019007228A1
WO2019007228A1 PCT/CN2018/092834 CN2018092834W WO2019007228A1 WO 2019007228 A1 WO2019007228 A1 WO 2019007228A1 CN 2018092834 W CN2018092834 W CN 2018092834W WO 2019007228 A1 WO2019007228 A1 WO 2019007228A1
Authority
WO
WIPO (PCT)
Prior art keywords
active layer
drain
source
gate
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/092834
Other languages
English (en)
French (fr)
Inventor
徐攀
林奕呈
盖翠丽
张保侠
李全虎
王玲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US16/620,663 priority Critical patent/US11257957B2/en
Publication of WO2019007228A1 publication Critical patent/WO2019007228A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/258—Source or drain electrodes for field-effect devices characterised by the relative positions of the source or drain electrodes with respect to the gate electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H10D86/0223—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a thin film transistor and a method for fabricating the same, an array substrate, and a display device.
  • Oxide thin film transistors are becoming more and more widely used due to high mobility, low leakage, and good uniformity. Reducing the size of oxide thin film transistors has become a trend in the future.
  • An active layer disposed on the substrate and in contact with the source and the drain; a gate insulating layer disposed on a side of the active layer facing away from the substrate; a gate Provided on a side of the gate insulating layer facing away from the substrate; wherein an orthographic projection of the gate, the source, and the drain on the substrate does not overlap. And a side of the active layer facing away from the base substrate is not conductorized by a region covered by the gate, the source, and the drain.
  • the pattern of the gate insulating layer overlaps with the orthographic projection of the gate.
  • the gate and the source, the drain are located on the same side of the active layer, and at least a portion of the source and at least a portion of the drain are active A side of the layer facing away from the base substrate covers the active layer.
  • the gate and the source and the drain are located on opposite sides of the active layer, and a portion of the active layer is opposite to the base substrate of the source One side covers the source, and another portion of the active layer covers the drain on a side of the drain facing away from the base substrate.
  • the source, the drain and the active layer are disposed in the same layer such that an entire surface of the active layer facing away from the substrate substrate is not by the source and the Drain coverage.
  • the thin film transistor further includes: a passivation layer disposed on a side of the thin film transistor facing away from the base substrate; and disposed on the passivation layer facing away from the substrate a side, wherein a region of the passivation layer corresponding to a drain of the thin film transistor is formed with a via, and the conductive electrode is connected to the drain through the via.
  • the present disclosure also provides a display device comprising: the array substrate as described above.
  • the present disclosure also provides a method for fabricating a thin film transistor, including:
  • the step of forming a gate insulating layer and a gate on a side of the active layer facing away from the substrate substrate comprises:
  • the orthographic projection is the same.
  • the material of the active layer is a metal oxide semiconductor
  • the step of conducting a conductor treatment on a region of the active layer facing away from the base substrate without being covered by the gate, the source, and the drain includes:
  • the step of forming a source, a drain, and an active layer on the base substrate includes:
  • Laser crystallization treatment is performed on a region of the active layer facing away from the substrate and not covered by the source and drain;
  • the step of forming a source, a drain, and an active layer on the base substrate includes:
  • the source, the drain and the active layer are formed such that a portion of the active layer covers the source on a side of the source facing away from the base substrate, Another portion of the active layer covers the drain on a side of the drain facing away from the substrate.
  • FIG. 1 is a schematic structural view of a thin film transistor in the prior art
  • FIG. 2 is a schematic structural view of another thin film transistor in the prior art
  • 3a is a schematic structural diagram of a thin film transistor according to an embodiment of the present disclosure.
  • Figure 3b is a plan view showing the structure of the thin film transistor shown in Figure 3a;
  • FIG. 4a is a schematic structural diagram of a thin film transistor according to another embodiment of the present disclosure.
  • 4b is a schematic structural diagram of a thin film transistor according to still another embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
  • FIG. 5b is a schematic structural diagram of an array substrate according to another embodiment of the present disclosure.
  • FIG. 6 is a flowchart of a method for fabricating a thin film transistor according to an embodiment of the present disclosure
  • 7a to 7g are schematic diagrams showing an intermediate structure of a thin film transistor prepared by the preparation method shown in FIG. 6;
  • FIG. 8 is a schematic view showing a case where an active layer is subjected to a conductor treatment when the active layer is located above the source and the drain;
  • Figure 9a is a schematic view of a passivation layer formed over a thin film transistor
  • Figure 9b is a schematic illustration of the formation of conductive electrodes and conductive traces on a passivation layer.
  • the thin film transistor is a bottom gate thin film transistor, that is, the gate 1 is located under the active layer 3, so that the active layer 3 is
  • the formation of the conductive channel connecting the source 4 and the drain 5 makes the size of the gate 1 as large as possible.
  • a partial region of the gate 1 overlaps with a partial region of the source 4 (and the drain 5), thereby generating a parasitic capacitance at the position of the overlapping region A of the conductive channel, thereby affecting the operational characteristics of the thin film transistor. .
  • FIG. 2 is a schematic structural view of another thin film transistor in the prior art.
  • the gate 1 of the thin film transistor is located above the active layer 3, and the source 4 and the drain 5 are also located at the active layer 3.
  • Above the source 4 and the drain 5 are connected to the active layer 3 through vias 7. Since there is no overlapping region between the gate 1 and the source 4 and the drain 5 at this time, the problem of parasitic capacitance can be effectively solved.
  • the via hole 7 needs to be provided on the second insulating layer 6 above the active layer 3, the subsequently formed source 4 and drain 5 can pass through the via hole 7 and The active layer 3 is connected. Since the via hole 7 needs to occupy a certain volume, the size of the entire thin film transistor is large, which is disadvantageous for the small size of the thin film transistor, which is disadvantageous for the high resolution of the display panel.
  • the thin film transistor includes a source 4, a drain 5, and an active layer 3 on a substrate substrate 16.
  • the source 4 and the drain 5 are disposed in the same layer and are respectively in contact with the active layer 3.
  • a gate insulating layer 2 is formed on a side of the active layer 3 facing away from the base substrate 16, and a gate 1 is formed on a side of the gate insulating layer 2 facing away from the base substrate 16, and the gate 1, the source 4, and the drain 5 are formed.
  • the orthographic projections on the active layer 3 do not overlap, and the region B of the active layer 3 facing away from the base substrate 16 that is not covered by the gate 1, the source 4, and the drain 5 is conductorized.
  • the region B of the active layer 3 facing away from the base substrate 16 in FIG. 3a is not covered by the gate 1, the source 4 and the drain 5, and the gate of the active layer 3 is at the gate. 1.
  • the direction in which the drain 4 and the source 5 extend ie, the direction indicated by the arrow A in FIG. 3b) is covered by the orthographic projection of the gate 1, the orthographic projection of the source 4, and the orthographic projection of the drain 5.
  • the area outside the area i.e., the area of the active layer 3 between the gate 1 and the source 5 and between the gate 1 and the drain 4) is as shown by the area B in Fig. 3b.
  • the term “same layer setting” refers to the relationship between layers that are simultaneously formed in the same step.
  • the source and drain when the source and drain are formed as a result of one or more steps of the same patterning process performed in the same material layer, they are located in the same layer.
  • the source and the drain may be formed in the same layer by simultaneously performing the step of forming the source and the step of forming the drain.
  • the term “same layer setting" does not always mean that the thickness of the layer or the height of the layer is the same in the cross-sectional view. For example, in FIG. 3a, the source 5 and the drain 4 formed by one patterning process can be understood as being disposed in the same layer.
  • the material of the active layer 3 is a metal oxide semiconductor, that is, the thin film transistor is a metal oxide thin film transistor.
  • the source electrode 4 and the drain electrode 5 are directly in contact with the active layer 3, it is not necessary to provide a via hole, thereby facilitating the miniaturization of the thin film transistor.
  • the orthographic projections of the gate 1, the source 4, and the drain 5 on the active layer 3 do not overlap, there is no overlapping area between the gate 1 and the source 4 and the drain 5, and thus Effectively avoid the generation of parasitic capacitance.
  • the gate 1, the source 4 and the drain 5 are located on the same side of the active layer 3, and at least a portion of the source 4 and at least a portion of the drain 5 cover the active layer 3.
  • the pattern of the gate insulating layer 2 overlaps with the orthographic projection of the gate 1.
  • the same mask can be used to realize the patterning of the gate insulating layer 2 and the gate 1, thereby effectively reducing the number of masks in the production process and saving production costs.
  • FIG. 4a is a schematic structural diagram of a thin film transistor according to another embodiment of the present disclosure.
  • the gate 1 and the source 4 of the thin film transistor shown in FIG. 3 are located on the same side of the active layer 3.
  • the gate 1 and the source 4 of the thin film transistor provided in this embodiment are located on different sides of the active layer 3, that is, the gate 1 is located on the side of the active layer 3 facing away from the substrate 16, and the source is 4 and the drain 5 are located on the side of the active layer 3 facing the substrate substrate 16.
  • a portion of the active layer 3 covers and contacts the source 4
  • another portion of the active layer 3 covers and contacts the drain 5, and the remaining portion of the active layer 3 covers and contacts the substrate 16.
  • the region of the active layer 3 facing away from the base substrate 16 in FIG. 4a that is not covered by the gate 1, the source 4 and the drain 5 means that the active layer 3 is at the gate 1 A region other than a region covered by the orthographic projection of the gate 1 in the extending direction of the drain 4 and the source 5 .
  • the region of the active layer 3 covered only by the orthographic projection of the gate 1 is not conductorized, and the regions of the active layer 3 that are not covered by the orthographic projection of the gate 1 are all conductorized.
  • the contact area between the source 4 and the drain 5 and the conductorized portion on the active layer 3 can be effectively increased, thereby effectively reducing the contact between the source 4 and the drain 5 and the conductorized portion on the active layer 3. resistance.
  • the source 4 and the drain 5 are in contact with the active layer 3, respectively.
  • the active layer 3, the source 4 and the drain 5 may be disposed in the same layer such that the entire surface of the active layer facing away from the substrate is not subjected to the source and The drain is covered.
  • the region of the active layer 3 facing away from the base substrate 16 in FIG. 4b that is not covered by the gate 1, the source 4 and the drain 5 means that the active layer 3 is at the gate 1 A region other than a region covered by the orthographic projection of the gate 1 in the extending direction of the drain 4 and the source 5 .
  • the active layer 3 and the source 4 and the drain 5 do not overlap each other. In this way, production costs can be reduced.
  • FIG. 5A is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
  • the array substrate includes a thin film transistor TFT, and the thin film transistor TFT uses the thin film transistor provided in the above embodiment (FIG. 5a).
  • the thin film transistor on the array substrate is the thin film transistor of FIG. 3 is illustrated in FIG. 5b.
  • the thin film transistor TFT refer to the content in the above embodiment, and details are not described herein again.
  • the array substrate in the present embodiment is an array substrate in a liquid crystal display panel (LCD) or an array substrate in an Organic Light-Emitting Diode (OLED).
  • LCD liquid crystal display panel
  • OLED Organic Light-Emitting Diode
  • the array substrate further includes a passivation layer 8 and a conductive electrode 9 , wherein the passivation layer 8 is located on a side of the thin film transistor facing away from the substrate 16 , and the conductive electrode 9 is located at a side of the passivation layer 8 facing away from the substrate 16 .
  • a region of the passivation layer 8 corresponding to the drain 5 of the thin film transistor is formed with a via, and the conductive electrode 9 is connected to the drain 5 through the via.
  • the conductive electrode 9 is a pixel electrode; when the array substrate is an array substrate in an OLED, the conductive electrode 9 is an anode of the light emitting diode.
  • the array substrate provided in this embodiment may further include a gate line 12 and a data line 11, wherein the gate line 12 is disposed in the same layer as the gate 1, the data line 11 is disposed in the same layer as the source 4, and the data line 11 is directly connected to the source.
  • the pole 4 is connected, and the gate line 12 is electrically connected to the gate 1 through the conductive trace 13.
  • the source electrode 4 and the data line 11 may be simultaneously prepared by one patterning process, and the gate electrode 1 and the gate line 12 are simultaneously prepared by one patterning process, and the gate insulating layer 2 is present under the gate line 12, The gate line 12 and the data line 11 are insulated.
  • a via hole is also formed on the passivation layer 8 at a position corresponding to the gate line 12 and the gate 1, and the conductive trace 13 is connected to both the gate line 12 and the gate 1 through the via.
  • the conductive traces 13 are disposed in the same layer as the conductive electrodes 9, and the conductive traces 13 and the conductive electrodes 9 can be simultaneously prepared by one patterning process, thereby greatly reducing the number of masks required in the process. reduce manufacturing cost.
  • FIG. 5 is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure.
  • the array substrate is an array substrate in an OLED
  • the light emitting device on the array substrate is a bottom emission light emitting device
  • a light shielding pattern 14 and an insulating layer 15 are required to be disposed under the thin film transistor TFT.
  • the light shielding pattern 14 can be connected to the source or the drain of the thin film transistor TFT to prevent the light shielding pattern 14 from floating.
  • the material of the light shielding pattern 14 is a metal material.
  • the embodiment of the present disclosure further provides a display device, which includes an array substrate, and the array substrate adopts the array substrate in the above embodiment.
  • the array substrate adopts the array substrate in the above embodiment.
  • the description of the array substrate refer to the content in the above embodiment. Narration.
  • the display device in this embodiment may be: a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or the like, or any product having a display function or component.
  • FIG. 6 is a flow chart of a method for fabricating a thin film transistor according to an embodiment of the present disclosure
  • FIGS. 7a to 7f are schematic diagrams showing an intermediate structure of a thin film transistor prepared by using the preparation method shown in FIG. 6, as shown in FIG. 6 to FIG.
  • the preparation method can prepare the thin film transistor in the above embodiment, and the preparation method comprises:
  • Step S1 forming a source, a drain, and an active layer on the base substrate, and the source and the drain are disposed in the same layer and are respectively in contact with the active layer.
  • Step S1 specifically includes:
  • Step S101 forming an active layer on the base substrate.
  • a thin film of an active layer material is formed on the substrate substrate 16 by a coating, magnetron sputtering or vapor deposition process.
  • the active layer material is a metal oxide semiconductor material; Then, the active layer material film is subjected to a patterning process to obtain a pattern of the active layer 3.
  • the patterning process in the present disclosure refers to a process including photoresist coating, exposure, development, etching, photoresist stripping, and the like.
  • Step S102 forming a source and a drain on a side of the active layer facing away from the substrate.
  • a film of a conductive material is formed on the surface of the base substrate 16 and the side of the active layer 3 facing away from the base substrate 16 by a coating, magnetron sputtering or vapor deposition process, optionally
  • the conductive material is a metal material; then, the conductive material film is patterned to obtain a pattern of the source 4 and the drain 5, and both the source 4 and the drain 5 are in contact with the active layer 3.
  • the method further includes:
  • Step S101a laser crystallization treatment is performed on a region of the active layer facing away from the substrate and not covered by the source and drain.
  • the laser crystallization treatment is performed on the region of the active layer 3 that is not covered by the subsequent source 4 and the drain 5 in advance, so that the corrosion resistance of the region is enhanced, thereby avoiding erroneous etching.
  • the source 4 and the drain 5 may be prepared first, and then the active layer 3 (the case shown in FIG. 4a) is prepared.
  • the step S1 may include: forming a thin film of a conductive material on the base substrate 16; patterning the thin film of the conductive material to obtain a pattern of the source 4 and the drain 5; at the source 4 and the drain A pattern of 5 is formed on a side of the base substrate 16 to form a thin film of the active layer material; and a patterning process is performed on the thin film of the active layer material to obtain a pattern of the active layer 3.
  • Step S2 forming a gate insulating layer and a gate on a side of the active layer facing away from the base substrate, the gate is located on a side of the gate insulating layer facing away from the base substrate, and the gate, the source and the drain are in the active layer
  • the orthographic projections on the top do not overlap.
  • Step S2 specifically includes:
  • Step S201 forming a thin film of gate insulating material on a side of the active layer facing away from the substrate.
  • a film 2a of gate insulating material is formed on the surface of the substrate prepared in step S1 by a coating, magnetron sputtering or vapor deposition process.
  • the gate insulating material includes at least one of silicon oxide and silicon nitride.
  • Step S202 forming a film of a gate conductive material on a side of the gate insulating material film facing away from the substrate.
  • a gate conductive material film 1a is formed on the side of the gate insulating material film 2a facing away from the substrate substrate 16 by coating, magnetron sputtering or vapor deposition.
  • the electrically conductive material is a metallic material.
  • Step S203 applying a photoresist on a side of the gate conductive material film facing away from the substrate.
  • Step S204 exposing the photoresist to the photoresist using a mask, and developing the exposed photoresist, and the photoresist located in the region where the gate is to be formed is completely retained.
  • the photoresist 10 located in the region where the gate electrode is to be formed is completely retained.
  • Step S205 respectively etching the gate conductive material film and the gate insulating material film to obtain a pattern of the gate and a pattern of the gate insulating layer, and the pattern of the gate and the orthographic projection of the gate insulating layer overlap.
  • the gate conductive material film is etched by a wet etching process to obtain a pattern of the gate electrode 1; then, the gate insulating material film is etched by a dry etching process, A pattern of the gate insulating layer 2 is obtained. At this time, the pattern of the gate electrode 1 and the front projection of the gate insulating layer 2 overlap.
  • the photoresist located above the gate 1 is peeled off.
  • Step S3 Conducting a conductor layer on a side of the active layer facing away from the substrate without being covered by the gate, the source and the drain.
  • hydrogen plasma is implanted into the surface of the substrate prepared in step S2, and the side of the active layer 3 facing away from the substrate 16 is not covered by the gate 1, the source 4, and the drain 5.
  • a metal oxide semiconductor of a region (a region outside the region covered by the orthographic projection of the gate 1, the source 4, and the drain 5 on the active layer 3) is in contact with and reacted with hydrogen plasma (hydrogen ion and metal oxide semiconductor)
  • the oxygen ions in the region are combined, and the metal oxide in this region is deoxidized and converted into a simple metal element to have conductivity (ie, the metal oxide semiconductor is conductorized).
  • step S2 if the pattern of the gate insulating layer 2 in step S2 is different from the pattern of the gate electrode 1 (the pattern of the gate insulating layer 2 is larger than the pattern of the gate electrode 1), the portion of the gate insulating layer 2 beyond the gate 1 will The effect of the conductor treatment in step S3 is affected, thereby affecting the electrical characteristics of the finally formed thin film transistor.
  • step S1 is a schematic view showing a case where the active layer 3 is electrically connected to the active layer 3 when it is placed over the source 4 and the drain 5.
  • the source 4 and the drain 5 are prepared in step S1
  • the active layer 3 is further prepared (the active layer 3 is located on the side of the source 4 and the drain 5 facing away from the base substrate 16)
  • the source layer 3 is sourced when hydrogen plasma implantation is performed in step S3.
  • the region covered by the positive projection of the pole 4 and the drain 5 is also conductorized, and the contact area between the source 4 and the drain 5 and the conductorized portion on the active layer 3 can be effectively increased, thereby effectively reducing the contact area.
  • the technical solution of the present disclosure can greatly reduce the number of reticle used in the production process.
  • FIG. 9a is a schematic view showing a passivation layer formed on a thin film transistor.
  • a passivation layer material film is formed on the substrate obtained in step S3, and a gate electrode is formed on the passivation layer material film by a patterning process.
  • the regions of the gate lines 12 and the drain electrodes 5 respectively form via holes, and the remaining passivation layer material constitutes a pattern of the passivation layer 8.
  • FIG. 9b is a schematic view showing the formation of a conductive electrode and a conductive trace on the passivation layer. As shown in FIG. 9b, a thin film of a conductive material is formed on the passivation layer 8 to form a pattern of the conductive electrode 9 and the conductive trace 13 by a patterning process. .

Landscapes

  • Thin Film Transistor (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Liquid Crystal (AREA)

Abstract

本公开提供了一种薄膜晶体管及其制备方法、阵列基板和显示装置，该薄膜晶体管包括源极和漏极，其同层设置并设置在衬底基板上；有源层，其设置在所述衬底基板上并与所述源极、漏极接触；栅绝缘层，其设置在所述有源层的背向所述衬底基板的一侧；栅极，其设置在所述栅绝缘层的背向所述衬底基板的一侧；其中，所述栅极、所述源极、所述漏极在所述衬底基板上的正投影不重叠，并且所述有源层背向所述衬底基板的一侧未被所述栅极、所述源极和所述漏极的所覆盖的区域被导体化。

Description

薄膜晶体管及其制备方法、阵列基板和显示装置
相关申请的交叉引用
本申请要求于2017年7月4日提交至中国知识产权局的中国专利申请No.201710538052.8的优先权，所公开的内容以引用的方式并入本文。
技术领域
本公开涉及显示技术领域，特别涉及一种薄膜晶体管及其制备方法、阵列基板和显示装置。
背景技术
随着氧化物薄膜晶体管由于高迁移率、低漏电以及均匀性佳等原因，越来越被广泛使用。减小氧化物薄膜晶体管的尺寸已经成为未来的发展趋势。
发明内容
在一方面，本公开提供了一种薄膜晶体管，包括：源极和漏极，其同层设置并设置在衬底基板上；
有源层，其设置在所述衬底基板上并与所述源极、漏极接触；栅绝缘层，其设置在所述有源层的背向所述衬底基板的一侧；栅极，其设置在所述栅绝缘层的背向所述衬底基板的一侧；其中，所述栅极、所述源极、所述漏极在所述衬底基板上的正投影不重叠，并且所述有源层背向所述衬底基板的一侧未被所述栅极、所述源极和所述漏极的所覆盖的区域被导体化。
可选地，所述栅绝缘层的图形与所述栅极的正投影重叠。
可选地，所述栅极和所述源极、所述漏极位于所述有源层的相同侧，并且，所述源极的至少一部分和所述漏极的至少一部分在所述有源层的背向所述衬底基板的一侧覆盖所述有源层。
可选地，所述栅极和所述源极、所述漏极位于所述有源层的相 对侧，并且，所述有源层的一部分在所述源极的背向所述衬底基板的一侧覆盖所述源极，所述有源层的另一部分在所述漏极的背向所述衬底基板的一侧覆盖所述漏极。可选地，所述源极、所述漏极和所述有源层同层设置，以使得所述有源层的背向所述衬底基板的整个表面不被所述源极和所述漏极覆盖。
另一方面，本公开还提供了一种阵列基板，包括：如上述的薄膜晶体管。
可选地，所述薄膜晶体管还包括：钝化层，其设置在所述薄膜晶体管背向所述衬底基板的一侧；其设置在所述钝化层背向所述衬底基板的一侧，其中，所述钝化层上对应所述薄膜晶体管的漏极的区域形成有过孔，所述导电电极通过所述过孔与所述漏极连接。
另一方面，本公开还提供了一种显示装置，包括：如上述的阵列基板。
另一方面，本公开还提供了一种薄膜晶体管的制备方法，包括：
在衬底基板上形成源极、漏极和有源层，所述源极和所述漏极同层设置并且分别与所述有源层接触；
在所述有源层背向所述衬底基板的一侧形成栅绝缘层，在所述栅绝缘层背向所述衬底基板的一侧形成栅极，所述栅极、所述源极、所述漏极在所述衬底基板上的正投影不重叠；以及
对所述有源层上背向所述衬底基板的一侧未被所述栅极、所述源极和所述漏极所覆盖的区域进行导体化处理。
可选地，所述在所述有源层背向所述衬底基板的一侧形成栅绝缘层和栅极的步骤包括：
在所述有源层的背向所述衬底基板的形成栅绝缘材料薄膜；
在所述栅绝缘材料薄膜背向所述衬底基板的一侧形成栅导电材料薄膜；
在所述栅导电材料薄膜背向所述衬底基板的一侧涂布光刻胶；
使用掩模板对所述光刻胶进行曝光处理，并对曝光处理后的光刻胶进行显影处理，位于待形成栅极的区域的光刻胶完全保留；
分别对所述栅导电材料薄膜和栅绝缘材料薄膜进行刻蚀处理， 以得到栅极的图形和栅绝缘层的图形，所述栅极的图形和栅绝缘层的图形在所述衬底基板上的正投影相同。
可选地，所述有源层的材料为金属氧化物半导体；
所述对所述有源层上背向所述衬底基板的一侧未被所述栅极、所述源极和所述漏极所覆盖的区域进行导体化处理的步骤包括：
对所述有源层上背向所述衬底基板的一侧未被所述栅极、所述源极和所述漏极所覆盖的区域进行脱氧处理，以使得所述区域的氧化物半导体导体化。
可选地，所述在衬底基板上形成源极、漏极和有源层的步骤包括：
在衬底基板上形成有源层材料薄膜；
对所述有源层材料薄膜晶体管进行构图工艺以得到有源层的图形；
对有源层背向所述衬底基板的一侧且未被后续形成源极和漏极所覆盖的区域进行激光晶化处理；
在有源层背向衬底基板的一侧形成导电材料薄膜；
对所述导电材料薄膜进行构图工艺以得到源极和漏极的图形，其中，所述源极、所述漏极和所述有源层形成为：所述源极的至少一部分和所述漏极的至少一部分在所述有源层的背向所述衬底基板的一侧覆盖所述有源层。
可选地，所述在衬底基板上形成源极、漏极和有源层的步骤包括：
在衬底基板上形成导电材料薄膜；
对所述导电材料薄膜进行构图工艺以得到所述源极的图形和所述漏极的图形；
在所述源极的图形和所述漏极的图形背向所述衬底基板的一侧形成有源层材料薄膜；以及
对所述有源层材料薄膜进行构图工艺以得到有源层的图形，
其中，所述源极、所述漏极和所述有源层形成为：所述有源层的一部分在所述源极的背向所述衬底基板的一侧覆盖所述源极，所述 有源层的另一部分在所述漏极的背向所述衬底基板的一侧覆盖所述漏极。
附图说明
图1是现有技术中一种薄膜晶体管的结构示意图；
图2为现有技术中又一种薄膜晶体管的结构示意图；
图3a为本公开的一个实施例提供的一种薄膜晶体管的结构示意图；
图3b为图3a所示的薄膜晶体管的结构的俯视图；
图4a为本公开的另一个实施例提供的一种薄膜晶体管的结构示意图；
图4b为本公开的又一个实施例提供的一种薄膜晶体管的结构示意图；
图5a为本公开的一个实施例提供的一种阵列基板的结构示意图；
图5b为本公开的另一个实施例提供的阵列基板的结构示意图，
图6为本公开实施例提供的一种薄膜晶体管的制备方法的流程图；
[根据细则91更正 22.08.2018]　
图7a～图7g为采用图6所示制备方法制备薄膜晶体管的中间结构示意图；
图8为有源层位于源极和漏极上方时对有源层进行导体化处理时的示意图；
图9a为在薄膜晶体管上方形成钝化层时的示意图；
图9b为在钝化层上形成导电电极和导电走线的示意图。
具体实施方式
为使本领域的技术人员更好地理解本公开的技术方案，下面结合附图对本公开提供的一种薄膜晶体管及其制备方法、阵列基板和显示装置进行详细描述。
图1是现有技术中一种薄膜晶体管的结构示意图，如图1所示，该薄膜晶体管为底栅型薄膜晶体管，即栅极1位于有源层3的下方， 为使得有源层3中能够形成连接源极4和漏极5的导电沟道，则会将栅极1的尺寸做的尽量较大。然而，此时栅极1的部分区域与源极4(以及漏极5)的部分区域重叠，从而在导电沟道的重叠区域A的位置处产生寄生电容，进而对薄膜晶体管的工作特性产生影响。
为解决该寄生电容的问题，现有技术中提供又一种顶栅型薄膜晶体管。图2为现有技术中又一种薄膜晶体管的结构示意图，如图2所示，该薄膜晶体管中栅极1位于有源层3的上方，源极4和漏极5也位于有源层3的上方，源极4和漏极5均通过过孔7与有源层3连接。由于此时栅极1与源极4、漏极5之间不存在重叠区域，因而可有效解决寄生电容的问题。
然而，在图2所示薄膜晶体管中，由于需要在位于有源层3上方的第二绝缘层6上设置过孔7，以使得后续形成的源极4和漏极5能够通过过孔7与有源层3连接。由于该过孔7需要占用一定的体积，则会使得整个薄膜晶体管的尺寸较大，不利于薄膜晶体管的小尺寸化，不利于显示面板高分辨率的实现。
由此可见，如何在避免产生寄生电容的同时减小薄膜晶体管的尺寸，是本领域技术人员亟需解决的技术问题。
图3a为本公开的一个实施例提供的一种薄膜晶体管的结构示意图，如图3a所示，该薄膜晶体管包括：位于衬底基板16上的源极4、漏极5、有源层3，其中，源极4与漏极5同层设置并分别与有源层3接触。有源层3背向衬底基板16的一侧形成有栅绝缘层2，栅绝缘层2背向衬底基板16的一侧形成有栅极1，栅极1、源极4、漏极5在有源层3上的正投影不重叠，有源层3背向衬底基板16的一侧未被栅极1、源极4和漏极5所覆盖的区域B被导体化。
需要说明的是，图3a中有源层3背向衬底基板16的一侧未被栅极1、源极4和漏极5所覆盖的区域B是指，有源层3的在栅极1、漏极4、源极5的延伸方向(即，图3b中箭头A所示的方向)上除了被栅极1的正投影、源极4的正投影、漏极5的正投影所覆盖的区域之外的(即，有源层3的位于栅极1和源极5之间以及栅极1和漏极4之间的区域)区域，如图3b中的区域B所示。
如本文所用，术语“同层设置”指的是在相同步骤中同时形成的各层之间的关系。在一个示例中，当源极与漏极作为在相同材料层中执行的相同构图工艺的一个或多个步骤的结果而形成时，它们位于相同层。在另一个示例中，可以通过同时执行形成源极的步骤和形成漏极的步骤而将源极和漏极形成在相同层。术语“同层设置”不总是意味着层的厚度或层的高度在截面图中是相同的。例如，图3a中，通过一次构图工艺形成的源极5和漏极4可以理解为同层设置。
可选地，有源层3的材料为金属氧化物半导体，即该薄膜晶体管为金属氧化物型薄膜晶体管。
在本公开中，由于源极4和漏极5直接与有源层3接触，因而无需设置过孔，从而有利于薄膜晶体管的小尺寸化。与此同时，由于栅极1、源极4、漏极5在有源层3上的正投影不重叠，因此栅极1与源极4和漏极5之间不会存在重叠区域，因而可有效避免寄生电容的产生。
由此可见，本公开的技术方案可在减小薄膜晶体管尺寸的同时有效避免寄生电容的产生。
本实施例中，栅极1、源极4和漏极5位于所述有源层3的相同侧，源极4的至少一部分和漏极5的至少一部分覆盖有源层3。
本实施例中，可选地，栅绝缘层2的图形与栅极1的正投影重叠。此时可使用同一掩模板来实现栅绝缘层2和栅极1的图案化，从而有效减少生产工序中掩模板的数量，节约生产成本。此外，通过使得栅绝缘层2与栅极1的正投影重叠，还能方便后续对有源层3背向衬底基板16的一侧未被栅极1、源极4和漏极5所覆盖的区域的导体化工序的进行，具体原理可参见下方相应内容。
图4a为本公开的另一实施例提供的一种薄膜晶体管的结构示意图，如图4a所示，与图3所示薄膜晶体管中栅极1和源极4位于有源层3的相同侧的情况不同的是，本实施例提供的薄膜晶体管中栅极1和源极4位于有源层3的不同侧，即栅极1位于有源层3背向衬底基板16的一侧，源极4和漏极5位于有源层3的朝向衬底基板16的一侧。换句话说，有源层3的一部分覆盖并接触所述源极4，有源 层3的另一部分覆盖并接触所述漏极5，有源层3的剩余部分覆盖并接触所述衬底基板16。
需要说明的是，图4a中有源层3背向衬底基板16的一侧未被栅极1、源极4和漏极5所覆盖的区域是指，有源层3的在栅极1、漏极4、源极5的延伸方向上除了被栅极1的正投影所覆盖的区域之外的区域。
在本实施例中，有源层3上仅被栅极1的正投影所覆盖的区域未被导体化，而有源层3上未被栅极1的正投影所覆盖的区域全部被导体化。此时可有效增大源极4、漏极5与有源层3上被导体化部分的接触面积，从而有效减小源极4、漏极5与有源层3上被导体化部分的接触电阻。
需要说明的是，上述有源层3的被源极4、漏极5的正投影所覆盖的区域也被导体化的情况为本公开的可选方案，其不会对本公开的技术方案产生限制。本领域技术人员应该知晓的是，在本公开中仅需使得有源层3上未被栅极1、源极4和漏极5的正投影所覆盖的区域被导体化，即可保证薄膜晶体管的正常工作。
根据本公开的又一个实施例，如图4b所示，源极4和漏极5分别与有源层3接触。与上述实施例不同的是，有源层3、源极4和漏极5可以同层设置，以使得所述有源层的背向所述衬底基板的整个表面不被所述源极和所述漏极覆盖。需要说明的是，图4b中有源层3背向衬底基板16的一侧未被栅极1、源极4和漏极5所覆盖的区域是指，有源层3的在栅极1、漏极4、源极5的延伸方向上除了被栅极1的正投影所覆盖的区域之外的区域。
在该情况下，有源层3与源极4和漏极5彼此不重叠。通过这种方式，可以减小生产成本。
图5a为本公开的一个实施例提供的一种阵列基板的结构示意图，如图5a所示，该阵列基板包括：薄膜晶体管TFT，该薄膜晶体管TFT采用上述实施例中提供的薄膜晶体管(图5a和图5b中仅示例出阵列基板上的薄膜晶体管为图3的薄膜晶体管的情况)，对于该薄膜晶体管TFT的描述可参见上述实施例中的内容，此处不再赘述。
需要说明的是，本实施例中的阵列基板为液晶显示面板(Liquid Crystal Display，简称LCD)中的阵列基板，或者是有机发光二极管面板(Organic Light-Emitting Diode，简称OLED)中的阵列基板。
该阵列基板还包括：钝化层8和导电电极9，其中，钝化层8位于薄膜晶体管背向衬底基板16的一侧，导电电极9位于钝化层8背向衬底基板16的一侧，钝化层8上对应薄膜晶体管的漏极5的区域形成有过孔，导电电极9通过过孔与漏极5连接。
需要说明的是，当该阵列基板为LCD中的阵列基板时，该导电电极9为像素电极；当该阵列基板为OLED中的阵列基板时，该导电电极9为发光二极管的阳极。
当然，本实施例提供的阵列基板还可包括栅线12和数据线11，其中，栅线12与栅极1同层设置，数据线11与源极4同层设置，数据线11直接与源极4连接，栅线12通过导电走线13与栅极1电连接。
在实际制备过程中，可通过一次构图工艺以同时制备出源极4和数据线11，通过一次构图工艺以同时制备出栅极1和栅线12，栅线12的下方存在栅绝缘层2，以使得栅线12和数据线11绝缘。此外，钝化层8上对应栅线12和栅极1的位置也形成有过孔，导电走线13通过过孔与栅线12和栅极1均连接。
本实施例中，导电走线13与导电电极9同层设置，即可通过一次构图工艺以同时制备出导电走线13和导电电极9，从而可大大减少工艺过程中所需掩模板的数量，降低生产成本。
图5b为本公开实施例提供的另一种阵列基板的结构示意图，如图5a所示，当该阵列基板为OLED中的阵列基板，且该阵列基板上的发光器件为底发射发光器件时，则在薄膜晶体管TFT的下方需要设置遮光图形14和绝缘层15。其中，遮光图形14可与薄膜晶体管TFT的源极或漏极连接，以避免遮光图形14悬空(Floating)。可选地，该遮光图形14的材料为金属材料。
本公开实施例还提供了一种显示装置，该显示装置包括阵列基板，该阵列基板采用上述实施例中的阵列基板，对于该阵列基板的描 述可参见上述实施例中的内容，此处不再赘述。
需要说明的是，本实施例中的显示装置可以为：液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
图6为本公开实施例提供的一种薄膜晶体管的制备方法的流程图，图7a～图7f为采用图6所示制备方法制备薄膜晶体管的中间结构示意图，如图6至图7f所示，该制备方法可制备出上述实施例中的薄膜晶体管，该制备方法包括：
步骤S1、在衬底基板上形成源极、漏极和有源层，源极和漏极同层设置并分别与有源层接触。
步骤S1具体包括：
步骤S101、在衬底基板上形成有源层。
参见图7a所示，首先，通过涂覆、磁控溅射或气相沉积工艺在衬底基板16上形成一层有源层材料薄膜，可选地，有源层材料为金属氧化物半导体材料；然后，对该有源层材料薄膜进行构图工艺，以得到有源层3的图形。
需要说明的是，本公开中的构图工艺是指包括光刻胶涂布、曝光、显影、刻蚀、光刻胶剥离等工艺。
步骤S102、在有源层背向衬底基板的一侧形成源极和漏极。
参见图7b所示，首先，通过涂覆、磁控溅射或气相沉积工艺在衬底基板16表面以及有源层3背向衬底基板16的一侧形成一层导电材料薄膜，可选地，该导电材料为金属材料；然后，对该导电材料薄膜进行构图工艺，以得到源极4和漏极5的图形，源极4和漏极5均与有源层3接触。
考虑到在对导电材料薄膜进行构图工艺来制备源极4和漏极5时，往往采用湿法刻蚀，刻蚀液会对位于导电材料薄膜下方的有源层产生误刻蚀。本实施例中，可选地，在步骤S101和步骤S102之间还包括：
步骤S101a、对有源层背向衬底基板的一侧且未被后续形成源极和漏极所覆盖的区域进行激光晶化处理。
通过预先对有源层3上未被后续源极4和漏极5所覆盖的区域进行激光晶化处理，以使得该区域的抗腐蚀性增强，从而避免误刻蚀。
需要说明的是，本实施例中也可先制备源极4和漏极5，然后再制备有源层3(图4a中所示情况)。在这种情况下，步骤S1可包括：在衬底基板16上形成导电材料薄膜；对所述导电材料薄膜进行构图工艺以得到源极4和漏极5的图形；在源极4和漏极5的图形背向衬底基板16的一侧形成有源层材料薄膜；以及对所述有源层材料薄膜进行构图工艺以得到有源层3的图形。
步骤S2、在有源层背向衬底基板的一侧形成栅绝缘层和栅极，栅极位于栅绝缘层背向衬底基板的一侧，栅极、源极、漏极在有源层上的正投影不重叠。
步骤S2具体包括：
步骤S201、在有源层背向衬底基板的一侧形成栅绝缘材料薄膜。
参见图7c所示，通过涂覆、磁控溅射或气相沉积工艺在步骤S1所制备出的衬底基板的表面形成一层栅绝缘材料薄膜2a。其中，栅绝缘材料包括氧化硅、氮化硅中的至少一种。
步骤S202、在栅绝缘材料薄膜背向衬底基板的一侧形成栅导电材料薄膜。
参见图7d所示，通过涂覆、磁控溅射或气相沉积工艺在栅绝缘材料薄膜2a的背向衬底基板16的一侧形成一层栅导电材料薄膜1a。可选地，该导电材料为金属材料。
步骤S203、在栅导电材料薄膜的背向衬底基板的一侧涂布光刻胶。
步骤S204、使用掩模板对光刻胶进行曝光处理，并对曝光处理后的光刻胶进行显影处理，位于待形成栅极的区域的光刻胶完全保留。
参见图7e所示，经过曝光、显影处理后，位于待形成栅极的区域的光刻胶10完全保留。
步骤S205、分别对栅导电材料薄膜和栅绝缘材料薄膜进行刻蚀处理，以得到栅极的图形和栅绝缘层的图形，栅极的图形和栅绝缘层的正投影重叠。
参见图7f所示，首先，通过湿法刻蚀工艺对栅导电材料薄膜进行刻蚀处理，以得到栅极1的图形；然后，通过干法刻蚀工艺对栅绝缘材料薄膜进行刻蚀处理，以得到栅绝缘层2的图形。此时，栅极1的图形和栅绝缘层2的正投影重叠。
在得到栅极1的图形和栅绝缘层2的图形后，再将位于栅极1上方的光刻胶剥离。
步骤S3、对有源层背向衬底基板的一侧未被栅极、源极和漏极的所覆盖的区域进行导体化处理。
参见图7g所示，向步骤S2所制备出的基板的表面注入氢等离子体，有源层3背向衬底基板16的一侧未被栅极1、源极4、漏极5所覆盖的区域(有源层3上被栅极1、源极4、漏极5的正投影所覆盖区域之外的区域)的金属氧化物半导体与氢等离子体接触并反应(氢离子与金属氧化物半导体中的氧离子结合)，该区域的金属氧化物脱氧转换为金属单质，从而具有导电性(即金属氧化物半导体被导体化)。
需要说明的是，若步骤S2中的栅绝缘层2的图形与栅极1的图形不同(栅绝缘层2的图形大于栅极1的图形)，则栅绝缘层2超出栅极1的部分会影响到步骤S3中导体化处理的效果，从而影响了最终成型的薄膜晶体管的电学特性。
图8为有源层3位于源极4和漏极5上方时对有源层进行导体化处理时的示意图，如图8所示，若在步骤S1中先制备源极4、漏极5，再制备有源层3(有源层3位于源极4和漏极5背向衬底基板16的一侧)时，则在步骤S3中进行氢等离子体注入时，有源层3上被源极4、漏极5的正投影所覆盖的区域也会被导体化，此时可有效增大源极4、漏极5与有源层3上被导体化部分的接触面积，从而有效减小源极4、漏极5与有源层3上被导体化部分的接触电阻。
由此可见，在制备本公开提供的薄膜晶体管时，仅需使用三张掩模板：用于制备源/漏极的掩模板、用于制备有源层的掩模板、用于制备栅极/栅绝缘层的掩模板，本公开的技术方案可大大减少生产工艺过程中掩模板的使用数量。
需要补充说明的是，在制备上述实施例中图5a所示的阵列基板时，除了包含上述步骤S1～步骤S3外(栅线与栅极通过一次构图工艺形成，数据线与源/漏极通过一次构图工艺形成)，在步骤S3之后还包括钝化层的制备步骤和导电电极、导电走线的制备步骤。
图9a为在薄膜晶体管上方形成钝化层时的示意图，如图9a所示，在步骤S3所得到的基板上形成钝化层材料薄膜，通过构图工艺在钝化层材料薄膜上对应栅极1、栅线12、漏极5的区域分别形成过孔，剩余的钝化层材料构成钝化层8的图形。
图9b为在钝化层上形成导电电极和导电走线的示意图，如图9b所示，在钝化层8上形成导电材料薄膜，通过构图工艺以形成导电电极9和导电走线13的图形。
由此可见，在制备图5a所示阵列基板时，除了需要使用用于制备薄膜晶体管TFT的上述三张掩模板外，还需要另外两张掩模板：用于在钝化层上形成过孔的掩模板、用于制备导电电极/导电走线的掩模板。即该阵列基板的生产工艺过程中，总共需要使用五张掩模板。
此外，在制备图5b所示阵列基板时，则还需要进行遮光图形和绝缘层的制备，所需要的掩模板的数量相应增多。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (13)

  1. 一种薄膜晶体管，包括：
    源极和漏极，其同层设置并设置在衬底基板上；
    有源层，其设置在所述衬底基板上并与所述源极、漏极接触；
    栅绝缘层，其设置在所述有源层的背向所述衬底基板的一侧；
    栅极，其设置在所述栅绝缘层的背向所述衬底基板的一侧；
    其中，所述栅极、所述源极、所述漏极在所述衬底基板上的正投影不重叠，并且所述有源层背向所述衬底基板的一侧未被所述栅极、所述源极和所述漏极的所覆盖的区域被导体化。
  2. 根据权利要求1所述的薄膜晶体管，其中，所述栅绝缘层的图形与所述栅极的正投影重叠
  3. 根据权利要求1所述的薄膜晶体管，其中，所述栅极和所述源极、所述漏极位于所述有源层的相同侧，并且所述源极的至少一部分和所述漏极的至少一部分在所述有源层的背向所述衬底基板的一侧覆盖所述有源层。
  4. 根据权利要求1所述的薄膜晶体管，其中，所述栅极与所述源极、漏极分别位于所述有源层的相对侧，并且所述有源层的一部分在所述源极的背向所述衬底基板的一侧覆盖所述源极，所述有源层的另一部分在所述漏极的背向所述衬底基板的一侧覆盖所述漏极。
  5. 根据权利要求1所述的薄膜晶体管，其中所述源极、所述漏极和所述有源层同层设置，以使得所述有源层的背向所述衬底基板的整个表面不被所述源极和所述漏极覆盖。
  6. 一种阵列基板，包括：如权利要求1至5中任一项所述的薄膜晶体管。
  7. 根据权利要求6所述的阵列基板，还包括：
    钝化层，其设置在所述薄膜晶体管背向所述衬底基板的一侧；
    导电电极，其设置在所述钝化层背向所述衬底基板的一侧，其中，所述钝化层上对应所述薄膜晶体管的漏极的区域形成有过孔，所述导电电极通过所述过孔与所述漏极连接。
  8. 一种显示装置，包括：如权利要求6或7所述的阵列基板。
  9. 一种薄膜晶体管的制备方法，包括：
    在衬底基板上形成源极、漏极和有源层，所述源极和所述漏极同层设置并且分别与所述有源层接触；
    在所述有源层背向所述衬底基板的一侧形成栅绝缘层；
    在所述栅绝缘层背向所述衬底基板的一侧形成栅极，所述栅极、所述源极、所述漏极在所述衬底基板上的正投影不重叠；以及
    对所述有源层上背向所述衬底基板的一侧未被所述栅极、所述源极和所述漏极所覆盖的区域进行导体化处理。
  10. 根据权利要求9所述的薄膜晶体管的制备方法，其中，形成栅绝缘层和栅极的步骤包括：
    在所述有源层的背向所述衬底基板的形成栅绝缘材料薄膜；
    在所述栅绝缘材料薄膜背向所述衬底基板的一侧形成栅导电材料薄膜；
    在所述栅导电材料薄膜背向所述衬底基板的一侧涂布光刻胶；
    使用掩模板对所述光刻胶进行曝光处理，并对曝光处理后的光刻胶进行显影处理，位于待形成栅极的区域的光刻胶完全保留；
    分别对所述栅导电材料薄膜和栅绝缘材料薄膜进行刻蚀处理，以得到栅极的图形和栅绝缘层的图形，
  11. 根据权利要求10所述的薄膜晶体管的制备方法，其中，所述有源层的材料为金属氧化物半导体；
    所述对所述有源层上背向所述衬底基板的一侧未被所述栅极、所述源极和所述漏极所覆盖的区域进行导体化处理的步骤包括：
    对所述有源层上背向所述衬底基板的一侧未被所述栅极、所述源极和所述漏极所覆盖的区域进行脱氧处理，以使得所述区域的氧化物半导体导体化。
  12. 根据权利要求9所述的薄膜晶体管的制备方法，其中，所述在衬底基板上形成源极、漏极和有源层的步骤包括：
    在衬底基板上形成有源层材料薄膜；
    对所述有源层材料薄膜进行构图工艺以得到有源层的图形；
    对有源层背向所述衬底基板的一侧且未被后续形成的源极和漏极所覆盖的区域进行激光晶化处理；
    在有源层背向衬底基板的一侧形成导电材料薄膜；
    对所述导电材料薄膜进行构图工艺以得到源极和漏极的图形，
    其中，所述源极、所述漏极和所述有源层形成为：所述源极的至少一部分和所述漏极的至少一部分在所述有源层的背向所述衬底基板的一侧覆盖所述有源层。
  13. 根据权利要求9所述的薄膜晶体管的制备方法，其中，所述在衬底基板上形成源极、漏极和有源层的步骤包括：
    在衬底基板上形成导电材料薄膜；
    对所述导电材料薄膜进行构图工艺以得到所述源极的图形和所述漏极的图形；
    在所述源极的图形和所述漏极的图形背向所述衬底基板的一侧形成有源层材料薄膜；以及
    对所述有源层材料薄膜进行构图工艺以得到有源层的图形，
    其中，所述源极、所述漏极和所述有源层形成为：所述有源层的一部分在所述源极的背向所述衬底基板的一侧覆盖所述源极，所述有源层的另一部分在所述漏极的背向所述衬底基板的一侧覆盖所述漏极。
PCT/CN2018/092834 2017-07-04 2018-06-26 薄膜晶体管及其制备方法、阵列基板和显示装置 Ceased WO2019007228A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/620,663 US11257957B2 (en) 2017-07-04 2018-06-26 Thin film transistor, method of fabricating the same, array substrate and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710538052.8A CN107452808B (zh) 2017-07-04 2017-07-04 薄膜晶体管及其制备方法、阵列基板和显示装置
CN201710538052.8 2017-07-04

Publications (1)

Publication Number Publication Date
WO2019007228A1 true WO2019007228A1 (zh) 2019-01-10

Family

ID=60487684

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/092834 Ceased WO2019007228A1 (zh) 2017-07-04 2018-06-26 薄膜晶体管及其制备方法、阵列基板和显示装置

Country Status (3)

Country Link
US (1) US11257957B2 (zh)
CN (1) CN107452808B (zh)
WO (1) WO2019007228A1 (zh)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107452808B (zh) 2017-07-04 2021-10-22 京东方科技集团股份有限公司 薄膜晶体管及其制备方法、阵列基板和显示装置
CN108155245A (zh) * 2017-12-28 2018-06-12 深圳市华星光电半导体显示技术有限公司 薄膜晶体管及其制作方法
CN108461529A (zh) 2018-03-29 2018-08-28 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示装置
CN108630663B (zh) * 2018-04-27 2019-11-05 京东方科技集团股份有限公司 阵列基板及其制备方法、应用和性能改善方法
CN110190028A (zh) * 2019-06-10 2019-08-30 北海惠科光电技术有限公司 薄膜晶体管阵列基板制备方法
CN112002763A (zh) * 2020-08-10 2020-11-27 深圳市华星光电半导体显示技术有限公司 一种tft基板及其制造方法、显示面板
CN111987137A (zh) * 2020-09-10 2020-11-24 深圳市华星光电半导体显示技术有限公司 柔性面板及其制备方法
CN112530978B (zh) * 2020-12-01 2024-02-13 京东方科技集团股份有限公司 开关器件结构及其制备方法、薄膜晶体管膜层、显示面板
CN113193048A (zh) * 2021-04-26 2021-07-30 深圳市华星光电半导体显示技术有限公司 薄膜晶体管及其制备方法
CN113421887A (zh) * 2021-06-15 2021-09-21 合肥维信诺科技有限公司 阵列基板、阵列基板的制备方法及显示面板
CN116314199A (zh) * 2021-12-20 2023-06-23 瀚宇彩晶股份有限公司 显示面板及其制造方法
CN116686091A (zh) * 2021-12-29 2023-09-01 京东方科技集团股份有限公司 显示基板及其制作方法和显示装置
CN114823913A (zh) * 2022-04-14 2022-07-29 广州华星光电半导体显示技术有限公司 显示面板及其制作方法、移动终端
CN115000089B (zh) * 2022-05-27 2025-07-15 合肥鑫晟光电科技有限公司 阵列基板及其制造方法、显示装置
WO2024060211A1 (zh) * 2022-09-23 2024-03-28 北京京东方技术开发有限公司 薄膜晶体管及其制作方法、阵列基板和显示装置
CN116581131B (zh) * 2023-07-10 2024-01-30 惠科股份有限公司 阵列基板及其制备方法、显示面板

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103219391A (zh) * 2013-04-07 2013-07-24 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、阵列基板和显示装置
CN105702744A (zh) * 2016-04-05 2016-06-22 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、阵列基板、显示装置
CN106024813A (zh) * 2016-08-09 2016-10-12 京东方科技集团股份有限公司 一种低温多晶硅tft阵列基板的制作方法及相应装置
US20160329362A1 (en) * 2015-04-14 2016-11-10 Hon Hai Precision Industry Co., Ltd. Thin film transistor and method of making same
CN107452808A (zh) * 2017-07-04 2017-12-08 京东方科技集团股份有限公司 薄膜晶体管及其制备方法、阵列基板和显示装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011135896A1 (ja) * 2010-04-27 2011-11-03 シャープ株式会社 半導体装置及びその製造方法
KR20130107937A (ko) * 2012-03-23 2013-10-02 삼성디스플레이 주식회사 박막 트랜지스터, 이를 포함하는 표시 장치, 및 이의 제조 방법
KR102230943B1 (ko) * 2014-08-14 2021-03-24 엘지디스플레이 주식회사 광흡수층을 포함하는 유기발광 표시장치 및 이를 제조하는 방법
CN104218041B (zh) * 2014-08-15 2017-12-08 京东方科技集团股份有限公司 阵列基板及制备方法和显示装置
KR102308669B1 (ko) * 2014-12-05 2021-10-05 엘지디스플레이 주식회사 유기전계발광 표시장치 및 그 제조방법
CN105932067A (zh) * 2016-06-07 2016-09-07 京东方科技集团股份有限公司 一种顶栅型薄膜晶体管、制备方法、阵列基板及显示面板

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103219391A (zh) * 2013-04-07 2013-07-24 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、阵列基板和显示装置
US20160329362A1 (en) * 2015-04-14 2016-11-10 Hon Hai Precision Industry Co., Ltd. Thin film transistor and method of making same
CN105702744A (zh) * 2016-04-05 2016-06-22 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、阵列基板、显示装置
CN106024813A (zh) * 2016-08-09 2016-10-12 京东方科技集团股份有限公司 一种低温多晶硅tft阵列基板的制作方法及相应装置
CN107452808A (zh) * 2017-07-04 2017-12-08 京东方科技集团股份有限公司 薄膜晶体管及其制备方法、阵列基板和显示装置

Also Published As

Publication number Publication date
CN107452808A (zh) 2017-12-08
US20200176604A1 (en) 2020-06-04
CN107452808B (zh) 2021-10-22
US11257957B2 (en) 2022-02-22

Similar Documents

Publication Publication Date Title
WO2019007228A1 (zh) 薄膜晶体管及其制备方法、阵列基板和显示装置
CN109360828B (zh) 显示基板及其制造方法、显示装置
CN102723269B (zh) 阵列基板及其制作方法、显示装置
CN103715137B (zh) 阵列基板及其制造方法、显示装置
CN109300840B (zh) 显示基板及其制造方法、显示装置
CN104851789B (zh) 薄膜晶体管及制作方法、阵列基板及制作方法和显示装置
WO2021036840A1 (zh) 显示基板及其制造方法、显示装置
CN111415995B (zh) 一种显示面板、其制作方法及显示装置
CN111863841A (zh) 显示基板及其制作方法、显示装置
WO2017024640A1 (zh) 阵列基板及其制造方法
US10217851B2 (en) Array substrate and method of manufacturing the same, and display device
WO2017020480A1 (zh) 薄膜晶体管及阵列基板的制备方法、阵列基板及显示装置
CN107331709A (zh) 薄膜晶体管及其制作方法、显示基板及显示装置
WO2018205886A1 (zh) 薄膜晶体管及其制作方法、阵列基板和显示装置
CN103681514B (zh) 阵列基板及其制作方法、显示装置
WO2025112976A1 (zh) 显示面板及其制作方法、显示装置
WO2020140750A1 (zh) 薄膜晶体管、薄膜晶体管的制作方法以及显示装置
WO2016026207A1 (zh) 阵列基板及其制作方法和显示装置
WO2023226688A1 (zh) 阵列基板及其制造方法、显示装置
CN103413834A (zh) 一种薄膜晶体管及其制作方法、阵列基板及显示装置
CN105529274A (zh) 薄膜晶体管的制作方法、阵列基板和显示装置
CN105374827A (zh) 显示设备和用于制造该显示设备的方法
WO2021097995A1 (zh) 一种阵列基板及其制备方法
CN106449519A (zh) 一种薄膜晶体管及制作方法、显示装置
CN108922868B (zh) 显示基板及其制造方法、显示面板

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18828330

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18828330

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 28/05/2020)

122 Ep: pct application non-entry in european phase

Ref document number: 18828330

Country of ref document: EP

Kind code of ref document: A1

点击 这是indexloc提供的php浏览器服务，不要输入任何密码和下载