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WO2018113214A1 - 薄膜晶体管及其制作方法、显示基板、显示装置 - Google Patents

薄膜晶体管及其制作方法、显示基板、显示装置 Download PDF

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Publication number
WO2018113214A1
WO2018113214A1 PCT/CN2017/088566 CN2017088566W WO2018113214A1 WO 2018113214 A1 WO2018113214 A1 WO 2018113214A1 CN 2017088566 W CN2017088566 W CN 2017088566W WO 2018113214 A1 WO2018113214 A1 WO 2018113214A1
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Prior art keywords
oxide semiconductor
metal oxide
layer
semiconductor layer
thin film
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English (en)
French (fr)
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杨维
宁策
胡合合
王珂
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to US15/737,031 priority Critical patent/US10615284B2/en
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/18, H10D48/04 and H10D48/07, with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
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    • H10D62/86—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group II-VI materials, e.g. ZnO
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
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    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes

Definitions

  • the present disclosure relates to the field of display technologies, and in particular to a thin film transistor and a method of fabricating the same, a display substrate, and a display device.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • Oxide Thin Film Transistor (OTFT) technology is becoming more and more mature. It has high carrier mobility, low power consumption, and can be applied to low frequency driving. And can also be applied to an organic light emitting diode display called the next generation display technology.
  • a source/drain metal layer is deposited on the active layer, and the source/drain metal layer is etched to form a source. Electrode and drain electrode.
  • the etching time of the source/drain metal layer is increased when etching the source/drain metal layer.
  • the etching solution of the source/drain metal layer may damage the back channel of the active layer, so that the stability of the metal oxide thin film transistor is affected.
  • the technical problem to be solved by the present disclosure is to provide a thin film transistor, a method for fabricating the same, a display substrate, and a display device, which can improve the stability of the metal oxide thin film transistor and ensure the display quality of the display device.
  • an embodiment of the present disclosure provides the following technical solutions.
  • a method of fabricating a thin film transistor comprising: forming a metal oxide semiconductor pattern, the metal oxide semiconductor pattern comprising a first metal oxide semiconductor stacked in a stack a layer and a second metal oxide semiconductor layer, the second metal oxide semiconductor layer being over the first metal oxide semiconductor layer; depositing a source/drain metal layer on the metal oxide semiconductor pattern, The source/drain metal layer and the second metal oxide semiconductor layer are etched to form a source electrode, a drain electrode, and an active layer of the thin film transistor, wherein the active layer is used to remove the source by using the first etchant After the second metal oxide semiconductor layer between the electrode and the drain electrode, the first etching liquid etches the second metal oxide semiconductor layer at a higher rate than the first etching The rate at which the liquid etches the first metal oxide semiconductor layer.
  • a ratio of a rate at which the first etchant etches the second MOS layer and a rate at which the first etchant etches the first MOS layer Not less than 10.
  • the source/drain metal layer is deposited on the metal oxide semiconductor pattern, and the source/drain metal layer and the second metal oxide semiconductor layer are etched to form a source electrode and a drain electrode of the thin film transistor.
  • the active layer includes: depositing a source/drain metal layer over the metal oxide semiconductor pattern; coating a photoresist on the source/drain metal layer, exposing the photoresist, and developing a photoresist after development a reserved region and a photoresist-unretained region, wherein the photoresist-retained region corresponds to a region where a source electrode and a drain electrode of the thin film transistor are located, and a photoresist-unretained region corresponds to a source electrode and a drain electrode of the thin film transistor.
  • the second metal oxide semiconductor layer is made of ZnO, ZnON or IZO, the first metal oxide semiconductor layer is IGZO, the first etching liquid is H2O2 etching liquid; or the second metal oxide semiconductor is used.
  • the layer is made of ZnO, ZnON, IZO or IGZO, the first metal oxide semiconductor layer is made of ITZO, IGZTO or IGZXO, and the first etching liquid is made of Al etching liquid.
  • the source/drain metal layer is deposited on the metal oxide semiconductor pattern, and the source/drain metal layer and the second metal oxide semiconductor layer are etched to form a source electrode and a drain electrode of the thin film transistor.
  • the active layer includes: depositing a source and a drain over the metal oxide semiconductor pattern a metal layer; a photoresist is coated on the source/drain metal layer, and the photoresist is exposed to form a photoresist retention region and a photoresist unretained region, wherein the photoresist retention region corresponds to a region where the source electrode and the drain electrode of the thin film transistor are located, a region where the photoresist is not reserved corresponds to a region other than the source electrode and the drain electrode of the thin film transistor; and the source/drain metal layer is etched by the second etching solution, Removing a source/drain metal layer of the unretained region of the photoresist to form a source electrode and a drain electrode of the thin film transistor; and the second metal oxide
  • the second metal oxide semiconductor layer is ZnO, ZnON or IZO
  • the first metal oxide semiconductor layer is IGZO
  • the first etching liquid is H2O2 etching liquid
  • the second metal The oxide semiconductor layer is made of ZnO, ZnON, IZO or IGZO
  • the first metal oxide semiconductor layer is made of ITZO, IGZTO or IGZXO
  • the first etching liquid is made of an Al etching liquid.
  • the source/drain metal layer comprises Cu
  • the second etching liquid is an H2O2 etching liquid; or when the source/drain metal layer comprises Mo or Al, A1Nd, the second etching liquid is a Mo etching agent. liquid.
  • the manufacturing method further includes: providing a substrate; forming a gate electrode of the thin film transistor on the substrate; and forming the gate electrode A gate insulating layer is formed on the base substrate, and the metal oxide semiconductor pattern is formed on the gate insulating layer.
  • the fabricating method further includes: forming a gate insulating layer covering the source electrode, the drain electrode, and the active layer Forming a gate electrode of the thin film transistor on the gate insulating layer.
  • An embodiment of the present disclosure further provides a thin film transistor fabricated by the above-described fabrication method, the active layer of the thin film transistor including a first metal oxide semiconductor layer, and the first metal oxide semiconductor layer and a second metal oxide semiconductor layer between the drain electrodes, and a second metal oxide semiconductor layer between the first metal oxide semiconductor layer and the source electrode.
  • the second metal oxide semiconductor layer is etched by the predetermined etching solution at a higher rate than the first metal oxygen The rate at which the semiconductor layer is etched by a predetermined etchant.
  • Embodiments of the present disclosure also provide a display substrate including the thin film transistor as described above.
  • Embodiments of the present disclosure also provide a display device including the display substrate as described above.
  • the metal oxide semiconductor pattern includes a first metal oxide semiconductor layer and a second metal oxide semiconductor layer which are laminated, and the second metal oxide semiconductor layer is located at the first metal Above the oxide semiconductor layer, after forming the source and drain electrodes of the thin film transistor or after forming the source and drain electrodes of the thin film transistor, the second metal oxide semiconductor layer between the source electrode and the drain electrode can be completely engraved Etched, thus preventing residual conductive ions from remaining on the first metal oxide semiconductor layer (the main structure of the active layer), affecting the characteristics of the thin film transistor; meanwhile, due to the first etching liquid to the second metal oxide The rate at which the semiconductor layer is etched is greater than the rate at which the first etchant etches the first MOS layer, and when the second MOS layer is etched using the first etchant, the second metal The oxide semiconductor layer is relatively easily etched away, and the etching time can be shortened, and the first metal oxide semiconductor layer is not easily Etched
  • FIG. 1 is a schematic view showing formation of a first metal oxide layer and a second metal oxide layer on a base substrate according to an embodiment of the present disclosure
  • FIG. 2 is a schematic view of forming a metal oxide semiconductor pattern according to an embodiment of the present disclosure
  • FIG. 3 is a schematic view showing deposition of a source/drain metal layer according to an embodiment of the present disclosure
  • FIG. 4 is a schematic view showing formation of a source electrode, a drain electrode, and an active layer according to an embodiment of the present disclosure
  • FIG. 5 is a schematic view showing etching of a source/drain metal layer to form a source electrode and a drain electrode according to an embodiment of the present disclosure
  • FIG. 6 is a schematic view of a display substrate according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of a thin film transistor of an embodiment of the present disclosure.
  • the embodiment of the present disclosure is directed to the problem that the etching liquid of the source/drain metal layer is likely to damage the back channel of the active layer, so that the stability of the metal oxide thin film transistor is affected, and the thin film transistor and the manufacturing method thereof are provided.
  • the display substrate and the display device can improve the stability of the metal oxide thin film transistor and ensure the display quality of the display device.
  • Some embodiments of the present disclosure provide a method of fabricating a thin film transistor, including: forming a metal oxide semiconductor pattern including a first metal oxide semiconductor layer and a second metal oxide semiconductor stacked in a stack a layer, the second metal oxide semiconductor layer is located above the first metal oxide semiconductor layer; a source/drain metal layer is deposited on the metal oxide semiconductor pattern, and the source/drain metal layer and the first The MOSFET is etched to form a source electrode, a drain electrode, and an active layer of the thin film transistor, wherein the active layer is between the source electrode and the drain electrode by using a first etchant
  • the first etching liquid etches the second metal oxide semiconductor layer at a higher rate than the first etching liquid oxidizes the first metal The rate at which the semiconductor layer is etched.
  • the metal oxide semiconductor pattern includes a first metal oxide semiconductor layer and a second metal oxide semiconductor layer which are disposed in a stacked manner, and the second metal oxide semiconductor layer is located above the first metal oxide semiconductor layer to form
  • the second metal oxide semiconductor layer between the source electrode and the drain electrode can be completely etched away, thereby avoiding residual Conductive ions remain in the first metal oxidation
  • the characteristics of the thin film transistor are affected by the semiconductor layer (the main structure of the active layer).
  • the first etching liquid is used When the second metal oxide semiconductor layer is etched, the second metal oxide semiconductor layer is relatively easily etched away, and the etching time can be shortened; and the first metal oxide semiconductor layer is not easily etched, and can be reduced.
  • the damage of the first etching solution to the back channel improves the stability of the thin film transistor.
  • a rate at which the first etchant etches the second MOS layer and a rate at which the first etchant etches the first MOS layer is not less than 10.
  • the first etching liquid has little influence on the first metal oxide semiconductor layer, and the first metal oxide semiconductor layer is not damaged substantially when the second metal oxide semiconductor layer is etched by the first etching liquid.
  • the source metal and the drain electrode may be etched by using the first etching solution to form the source electrode and the drain electrode, and the second metal oxide semiconductor layer is etched by the first etching solution to remove the source.
  • a second metal oxide semiconductor layer between the electrode and the drain electrode forms an active layer of the thin film transistor.
  • the source/drain metal layer is deposited on the metal oxide semiconductor pattern, and the source/drain metal layer and the second metal oxide semiconductor layer are etched to form a source electrode of the thin film transistor.
  • the drain electrode and the active layer include: depositing a source/drain metal layer over the metal oxide semiconductor pattern; coating a photoresist on the source/drain metal layer, exposing the photoresist, and developing the photoresist a photoresist retention region and a photoresist unretained region, wherein the photoresist retention region corresponds to a region where the source electrode and the drain electrode of the thin film transistor are located, and the photoresist unretained region corresponds to the source electrode and the drain electrode of the thin film transistor.
  • Other regions than the first metal oxide layer and the second metal oxide semiconductor layer are etched by the first etching liquid to remove the source/drain metal layer and the second metal oxide in the unretained region of the photoresist a semiconductor layer forming a source electrode, a drain electrode, and an active layer of the thin film transistor, the active layer including the first metal oxide semiconductor layer, and the first metal oxide semiconductor The second metal oxide semiconductor layer between the source and the drain, in the second metal oxide semiconductor layer between the first metal oxide semiconductor layer and the source electrode.
  • the second metal oxide semiconductor layer is etched by the first etching solution to remove the second metal between the source electrode and the drain electrode.
  • the oxide semiconductor layer forms an active layer of the thin film transistor.
  • Depositing a source/drain metal layer on the metal oxide semiconductor pattern, etching the source/drain metal layer and the second metal oxide semiconductor layer to form a source electrode, a drain electrode, and an active layer of the thin film transistor includes: depositing a source/drain metal layer over the metal oxide semiconductor pattern; coating a photoresist on the source/drain metal layer, exposing the photoresist to form a photoresist retention region and photolithography a region where the photoresist remaining region corresponds to a region where the source electrode and the drain electrode of the thin film transistor are located, and a region where the photoresist is not reserved corresponds to a region other than the source electrode and the drain electrode of the thin film transistor; Etching the source/drain metal layer to remove the source/drain metal layer of the unretained region of the photoresist to form a source electrode and a drain electrode of the thin film transistor; using the first etching solution to the source electrode and Etching the second metal oxide semiconductor layer between the drain electrode
  • the second metal oxide semiconductor layer is made of ZnO, ZnON or IZO
  • the first metal oxide semiconductor layer is IGZO
  • the first etching liquid is made of H 2 O 2 etching liquid.
  • the second metal oxide semiconductor layer is made of ZnO, ZnON, IZO or IGZO
  • the first metal oxide semiconductor layer is made of ITZO, IGZTO or IGZXO
  • the first etching liquid is made of Al etching liquid.
  • the second etchant is an H 2 O 2 etchant
  • the source/drain metal layer comprises Mo or Al
  • A1Nd the second The etching solution is a Mo etching solution.
  • I represents indium Indium
  • G represents gallium Gallium
  • Z or Zn represents zinc Zinc
  • T represents tin Tin
  • O oxide Oxide
  • X refers to a Sn element or mainly a Sn element and includes other trace elements.
  • the ratio of the rate at which the first etchant etches the second MOS layer to the etch rate of the first etchant to the first MOS layer is relatively large.
  • IZO is used for the second metal oxide semiconductor layer
  • IGZO is used for the first metal oxide semiconductor layer
  • H 2 O 2 etching solution is used for the IZO when the first etching solution is made of H 2 O 2 etching solution.
  • Etching rate can be reached The etch rate for IGZO is only It can be seen that the rate of etching the IZO by the H 2 O 2 etching solution is much higher than the rate of etching the IGZO.
  • IGZO is used for the second metal oxide semiconductor layer
  • IGZXO is used for the first metal oxide semiconductor layer
  • etch rate of the IGZO by the Al etching solution when the first etching solution is made of the Al etching solution. can reach The etch rate for IGZXO is only It can be seen that the etching rate of the IGZO by the Al etching solution is much higher than the etching rate of the IGZXO. Thus, when the second metal oxide semiconductor layer is etched by the first etching liquid, damage to the first metal oxide semiconductor layer is small.
  • the method for fabricating the thin film transistor of the present embodiment may be used to fabricate a bottom gate type thin film transistor.
  • the manufacturing method further includes: providing a substrate; A gate electrode of the thin film transistor is formed on the base substrate; a gate insulating layer is formed on the base substrate on which the gate electrode is formed, wherein the metal oxide semiconductor pattern is formed on the gate insulating layer.
  • the top gate type thin film transistor specifically includes: a substrate 1; a gate electrode 2; a gate insulating layer 3; an active layer on the gate insulating layer 3, the active layer including the first metal oxide semiconductor layer 4 and a second metal oxide semiconductor layer 5; a source electrode 7 and a drain electrode 8.
  • the manufacturing method of the thin film transistor of the embodiment may be used to fabricate a top gate thin film transistor, after the step of forming a source electrode, a drain electrode and an active layer of the thin film transistor, the manufacturing method further includes: forming a cover The source electrode, the drain electrode, and a gate insulating layer of the active layer; a gate electrode of a thin film transistor is formed on the gate insulating layer.
  • the top gate thin film transistor specifically includes: a substrate 1; a buffer layer 11 on the substrate 1; an active layer on the buffer layer 11, the active layer including the first metal oxide semiconductor Layer 4 and second metal oxide semiconductor layer 5; source electrode 7 and drain electrode 8; gate insulating layer 3; and gate electrode 2.
  • the method of fabricating the thin film transistor of this embodiment includes the following steps.
  • Step 1 As shown in FIG. 1, a gate electrode 2, a gate insulating layer 3, a first metal oxide semiconductor layer 4, and a second metal oxide semiconductor layer 5 are formed on a base substrate 1.
  • the base substrate 1 may be a glass substrate or a quartz substrate. Specifically, the thickness of the substrate substrate 1 can be deposited by sputtering or thermal evaporation.
  • the gate metal layer, the gate metal layer may be a metal such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W, and an alloy of these metals, and the gate metal layer may be a single layer structure or multiple layers. Structure, multilayer structure such as Cu ⁇ Mo, Ti ⁇ Cu ⁇ Ti, Mo ⁇ Al ⁇ Mo, etc.
  • a photoresist is coated on the gate metal layer, and the photoresist is exposed by using a mask to form a photoresist unretained region and a photoresist retention region, wherein the photoresist retention region corresponds to In the region where the pattern of the gate electrode is located, the unretained area of the photoresist corresponds to the area other than the above-mentioned pattern; the development process is performed, the photoresist in the unretained area of the photoresist is completely removed, and the thickness of the photoresist in the remaining area of the photoresist is performed. It remains unchanged; the gate metal film of the unretained region of the photoresist is completely etched away by an etching process, and the remaining photoresist is stripped to form a pattern of the gate electrode 2.
  • the thickness can be deposited on the base substrate 1 on which the gate electrode 2 is formed by a plasma enhanced chemical vapor deposition (PECVD) method.
  • PECVD plasma enhanced chemical vapor deposition
  • the gate insulating layer 3, the gate insulating layer 3 may be an oxide, a nitride or an oxynitride compound, and the corresponding reaction gas is SiH 4 , NH 3 , N 2 or SiH 2 Cl 2 , NH 3 , N 2 .
  • a first metal oxide semiconductor layer 4 and a second metal oxide semiconductor layer 5 are deposited on the gate insulating layer 3, and the first metal oxide semiconductor layer 4 and the second metal oxide semiconductor layer 5 satisfy certain requirements, that is, The rate at which the second metal oxide semiconductor layer 5 is etched by a particular etchant is greater than the rate at which the first MOS layer 4 is etched by the particular etchant.
  • the second metal oxide semiconductor layer 5 is etched by a specific etchant at a rate greater than 10 times the rate at which the first MOS layer 4 is etched by the specific etchant.
  • the metal oxide semiconductor and the corresponding etching liquid satisfying such requirements are: 1 the second metal oxide semiconductor layer 5 is IZO, ZnO or ZnON, and the first metal oxide semiconductor layer 4 is IGZO, and the corresponding etching liquid is Hydrogen peroxide (H 2 O 2 ) etching solution (H 2 O 2 etching solution is an etching solution for etching Cu which is currently used for mass production); 2 second metal oxide semiconductor layer 5 is IZO, IGZO, ZnO or ZnON, the first metal oxide semiconductor layer 4 is made of ITZO, IGZTO or IGZXO. Since the acid etching solution is difficult to etch the first metal oxide semiconductor layer 4, the corresponding etching liquid can be selected as Al etching. Etch liquid (the etching solution for etching Al used in mass production at present).
  • Step 2 As shown in FIG. 2, the first metal oxide semiconductor layer 4 and the second metal oxide semiconductor layer 5 are patterned to form an active region pattern.
  • This step may select an etchant having a higher etch rate for both the first metal oxide semiconductor layer 4 and the second metal oxide semiconductor layer 5, the first metal oxide semiconductor layer 4 and the second metal oxide semiconductor layer.
  • 5 etching such as H 2 SO 4 etching solution, HNO 3 etching solution, H 2 O 2 etching solution, etc., and mass production of ITO etching solution.
  • Step 3 As shown in FIG. 3, the source/drain metal layer 6 is deposited on the substrate 1 through the step 2.
  • a thickness of about one layer may be deposited on the base substrate 1 on which the step 2 is completed by magnetron sputtering, thermal evaporation or other film formation methods.
  • the source/drain metal layer 6, the source/drain metal layer may be a metal such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W, and an alloy of these metals.
  • the source/drain metal layer 6 may be a single layer structure or a multilayer structure such as Cu ⁇ Mo, Ti ⁇ Cu ⁇ Ti, Mo ⁇ Al ⁇ Mo or the like.
  • Step 4 as shown in FIG. 4, patterning the source/drain metal layer 6 and the active region pattern to form a source electrode 7, a drain electrode 8 and an active layer of the thin film transistor;
  • a photoresist is coated on the source/drain metal layer 6, and the photoresist is exposed to form a photoresist retention area A and a photoresist unretained area B, wherein the photoresist retention area corresponds to the film.
  • the layer 5 is etched to remove the source/drain metal layer 6 and the second metal oxide semiconductor layer 5 of the unretained region of the photoresist to form the source electrode 7, the drain electrode 8 and the active layer of the thin film transistor, and the active layer includes the a first metal oxide semiconductor layer, a second metal oxide semiconductor layer between the first metal oxide semiconductor layer and the drain electrode, and the first metal oxide semiconductor layer and the source electrode A second metal oxide semiconductor layer between.
  • the rate at which the specific etchant etches the second MOS layer is much greater than the rate at which the first MOS layer is etched, and the rate at which the source/drain metal layer is etched is also compared. Large, such that while the source and drain metal layers are etched using the specific etching solution, the second metal oxide semiconductor layer in the unretained region of the photoresist is also etched away, and the first metal oxide semiconductor The layer is retained because of the slow rate of etching.
  • the rate at which the layer is etched is greater than the rate at which the first etchant etches the first MOS layer, and when the second MOS layer is etched with the etchant, the second MOS
  • the layer is relatively easy to be etched away, and the etching time can be shortened, and the first metal oxide semiconductor layer cannot be tolerated. It is easy to be etched, which can reduce the damage of the specific etching solution to the back channel and improve the stability of the thin film transistor.
  • the thin film transistor of the present embodiment can be fabricated. Then, as shown in FIG. 6, the passivation layer 9 and the pixel electrode 10 are formed on the base substrate 1 on which the thin film transistor is formed, thereby obtaining a display substrate.
  • Step 1 as shown in FIG. 1, forming a gate electrode 2, a gate insulating layer 3, a first metal oxide semiconductor layer 4 and a second metal oxide semiconductor layer 5 on the base substrate 1;
  • the base substrate 1 may be a glass substrate or a quartz substrate. Specifically, the thickness of the substrate substrate 1 can be deposited by sputtering or thermal evaporation.
  • the gate metal layer, the gate metal layer may be a metal such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W, and an alloy of these metals, and the gate metal layer may be a single layer structure or multiple layers. Structure, multilayer structure such as Cu ⁇ Mo, Ti ⁇ Cu ⁇ Ti, Mo ⁇ Al ⁇ Mo, etc.
  • a photoresist is coated on the gate metal layer, and the photoresist is exposed by using a mask to form a photoresist unretained region and a photoresist retention region, wherein the photoresist retention region corresponds to In the region where the pattern of the gate electrode is located, the unretained area of the photoresist corresponds to the area other than the above-mentioned pattern; the development process is performed, the photoresist in the unretained area of the photoresist is completely removed, and the thickness of the photoresist in the remaining area of the photoresist is performed. It remains unchanged; the gate metal film of the unretained region of the photoresist is completely etched away by an etching process, and the remaining photoresist is stripped to form a pattern of the gate electrode 2.
  • the thickness can be deposited on the base substrate 1 on which the gate electrode 2 is formed by a plasma enhanced chemical vapor deposition (PECVD) method.
  • PECVD plasma enhanced chemical vapor deposition
  • the gate insulating layer 3, the gate insulating layer 3 may be an oxide, a nitride or an oxynitride compound, and the corresponding reaction gas is SiH 4 , NH 3 , N 2 or SiH 2 Cl 2 , NH 3 , N 2 .
  • a first metal oxide semiconductor layer 4 and a second metal oxide semiconductor layer 5 are deposited on the gate insulating layer 3, and the first metal oxide semiconductor layer 4 and the second metal oxide semiconductor layer 5 satisfy certain requirements, that is, The rate at which the second metal oxide semiconductor layer 5 is etched by a particular etchant is greater than the rate at which the first MOS layer 4 is etched by the particular etchant.
  • the second metal oxide semiconductor layer 5 is etched by a specific etchant at a rate greater than 10 times the rate at which the first MOS layer 4 is etched by the specific etchant.
  • the metal oxide semiconductor and the corresponding etching liquid satisfying such requirements are: 1 the second metal oxide semiconductor layer 5 is IZO, ZnO or ZnON, and the first metal oxide semiconductor layer 4 is IGZO, and the corresponding etching liquid is Hydrogen peroxide (H 2 O 2 )-based etching solution (H 2 O 2 etching solution is an etching solution for etching Cu which is currently used for mass production); 2 second metal oxide semiconductor layer 5 is IZO, IGZO, ZnO or ZnON, the first metal oxide semiconductor layer 4 is made of ITZO, IGZTO or IGZXO. Since the acid etching solution is difficult to etch the first metal oxide semiconductor layer 4, the corresponding etching liquid can be selected as Al etching. Etch liquid (the etching solution for etching Al used in mass production at present).
  • Step 2 as shown in FIG. 2, patterning the first metal oxide semiconductor layer 4 and the second metal oxide semiconductor layer 5 to form an active area pattern;
  • This step may select an etchant having a higher etch rate for both the first metal oxide semiconductor layer 4 and the second metal oxide semiconductor layer 5, the first metal oxide semiconductor layer 4 and the second metal oxide semiconductor layer.
  • 5 etching such as H 2 SO 4 etching solution, HNO 3 etching solution, H 2 O 2 etching solution, etc., and mass production of ITO etching solution.
  • Step 3 as shown in Figure 3, on the substrate substrate 1 through step 2 deposited source and drain metal layer 6;
  • a thickness of about one layer may be deposited on the base substrate 1 on which the step 2 is completed by magnetron sputtering, thermal evaporation or other film formation methods.
  • the source/drain metal layer 6, the source/drain metal layer may be a metal such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W, and an alloy of these metals.
  • the source/drain metal layer 6 may be a single layer structure or a multilayer structure such as Cu ⁇ Mo, Ti ⁇ Cu ⁇ Ti, Mo ⁇ Al ⁇ Mo or the like.
  • Step 4 as shown in Figure 5, the source and drain metal layer 6 is patterned to form the source electrode 7 and the drain electrode 8 of the thin film transistor;
  • a photoresist is coated on the source/drain metal layer, and the photoresist is exposed to form a photoresist retention area A and a photoresist unretained area B, wherein the photoresist retention area corresponds to The region where the source electrode and the drain electrode of the thin film transistor are located, the region where the photoresist is not reserved corresponds to the region other than the source electrode and the drain electrode of the thin film transistor; the source and drain metal layer is etched by another etching solution to remove The source/drain metal layer of the photoresist is not reserved, and the source electrode 7 and the drain electrode 8 of the thin film transistor are formed; the etching liquid for etching the source/drain metal layer can etch away the source/drain metal layer, but for the second metal The oxide semiconductor layer is etched at a slow rate or substantially cannot etch the second metal oxide semiconductor layer.
  • Step 5 As shown in FIG. 4, the second metal oxide semiconductor layer 5 which is not covered by the source electrode 7 and the drain electrode 8 of the thin film transistor is etched to form an active layer of the thin film transistor.
  • the specific etching solution used in this step etches the second metal oxide semiconductor layer much faster than the first metal oxide semiconductor layer, so that the specific etching solution is utilized. While the second metal oxide semiconductor layer is being etched, the first metal oxide semiconductor layer is retained because of the slow rate of etching.
  • the rate at which the layer is etched is greater than the rate at which the first etchant etches the first MOS layer, and when the second MOS layer is etched with the etchant, the second MOS
  • the layer is relatively easy to be etched away, and the etching time can be shortened.
  • the first metal oxide semiconductor layer is not easily etched, the damage of the specific etching liquid to the back channel can be reduced, and the stability of the thin film transistor can be improved.
  • the thin film transistor of the present embodiment can be fabricated. Then, as shown in FIG. 6, the passivation layer 9 and the pixel electrode 10 are formed on the base substrate 1 on which the thin film transistor is formed, thereby obtaining a display substrate.
  • An embodiment of the present disclosure further provides a thin film transistor fabricated by the above-described fabrication method, the active layer of the thin film transistor including a first metal oxide semiconductor layer, and the first metal oxide semiconductor layer a second metal oxide semiconductor layer between the drain electrode and a second metal oxide semiconductor layer between the first metal oxide semiconductor layer and the source electrode, wherein the second metal oxide semiconductor layer is The rate of the predetermined etching solution etching is greater than the rate at which the first metal oxide semiconductor layer is etched by the predetermined etching solution.
  • the metal oxide semiconductor pattern includes a first metal oxide semiconductor layer and a second metal oxide semiconductor layer which are disposed in a stacked manner, and the second metal oxide semiconductor layer is located above the first metal oxide semiconductor layer to form
  • the second metal oxide semiconductor layer between the source electrode and the drain electrode can be completely etched away, thereby avoiding residual
  • the conductive ions remain on the first metal oxide semiconductor layer (the main structure of the active layer), affecting the characteristics of the thin film transistor; meanwhile, the rate of etching the second metal oxide semiconductor layer by the first etching liquid is greater than that of the first metal oxide semiconductor layer
  • An etching solution etches the first metal oxide semiconductor layer at a rate of oxidizing the second metal with the first etching solution When the semiconductor layer is etched, the second metal oxide semiconductor layer is relatively easily etched, the etching time can be shortened, the first metal oxide semiconductor layer is not easily etched, and the first etching
  • Embodiments of the present disclosure also provide a display substrate including the thin film transistor as described above.
  • the display substrate may further include other components such as a power source, a driving chip, and a light emitting component.
  • Embodiments of the present disclosure also provide a display device including the display substrate as described above.
  • the display device may be any product or component having a display function, such as a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device further includes a flexible circuit board, a printed circuit board, and a backboard.

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Abstract

提供一种薄膜晶体管及其制作方法、显示基板、显示装置，属于显示技术领域。方法包括：形成金属氧化物半导体图形，金属氧化物半导体图形包括第一金属氧化物半导体层（4）和第二金属氧化物半导体层（5），第二金属氧化物半导体层（5）位于第一金属氧化物半导体层（4）上方；在金属氧化物半导体图形上沉积源漏金属层（6），对源漏金属层（6）和第二金属氧化物半导体层（5）进行刻蚀，形成薄膜晶体管的源电极（7）、漏电极（8）和有源层。有源层为利用第一刻蚀液去除源电极（7）和漏电极（8）之间的第二金属氧化物半导体层（5）后得到，第一刻蚀液对第二金属氧化物半导体层（5）进行刻蚀的速率大于对第一金属氧化物半导体层（4）进行刻蚀的速率。

Description

薄膜晶体管及其制作方法、显示基板、显示装置
相关申请的交叉引用
本申请主张在2016年12月23日在中国提交的中国专利申请号No.201611204738.5的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，特别是指一种薄膜晶体管及其制作方法、显示基板、显示装置。
背景技术
在平板显示技术领域，薄膜晶体管显示器(Thin Film Transistor Liquid Crystal Display，简称TFT-LCD)具有体积小、功耗低、制造成本较低等优点，逐渐在当今平板显示市场占据了主导地位。
随着TFT-LCD技术的发展，金属氧化物薄膜晶体管(Oxide Thin Film Transistor，简称OTFT)技术也越来越成熟，它具有载流子迁移率高、功耗低、能应用于低频驱动等优点，而且还能应用在被称为下一代显示技术的有机发光二极管显示器上。
在相关技术中，在制作金属氧化物薄膜晶体管时，在利用金属氧化物制作薄膜晶体管的有源层后，在有源层上沉积源漏金属层，并对源漏金属层进行刻蚀形成源电极和漏电极。为了避免源漏金属层的导电离子残留在沟道区，在进行源漏金属层的刻蚀时会增加对源漏金属层的刻蚀时间。但是，在刻蚀时间增加后，源漏金属层的刻蚀液又会损伤有源层的背沟道，使得金属氧化物薄膜晶体管的稳定性受到影响。
发明内容
本公开要解决的技术问题是提供一种薄膜晶体管及其制作方法、显示基板、显示装置，能够提高金属氧化物薄膜晶体管的稳定性，保证显示装置的显示质量。
为解决上述技术问题，本公开的实施例提供如下技术方案。
一方面，提供一种薄膜晶体管的制作方法，包括：形成金属氧化物半导体图形，所述金属氧化物半导体图形包括层叠设置的第一金属氧化物半导体 层和第二金属氧化物半导体层，所述第二金属氧化物半导体层位于所述第一金属氧化物半导体层的上方；在所述金属氧化物半导体图形上沉积源漏金属层，对所述源漏金属层和所述第二金属氧化物半导体层进行刻蚀，形成薄膜晶体管的源电极、漏电极和有源层，其中，所述有源层为利用第一刻蚀液去除所述源电极和所述漏电极之间的所述第二金属氧化物半导体层后得到，所述第一刻蚀液对所述第二金属氧化物半导体层进行刻蚀的速率大于所述第一刻蚀液对所述第一金属氧化物半导体层进行刻蚀的速率。
进一步地，所述第一刻蚀液对所述第二金属氧化物半导体层进行刻蚀的速率与所述第一刻蚀液对所述第一金属氧化物半导体层进行刻蚀的速率的比值不小于10。
进一步地，所述在所述金属氧化物半导体图形上沉积源漏金属层，对所述源漏金属层和所述第二金属氧化物半导体层进行刻蚀，形成薄膜晶体管的源电极、漏电极和有源层包括：在所述金属氧化物半导体图形上方沉积源漏金属层；在所述源漏金属层上涂覆光刻胶，对所述光刻胶进行曝光，显影后形成光刻胶保留区域和光刻胶未保留区域，其中，所述光刻胶保留区域对应薄膜晶体管的源电极和漏电极所在区域，光刻胶未保留区域对应除薄膜晶体管的源电极和漏电极之外的其他区域；利用第一刻蚀液对所述源漏金属层和所述第二金属氧化物半导体层进行刻蚀，去除光刻胶未保留区域的源漏金属层和第二金属氧化物半导体层，形成薄膜晶体管的源电极、漏电极和有源层，所述有源层包括所述第一金属氧化物半导体层、位于所述第一金属氧化物半导体层与所述漏电极之间的第二金属氧化物半导体层、位于所述第一金属氧化物半导体层与所述源电极之间的第二金属氧化物半导体层。
所述第二金属氧化物半导体层采用ZnO、ZnON或IZO，所述第一金属氧化物半导体层采用IGZO，所述第一刻蚀液采用H2O2刻蚀液；或所述第二金属氧化物半导体层采用ZnO、ZnON、IZO或IGZO，所述第一金属氧化物半导体层采用ITZO、IGZTO或IGZXO，所述第一刻蚀液采用Al刻蚀液。
进一步地，所述在所述金属氧化物半导体图形上沉积源漏金属层，对所述源漏金属层和所述第二金属氧化物半导体层进行刻蚀，形成薄膜晶体管的源电极、漏电极和有源层包括：在所述金属氧化物半导体图形上方沉积源漏 金属层；在所述源漏金属层上涂覆光刻胶，对所述光刻胶进行曝光，形成光刻胶保留区域和光刻胶未保留区域，其中，所述光刻胶保留区域对应薄膜晶体管的源电极和漏电极所在区域，光刻胶未保留区域对应除薄膜晶体管的源电极和漏电极之外的其他区域；利用第二刻蚀液对所述源漏金属层进行刻蚀，去除光刻胶未保留区域的源漏金属层，形成薄膜晶体管的源电极和漏电极；利用第一刻蚀液对所述源电极和所述漏电极之间的所述第二金属氧化物半导体层进行刻蚀，去除所述源电极和所述漏电极之间的所述第二金属氧化物半导体层，形成薄膜晶体管的有源层，所述有源层包括所述第一金属氧化物半导体层、位于所述第一金属氧化物半导体层与所述漏电极之间的第二金属氧化物半导体层、位于所述第一金属氧化物半导体层与所述源电极之间的第二金属氧化物半导体层。
进一步地，所述第二金属氧化物半导体层采用ZnO、ZnON或IZO，所述第一金属氧化物半导体层采用IGZO，所述第一刻蚀液采用H2O2刻蚀液；或所述第二金属氧化物半导体层采用ZnO、ZnON、IZO或IGZO，所述第一金属氧化物半导体层采用ITZO、IGZTO或IGZXO，所述第一刻蚀液采用Al刻蚀液。所述源漏金属层包括Cu时，所述第二刻蚀液为H2O2刻蚀液；或所述源漏金属层包括Mo或Al、A1Nd时，所述第二刻蚀液为Mo刻蚀药液。
进一步地，所述形成金属氧化物半导体图形的步骤之前，所述制作方法还包括：提供一衬底基板；在所述衬底基板上形成薄膜晶体管的栅电极；在形成有所述栅电极的衬底基板上形成栅绝缘层，所述金属氧化物半导体图形形成在所述栅绝缘层上。
进一步地，所述形成薄膜晶体管的源电极、漏电极和有源层的步骤之后，所述制作方法还包括：形成覆盖所述源电极、所述漏电极和所述有源层的栅绝缘层；在所述栅绝缘层上形成薄膜晶体管的栅电极。
本公开实施例还提供了一种薄膜晶体管，采用如上所述的制作方法制作得到，所述薄膜晶体管的有源层包括第一金属氧化物半导体层、位于所述第一金属氧化物半导体层与漏电极之间的第二金属氧化物半导体层、位于所述第一金属氧化物半导体层与源电极之间的第二金属氧化物半导体层。其中，所述第二金属氧化物半导体层被预设刻蚀液刻蚀的速率大于所述第一金属氧 化物半导体层被预设刻蚀液刻蚀的速率。
本公开实施例还提供了一种显示基板，包括如上所述的薄膜晶体管。
本公开实施例还提供了一种显示装置，包括如上所述的显示基板。
本公开的实施例具有以下有益效果：上述方案中，金属氧化物半导体图形包括层叠设置的第一金属氧化物半导体层和第二金属氧化物半导体层，第二金属氧化物半导体层位于第一金属氧化物半导体层的上方，在形成薄膜晶体管的源电极和漏电极时或者在形成薄膜晶体管的源电极和漏电极后，可以把源电极和漏电极之间的第二金属氧化物半导体层完全刻蚀掉，这样就能避免残留的导电离子留在第一金属氧化物半导体层(有源层的主体结构)上，影响薄膜晶体管的特性；同时，由于第一刻蚀液对第二金属氧化物半导体层进行刻蚀的速率大于第一刻蚀液对第一金属氧化物半导体层进行刻蚀的速率，在利用第一刻蚀液对第二金属氧化物半导体层进行刻蚀时，第二金属氧化物半导体层会比较容易被刻蚀掉，能够缩短刻蚀时间，第一金属氧化物半导体层不容易被刻蚀掉，可以减小第一刻蚀液对背沟道的损伤，提高薄膜晶体管的稳定性。
附图说明
图1为本公开实施例在衬底基板上形成第一金属氧化物层和第二金属氧化物层的示意图；
图2为本公开实施例形成金属氧化物半导体图形的示意图；
图3为本公开实施例沉积源漏金属层的示意图；
图4为本公开实施例形成源电极、漏电极及有源层的示意图；
图5为本公开实施例对源漏金属层进行刻蚀形成源电极和漏电极的示意图；
图6为本公开实施例显示基板的示意图；
图7为本公开实施例薄膜晶体管的示意图。
附图标记
1衬底基板 2栅电极 3栅绝缘层 4第一金属氧化物半导体层 5第二金属氧化物半导体层 6源漏金属层 7源电极 8漏电极 9钝化层 10像素电极 11缓冲层
具体实施方式
为使本公开的实施例要解决的技术问题、技术方案和优点更加清楚，下面将结合附图及具体实施例进行详细描述。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也相应地改变。
本公开的实施例针对相关技术中源漏金属层的刻蚀液容易损伤有源层的背沟道，使得金属氧化物薄膜晶体管的稳定性受到影响的问题，提供一种薄膜晶体管及其制作方法、显示基板、显示装置，能够提高金属氧化物薄膜晶体管的稳定性，保证显示装置的显示质量。
本公开的一些实施例提供了一种薄膜晶体管的制作方法，包括：形成金属氧化物半导体图形，所述金属氧化物半导体图形包括层叠设置的第一金属氧化物半导体层和第二金属氧化物半导体层，所述第二金属氧化物半导体层位于所述第一金属氧化物半导体层的上方；在所述金属氧化物半导体图形上沉积源漏金属层，对所述源漏金属层和所述第二金属氧化物半导体层进行刻蚀，形成薄膜晶体管的源电极、漏电极和有源层，其中，所述有源层为利用第一刻蚀液去除所述源电极和所述漏电极之间的所述第二金属氧化物半导体层后得到，所述第一刻蚀液对所述第二金属氧化物半导体层进行刻蚀的速率大于所述第一刻蚀液对所述第一金属氧化物半导体层进行刻蚀的速率。
本实施例中，金属氧化物半导体图形包括层叠设置的第一金属氧化物半导体层和第二金属氧化物半导体层，第二金属氧化物半导体层位于第一金属氧化物半导体层的上方，在形成薄膜晶体管的源电极和漏电极时或者在形成薄膜晶体管的源电极和漏电极后，可以把源电极和漏电极之间的第二金属氧化物半导体层完全刻蚀掉，这样就能避免残留的导电离子留在第一金属氧化 物半导体层(有源层的主体结构)上影响薄膜晶体管的特性。同时，由于第一刻蚀液对第二金属氧化物半导体层进行刻蚀的速率大于第一刻蚀液对第一金属氧化物半导体层进行刻蚀的速率，在利用第一刻蚀液对第二金属氧化物半导体层进行刻蚀时，第二金属氧化物半导体层会比较容易被刻蚀掉，能够缩短刻蚀时间；而第一金属氧化物半导体层不容易被刻蚀掉，可以减小第一刻蚀液对背沟道的损伤，提高薄膜晶体管的稳定性。
可选地，所述第一刻蚀液对所述第二金属氧化物半导体层进行刻蚀的速率与所述第一刻蚀液对所述第一金属氧化物半导体层进行刻蚀的速率的比值不小于10。这样第一刻蚀液对第一金属氧化物半导体层的影响很小，在利用第一刻蚀液对第二金属氧化物半导体层进行刻蚀时，基本不会损伤第一金属氧化物半导体层。
具体实施例中，可以在利用第一刻蚀液对源漏金属层进行刻蚀形成源电极和漏电极的同时，利用第一刻蚀液对第二金属氧化物半导体层进行刻蚀，去除源电极和漏电极之间的第二金属氧化物半导体层，形成薄膜晶体管的有源层。在本实施例中，所述在所述金属氧化物半导体图形上沉积源漏金属层，对所述源漏金属层和所述第二金属氧化物半导体层进行刻蚀，形成薄膜晶体管的源电极、漏电极和有源层包括：在所述金属氧化物半导体图形上方沉积源漏金属层；在所述源漏金属层上涂覆光刻胶，对所述光刻胶进行曝光，显影后形成光刻胶保留区域和光刻胶未保留区域，其中，所述光刻胶保留区域对应薄膜晶体管的源电极和漏电极所在区域，光刻胶未保留区域对应除薄膜晶体管的源电极和漏电极之外的其他区域；利用第一刻蚀液对所述源漏金属层和所述第二金属氧化物半导体层进行刻蚀，去除光刻胶未保留区域的源漏金属层和第二金属氧化物半导体层，形成薄膜晶体管的源电极、漏电极和有源层，所述有源层包括所述第一金属氧化物半导体层、位于所述第一金属氧化物半导体层与所述漏电极之间的第二金属氧化物半导体层、位于所述第一金属氧化物半导体层与所述源电极之间的第二金属氧化物半导体层。
另一具体实施例中，可以在形成薄膜晶体管的源电极和漏电极之后，利用第一刻蚀液对第二金属氧化物半导体层进行刻蚀，去除源电极和漏电极之间的第二金属氧化物半导体层，形成薄膜晶体管的有源层。在本实施例中， 所述在所述金属氧化物半导体图形上沉积源漏金属层，对所述源漏金属层和所述第二金属氧化物半导体层进行刻蚀，形成薄膜晶体管的源电极、漏电极和有源层包括：在所述金属氧化物半导体图形上方沉积源漏金属层；在所述源漏金属层上涂覆光刻胶，对所述光刻胶进行曝光，形成光刻胶保留区域和光刻胶未保留区域，其中，所述光刻胶保留区域对应薄膜晶体管的源电极和漏电极所在区域，光刻胶未保留区域对应除薄膜晶体管的源电极和漏电极之外的其他区域；利用第二刻蚀液对所述源漏金属层进行刻蚀，去除光刻胶未保留区域的源漏金属层，形成薄膜晶体管的源电极和漏电极；利用第一刻蚀液对所述源电极和所述漏电极之间的所述第二金属氧化物半导体层进行刻蚀，去除所述源电极和所述漏电极之间的所述第二金属氧化物半导体层，形成薄膜晶体管的有源层，其中，所述有源层包括所述第一金属氧化物半导体层、位于所述第一金属氧化物半导体层与所述漏电极之间的第二金属氧化物半导体层、位于所述第一金属氧化物半导体层与所述源电极之间的第二金属氧化物半导体层。
进一步地，所述第二金属氧化物半导体层采用ZnO、ZnON或IZO，所述第一金属氧化物半导体层采用IGZO，所述第一刻蚀液采用H2O2刻蚀液。可选地，所述第二金属氧化物半导体层采用ZnO、ZnON、IZO或IGZO，所述第一金属氧化物半导体层采用ITZO、IGZTO或IGZXO，所述第一刻蚀液采用Al刻蚀液。可选地，当所述源漏金属层包括Cu时，所述第二刻蚀液为H2O2刻蚀液；当所述源漏金属层包括Mo或Al、A1Nd时，所述第二刻蚀液为Mo刻蚀药液。这里的I表示铟Indium，G表示镓Gallium，Z或者Zn表示锌Zinc，T表示锡Tin，O表示氧化物Oxide，X指的是Sn元素或主要为Sn元素还包括其他微量元素。
在采用上述组合后，第一刻蚀液对第二金属氧化物半导体层进行刻蚀的速率与第一刻蚀液对第一金属氧化物半导体层进行刻蚀的速率的比值会比较大。
具体实施例中，在第二金属氧化物半导体层采用IZO，第一金属氧化物半导体层采用IGZO，第一刻蚀液采用H2O2刻蚀液时，H2O2刻蚀液对IZO的刻蚀速率可以达到
Figure PCTCN2017088566-appb-000001
而对IGZO的刻蚀速率仅为
Figure PCTCN2017088566-appb-000002
可以看出， H2O2刻蚀液对IZO进行刻蚀的速率远大于对IGZO进行刻蚀的速率。再一具体实施例中，在第二金属氧化物半导体层采用IGZO，第一金属氧化物半导体层采用IGZXO，第一刻蚀液采用Al刻蚀液时，Al刻蚀液对IGZO的刻蚀速率可以达到
Figure PCTCN2017088566-appb-000003
而对IGZXO的刻蚀速率仅为
Figure PCTCN2017088566-appb-000004
可以看出，Al刻蚀液对IGZO进行刻蚀的速率远大于对IGZXO进行刻蚀的速率。这样在利用第一刻蚀液对第二金属氧化物半导体层进行刻蚀时，对第一金属氧化物半导体层的损害很小。
进一步地，本实施例的薄膜晶体管的制作方法可以用以制作底栅型薄膜晶体管，所述形成金属氧化物半导体图形的步骤之前，所述制作方法还包括：提供一衬底基板；在所述衬底基板上形成薄膜晶体管的栅电极；在形成有所述栅电极的衬底基板上形成栅绝缘层，其中，所述金属氧化物半导体图形形成在所述栅绝缘层上。
如图5所示，顶栅型薄膜晶体管具体包括：衬底基板1；栅电极2；栅绝缘层3；位于栅绝缘层3上的有源层，有源层包括第一金属氧化物半导体层4和第二金属氧化物半导体层5；源电极7和漏电极8。
进一步地，本实施例的薄膜晶体管的制作方法可以用以制作顶栅型薄膜晶体管，所述形成薄膜晶体管的源电极、漏电极和有源层的步骤之后，所述制作方法还包括：形成覆盖所述源电极、所述漏电极和所述有源层的栅绝缘层；在所述栅绝缘层上形成薄膜晶体管的栅电极。
如图7所示，顶栅型薄膜晶体管具体包括：衬底基板1；位于衬底基板1上的缓冲层11；位于缓冲层11上的有源层，有源层包括第一金属氧化物半导体层4和第二金属氧化物半导体层5；源电极7和漏电极8；栅绝缘层3；以及栅电极2。
下面结合附图对本公开的薄膜晶体管的制作方法进行进一步介绍。
本实施例的薄膜晶体管的制作方法包括以下步骤。
步骤1：如图1所示，在衬底基板1上形成栅电极2、栅绝缘层3、第一金属氧化物半导体层4和第二金属氧化物半导体层5。
其中，衬底基板1可为玻璃基板或石英基板。具体地，可以采用溅射或热蒸发的方法在衬底基板1上沉积厚度约为
Figure PCTCN2017088566-appb-000005
的栅金属层，栅金 属层可以是Cu，Al，Ag，Mo，Cr，Nd，Ni，Mn，Ti，Ta，W等金属以及这些金属的合金，栅金属层可以为单层结构或者多层结构，多层结构比如Cu\Mo，Ti\Cu\Ti，Mo\Al\Mo等。在栅金属层上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光，使光刻胶形成光刻胶未保留区域和光刻胶保留区域，其中，光刻胶保留区域对应于栅电极的图形所在区域，光刻胶未保留区域对应于上述图形以外的区域；进行显影处理，光刻胶未保留区域的光刻胶被完全去除，光刻胶保留区域的光刻胶厚度保持不变；通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的栅金属薄膜，剥离剩余的光刻胶，形成栅电极2的图形。
之后可以采用等离子体增强化学气相沉积(PECVD)方法在形成栅电极2的衬底基板1上沉积厚度为
Figure PCTCN2017088566-appb-000006
的栅绝缘层3，栅绝缘层3可以选用氧化物、氮化物或者氧氮化合物，对应的反应气体是SiH4、NH3、N2或SiH2Cl2、NH3、N2。
之后在栅绝缘层3上沉积第一金属氧化物半导体层4和第二金属氧化物半导体层5，第一金属氧化物半导体层4和第二金属氧化物半导体层5满足一定的要求，即第二金属氧化物半导体层5被某一特定刻蚀液进行刻蚀的速率大于第一金属氧化物半导体层4被该特定刻蚀液进行刻蚀的速率。可选地，第二金属氧化物半导体层5被某一特定刻蚀液进行刻蚀的速率大于第一金属氧化物半导体层4被该特定刻蚀液进行刻蚀的速率的10倍。满足这种要求的金属氧化物半导体和对应的刻蚀液有：①第二金属氧化物半导体层5为IZO、ZnO或ZnON，第一金属氧化物半导体层4为IGZO，对应的刻蚀液为双氧水(H2O2)系刻蚀液(H2O2刻蚀液即目前产线量产使用的对Cu进行刻蚀的刻蚀液)；②第二金属氧化物半导体层5采用IZO、IGZO、ZnO或ZnON，第一金属氧化物半导体层4采用ITZO、IGZTO或IGZXO，因酸系刻蚀液较难刻蚀第一金属氧化物半导体层4，所以对应的刻蚀液可以选择Al刻蚀液(目前产线量产使用的对Al进行刻蚀的刻蚀液)。
步骤2、如图2所示，对第一金属氧化物半导体层4和第二金属氧化物半导体层5进行构图，形成有源区图形。
该步骤可以选择对第一金属氧化物半导体层4和第二金属氧化物半导体层5都具有较高刻蚀速率的刻蚀液对第一金属氧化物半导体层4和第二金属 氧化物半导体层5进行刻蚀，比如H2SO4刻蚀液、HNO3刻蚀液、H2O2刻蚀液等，还有量产使用的ITO刻蚀液。
步骤3、如图3所示，在经过步骤2的衬底基板1上沉积源漏金属层6。
具体地，可以在完成步骤2的衬底基板1上采用磁控溅射、热蒸发或其它成膜方法沉积一层厚度约为
Figure PCTCN2017088566-appb-000007
的源漏金属层6，源漏金属层可以是Cu，Al，Ag，Mo，Cr，Nd，Ni，Mn，Ti，Ta，W等金属以及这些金属的合金。源漏金属层6可以是单层结构或者多层结构，多层结构比如Cu\Mo，Ti\Cu\Ti，Mo\Al\Mo等。
步骤4、如图4所示，对源漏金属层6和有源区图形进行构图，形成薄膜晶体管的源电极7、漏电极8和有源层；
具体地，在源漏金属层6上涂覆光刻胶，对光刻胶进行曝光，显影后形成光刻胶保留区域A和光刻胶未保留区域B，其中，光刻胶保留区域对应薄膜晶体管的源电极和漏电极所在区域，光刻胶未保留区域对应除薄膜晶体管的源电极和漏电极之外的其他区域；利用特定刻蚀液对源漏金属层6和第二金属氧化物半导体层5进行刻蚀，去除光刻胶未保留区域的源漏金属层6和第二金属氧化物半导体层5，形成薄膜晶体管的源电极7、漏电极8和有源层，有源层包括所述第一金属氧化物半导体层、位于所述第一金属氧化物半导体层与所述漏电极之间的第二金属氧化物半导体层、位于所述第一金属氧化物半导体层与所述源电极之间的第二金属氧化物半导体层。
其中，该特定的刻蚀液对第二金属氧化物半导体层进行刻蚀的速率远大于对第一金属氧化物半导体层进行刻蚀的速率，且对源漏金属层进行刻蚀的速率也比较大，这样在利用该特定的刻蚀液对源漏金属层进行刻蚀的同时，光刻胶未保留区域的第二金属氧化物半导体层也会被刻蚀掉，而第一金属氧化物半导体层因为被刻蚀的速率慢，得以保留。这样就能避免残留的源漏金属层离子留在第一金属氧化物半导体层(有源层的主体结构)上，影响薄膜晶体管的特性；同时，由于特定刻蚀液对第二金属氧化物半导体层进行刻蚀的速率大于特定刻蚀液对第一金属氧化物半导体层进行刻蚀的速率，在利用特定刻蚀液对第二金属氧化物半导体层进行刻蚀时，第二金属氧化物半导体层会比较容易被刻蚀掉，能够缩短刻蚀时间，第一金属氧化物半导体层不容 易被刻蚀掉，可以减小特定刻蚀液对背沟道的损伤，提高薄膜晶体管的稳定性。
经过上述步骤即可制作得到本实施例的薄膜晶体管，之后如图6所示，再在形成有薄膜晶体管的衬底基板1上形成钝化层9和像素电极10，即可得到显示基板。
下面结合附图对本公开的薄膜晶体管的制作方法进行进一步介绍。
本实施例的薄膜晶体管的制作方法包括以下步骤：
步骤1：如图1所示，在衬底基板1上形成栅电极2、栅绝缘层3、第一金属氧化物半导体层4和第二金属氧化物半导体层5；
其中，衬底基板1可为玻璃基板或石英基板。具体地，可以采用溅射或热蒸发的方法在衬底基板1上沉积厚度约为
Figure PCTCN2017088566-appb-000008
的栅金属层，栅金属层可以是Cu，Al，Ag，Mo，Cr，Nd，Ni，Mn，Ti，Ta，W等金属以及这些金属的合金，栅金属层可以为单层结构或者多层结构，多层结构比如Cu\Mo，Ti\Cu\Ti，Mo\Al\Mo等。在栅金属层上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光，使光刻胶形成光刻胶未保留区域和光刻胶保留区域，其中，光刻胶保留区域对应于栅电极的图形所在区域，光刻胶未保留区域对应于上述图形以外的区域；进行显影处理，光刻胶未保留区域的光刻胶被完全去除，光刻胶保留区域的光刻胶厚度保持不变；通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的栅金属薄膜，剥离剩余的光刻胶，形成栅电极2的图形。
之后可以采用等离子体增强化学气相沉积(PECVD)方法在形成栅电极2的衬底基板1上沉积厚度为
Figure PCTCN2017088566-appb-000009
的栅绝缘层3，栅绝缘层3可以选用氧化物、氮化物或者氧氮化合物，对应的反应气体是SiH4、NH3、N2或SiH2Cl2、NH3、N2。
之后在栅绝缘层3上沉积第一金属氧化物半导体层4和第二金属氧化物半导体层5，第一金属氧化物半导体层4和第二金属氧化物半导体层5满足一定的要求，即第二金属氧化物半导体层5被某一特定刻蚀液进行刻蚀的速率大于第一金属氧化物半导体层4被该特定刻蚀液进行刻蚀的速率。可选地，第二金属氧化物半导体层5被某一特定刻蚀液进行刻蚀的速率大于第一金属氧化物半导体层4被该特定刻蚀液进行刻蚀的速率的10倍。满足这种要求的 金属氧化物半导体和对应的刻蚀液有：①第二金属氧化物半导体层5为IZO、ZnO或ZnON，第一金属氧化物半导体层4为IGZO，对应的刻蚀液为双氧水(H2O2)系刻蚀液(H2O2刻蚀液即目前产线量产使用的对Cu进行刻蚀的刻蚀液)；②第二金属氧化物半导体层5为IZO、IGZO、ZnO或ZnON，第一金属氧化物半导体层4采用ITZO、IGZTO或IGZXO，因酸系刻蚀液较难刻蚀第一金属氧化物半导体层4，所以对应的刻蚀液可以选择Al刻蚀液(目前产线量产使用的对Al进行刻蚀的刻蚀液)。
步骤2、如图2所示，对第一金属氧化物半导体层4和第二金属氧化物半导体层5进行构图，形成有源区图形；
该步骤可以选择对第一金属氧化物半导体层4和第二金属氧化物半导体层5都具有较高刻蚀速率的刻蚀液对第一金属氧化物半导体层4和第二金属氧化物半导体层5进行刻蚀，比如H2SO4刻蚀液、HNO3刻蚀液、H2O2刻蚀液等，还有量产使用的ITO刻蚀液。
步骤3、如图3所示，在经过步骤2的衬底基板1上沉积源漏金属层6；
具体地，可以在完成步骤2的衬底基板1上采用磁控溅射、热蒸发或其它成膜方法沉积一层厚度约为
Figure PCTCN2017088566-appb-000010
的源漏金属层6，源漏金属层可以是Cu，Al，Ag，Mo，Cr，Nd，Ni，Mn，Ti，Ta，W等金属以及这些金属的合金。源漏金属层6可以是单层结构或者多层结构，多层结构比如Cu\Mo，Ti\Cu\Ti，Mo\Al\Mo等。
步骤4、如图5所示，对源漏金属层6进行构图，形成薄膜晶体管的源电极7和漏电极8；
具体地，在源漏金属层上涂覆光刻胶，对所述光刻胶进行曝光，形成光刻胶保留区域A和光刻胶未保留区域B，其中，所述光刻胶保留区域对应薄膜晶体管的源电极和漏电极所在区域，光刻胶未保留区域对应除薄膜晶体管的源电极和漏电极之外的其他区域；利用另一种刻蚀液对源漏金属层进行刻蚀，去除光刻胶未保留区域的源漏金属层，形成薄膜晶体管的源电极7和漏电极8；对源漏金属层进行刻蚀的刻蚀液能够刻蚀掉源漏金属层，但是对第二金属氧化物半导体层进行刻蚀的速率很慢或者基本不能刻蚀第二金属氧化物半导体层。
步骤5、如图4所示，对未被薄膜晶体管的源电极7和漏电极8覆盖的第二金属氧化物半导体层5进行刻蚀，形成薄膜晶体管的有源层。
该步骤中所使用的特定刻蚀液对第二金属氧化物半导体层进行刻蚀的速率远大于对第一金属氧化物半导体层进行刻蚀的速率，这样在利用该特定的刻蚀液对第二金属氧化物半导体层进行刻蚀的同时，第一金属氧化物半导体层因为被刻蚀的速率慢，得以保留。这样就能避免残留的源漏金属层离子留在第一金属氧化物半导体层(有源层的主体结构)上，影响薄膜晶体管的特性；同时，由于特定刻蚀液对第二金属氧化物半导体层进行刻蚀的速率大于特定刻蚀液对第一金属氧化物半导体层进行刻蚀的速率，在利用特定刻蚀液对第二金属氧化物半导体层进行刻蚀时，第二金属氧化物半导体层会比较容易被刻蚀掉，能够缩短刻蚀时间，第一金属氧化物半导体层不容易被刻蚀掉，可以减小特定刻蚀液对背沟道的损伤，提高薄膜晶体管的稳定性。
经过上述步骤即可制作得到本实施例的薄膜晶体管，之后如图6所示，再在形成有薄膜晶体管的衬底基板1上形成钝化层9和像素电极10，即可得到显示基板。
本公开的实施例还提供了一种薄膜晶体管，采用如上所述的制作方法制作得到，所述薄膜晶体管的有源层包括第一金属氧化物半导体层、位于所述第一金属氧化物半导体层与漏电极之间的第二金属氧化物半导体层、位于所述第一金属氧化物半导体层与源电极之间的第二金属氧化物半导体层，其中，所述第二金属氧化物半导体层被预设刻蚀液刻蚀的速率大于所述第一金属氧化物半导体层被预设刻蚀液刻蚀的速率。
本实施例中，金属氧化物半导体图形包括层叠设置的第一金属氧化物半导体层和第二金属氧化物半导体层，第二金属氧化物半导体层位于第一金属氧化物半导体层的上方，在形成薄膜晶体管的源电极和漏电极时或者在形成薄膜晶体管的源电极和漏电极后，可以把源电极和漏电极之间的第二金属氧化物半导体层完全刻蚀掉，这样就能避免残留的导电离子留在第一金属氧化物半导体层(有源层的主体结构)上，影响薄膜晶体管的特性；同时，由于第一刻蚀液对第二金属氧化物半导体层进行刻蚀的速率大于第一刻蚀液对第一金属氧化物半导体层进行刻蚀的速率，在利用第一刻蚀液对第二金属氧化 物半导体层进行刻蚀时，第二金属氧化物半导体层会比较容易被刻蚀掉，能够缩短刻蚀时间，第一金属氧化物半导体层不容易被刻蚀掉，可以减小第一刻蚀液对背沟道的损伤，提高薄膜晶体管的稳定性。
本公开实施例还提供了一种显示基板，包括如上所述的薄膜晶体管。该显示基板还可以包括电源、驱动芯片以及发光组件等其它组件
本公开实施例还提供了一种显示装置，包括如上所述的显示基板。所述显示装置可以为：液晶电视、液晶显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件，其中，所述显示装置还包括柔性电路板、印刷电路板和背板。
以上所述是本公开的可选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (11)

  1. 一种薄膜晶体管的制作方法，包括：
    形成金属氧化物半导体图形，所述金属氧化物半导体图形包括层叠设置的第一金属氧化物半导体层和第二金属氧化物半导体层，所述第二金属氧化物半导体层位于所述第一金属氧化物半导体层的上方；
    在所述金属氧化物半导体图形上沉积源漏金属层，
    对所述源漏金属层和所述第二金属氧化物半导体层进行刻蚀，形成薄膜晶体管的源电极、漏电极和有源层，
    其中，所述有源层为利用第一刻蚀液去除所述源电极和所述漏电极之间的所述第二金属氧化物半导体层后得到，所述第一刻蚀液对所述第二金属氧化物半导体层进行刻蚀的速率大于所述第一刻蚀液对所述第一金属氧化物半导体层进行刻蚀的速率。
  2. 根据权利要求1所述的薄膜晶体管的制作方法，其中，所述第一刻蚀液对所述第二金属氧化物半导体层进行刻蚀的速率与所述第一刻蚀液对所述第一金属氧化物半导体层进行刻蚀的速率的比值不小于10。
  3. 根据权利要求1所述的薄膜晶体管的制作方法，其中，所述在所述金属氧化物半导体图形上沉积源漏金属层，对所述源漏金属层和所述第二金属氧化物半导体层进行刻蚀，形成薄膜晶体管的源电极、漏电极和有源层包括：
    在所述金属氧化物半导体图形上方沉积源漏金属层；
    在所述源漏金属层上涂覆光刻胶，对所述光刻胶进行曝光，显影后形成光刻胶保留区域和光刻胶未保留区域，其中，所述光刻胶保留区域对应薄膜晶体管的源电极和漏电极所在区域，光刻胶未保留区域对应除薄膜晶体管的源电极和漏电极之外的其他区域；
    利用第一刻蚀液对所述源漏金属层和所述第二金属氧化物半导体层进行刻蚀，去除光刻胶未保留区域的源漏金属层和第二金属氧化物半导体层，形成薄膜晶体管的源电极、漏电极和有源层，其中，所述有源层包括所述第一金属氧化物半导体层、位于所述第一金属氧化物半导体层与所述漏电极之间的第二金属氧化物半导体层、位于所述第一金属氧化物半导体层与所述源电 极之间的第二金属氧化物半导体层。
  4. 根据权利要求3所述的薄膜晶体管的制作方法，其中，
    所述第二金属氧化物半导体层采用ZnO、ZnON或IZO，所述第一金属氧化物半导体层采用IGZO，所述第一刻蚀液采用H2O2刻蚀液；或
    所述第二金属氧化物半导体层采用ZnO、ZnON、IZO或IGZO，所述第一金属氧化物半导体层采用ITZO、IGZTO或IGZXO，其中，X为Sn元素，所述第一刻蚀液采用Al刻蚀液。
  5. 根据权利要求1所述的薄膜晶体管的制作方法，其中，所述在所述金属氧化物半导体图形上沉积源漏金属层，对所述源漏金属层和所述第二金属氧化物半导体层进行刻蚀，形成薄膜晶体管的源电极、漏电极和有源层包括：
    在所述金属氧化物半导体图形上方沉积源漏金属层；
    在所述源漏金属层上涂覆光刻胶，对所述光刻胶进行曝光，形成光刻胶保留区域和光刻胶未保留区域，其中，所述光刻胶保留区域对应薄膜晶体管的源电极和漏电极所在区域，光刻胶未保留区域对应除薄膜晶体管的源电极和漏电极之外的其他区域；
    利用第二刻蚀液对所述源漏金属层进行刻蚀，去除光刻胶未保留区域的源漏金属层，形成薄膜晶体管的源电极和漏电极；
    利用第一刻蚀液对所述源电极和所述漏电极之间的所述第二金属氧化物半导体层进行刻蚀，去除所述源电极和所述漏电极之间的所述第二金属氧化物半导体层，形成薄膜晶体管的有源层，其中，所述有源层包括所述第一金属氧化物半导体层、位于所述第一金属氧化物半导体层与所述漏电极之间的第二金属氧化物半导体层、位于所述第一金属氧化物半导体层与所述源电极之间的第二金属氧化物半导体层。
  6. 根据权利要求5所述的薄膜晶体管的制作方法，其中，
    所述第二金属氧化物半导体层采用ZnO、ZnON或IZO，所述第一金属氧化物半导体层采用IGZO，所述第一刻蚀液采用H2O2刻蚀液；或
    所述第二金属氧化物半导体层采用ZnO、ZnON、IZO或IGZO，所述第一金属氧化物半导体层采用ITZO、IGZTO或IGZXO，所述第一刻蚀液采用Al刻蚀液；或
    所述源漏金属层包括Cu，所述第二刻蚀液为H2O2刻蚀液；或
    所述源漏金属层包括Mo或Al、AlNd，所述第二刻蚀液为Mo刻蚀药液。
  7. 根据权利要求1所述的薄膜晶体管的制作方法，其中，所述形成金属氧化物半导体图形的步骤之前，所述制作方法还包括：
    提供一衬底基板；
    在所述衬底基板上形成薄膜晶体管的栅电极；
    在形成有所述栅电极的衬底基板上形成栅绝缘层，所述金属氧化物半导体图形形成在所述栅绝缘层上。
  8. 根据权利要求1所述的薄膜晶体管的制作方法，其中，所述形成薄膜晶体管的源电极、漏电极和有源层的步骤之后，所述制作方法还包括：
    形成覆盖所述源电极、所述漏电极和所述有源层的栅绝缘层；
    在所述栅绝缘层上形成薄膜晶体管的栅电极。
  9. 一种薄膜晶体管，采用如权利要求1-8中任一项所述的制作方法制作得到，所述薄膜晶体管的有源层包括第一金属氧化物半导体层、位于所述第一金属氧化物半导体层与漏电极之间的第二金属氧化物半导体层、位于所述第一金属氧化物半导体层与源电极之间的第二金属氧化物半导体层，其中，所述第二金属氧化物半导体层被预设刻蚀液刻蚀的速率大于所述第一金属氧化物半导体层被预设刻蚀液刻蚀的速率。
  10. 一种显示基板，包括如权利要求9所述的薄膜晶体管。
  11. 一种显示装置，包括如权利要求10所述的显示基板。
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CN107946366A (zh) * 2017-11-06 2018-04-20 深圳市华星光电技术有限公司 一种薄膜晶体管、阵列基板及阵列基板的制备方法
CN110120426B (zh) * 2018-02-07 2023-01-10 南京京东方显示技术有限公司 一种薄膜晶体管的制造方法及薄膜晶体管
CN109742150A (zh) * 2018-12-25 2019-05-10 惠科股份有限公司 一种阵列基板及其制造方法和显示面板
KR20210010333A (ko) * 2019-07-19 2021-01-27 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
KR102852909B1 (ko) * 2019-08-07 2025-09-03 삼성디스플레이 주식회사 도전 패턴, 도전 패턴을 포함하는 표시 장치, 및 도전 패턴의 제조 방법
CN116799016B (zh) * 2023-07-28 2024-08-09 惠科股份有限公司 阵列基板及其制作方法和显示面板

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100096634A1 (en) * 2008-10-17 2010-04-22 Samsung Electronics Co., Ltd. Panel structure, display device including same, and methods of manufacturing panel structure and display device
CN103337462A (zh) * 2013-06-13 2013-10-02 北京大学深圳研究生院 一种薄膜晶体管的制备方法
CN205810822U (zh) * 2016-06-15 2016-12-14 中华映管股份有限公司 薄膜晶体管及显示面板
CN106784014A (zh) * 2016-12-23 2017-05-31 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、显示基板、显示装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6872604B2 (en) * 2000-06-05 2005-03-29 Semiconductor Energy Laboratory Co., Ltd. Method of fabricating a light emitting device
JP5361651B2 (ja) * 2008-10-22 2013-12-04 株式会社半導体エネルギー研究所 半導体装置の作製方法
US8492756B2 (en) * 2009-01-23 2013-07-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
JP2012146956A (ja) * 2010-12-20 2012-08-02 Canon Inc チャネルエッチ型薄膜トランジスタとその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100096634A1 (en) * 2008-10-17 2010-04-22 Samsung Electronics Co., Ltd. Panel structure, display device including same, and methods of manufacturing panel structure and display device
CN103337462A (zh) * 2013-06-13 2013-10-02 北京大学深圳研究生院 一种薄膜晶体管的制备方法
CN205810822U (zh) * 2016-06-15 2016-12-14 中华映管股份有限公司 薄膜晶体管及显示面板
CN106784014A (zh) * 2016-12-23 2017-05-31 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、显示基板、显示装置

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