+

WO2013075591A1 - 阵列基板及其制作方法、显示装置 - Google Patents

阵列基板及其制作方法、显示装置 Download PDF

Info

Publication number
WO2013075591A1
WO2013075591A1 PCT/CN2012/084404 CN2012084404W WO2013075591A1 WO 2013075591 A1 WO2013075591 A1 WO 2013075591A1 CN 2012084404 W CN2012084404 W CN 2012084404W WO 2013075591 A1 WO2013075591 A1 WO 2013075591A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrode
strip electrodes
layer
array substrate
adjacent strip
Prior art date
Application number
PCT/CN2012/084404
Other languages
English (en)
French (fr)
Inventor
李润复
Original Assignee
京东方科技集团股份有限公司
合肥京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 合肥京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US13/806,182 priority Critical patent/US9147697B2/en
Publication of WO2013075591A1 publication Critical patent/WO2013075591A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device. Background technique
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • ADSDS Advanced Super Dimension Switch
  • the electric field generated by the edge of the slit electrode in the same plane and the electric field generated between the slit electrode layer and the plate electrode layer form a multi-dimensional electric field, so that all the aligned liquid crystal molecules between the slit electrodes in the liquid crystal cell and directly above the electrode can be generated. Rotation, thereby improving the liquid crystal working efficiency and increasing the light transmission efficiency.
  • Advanced super-dimensional field switching technology can improve the picture quality of TFT-LCD products, with high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, push mura, etc. advantage.
  • the liquid crystal panel of the ADS mode includes a color filter substrate 12 and an array substrate, and the array substrate includes a transparent indium tin oxide (ITO) common electrode (Vcom) formed on the substrate 1 at the lower portion, which can be regarded as a plate electrode. 3', and a strip electrode 8' (which can be regarded as a slit electrode) as a pixel electrode on the upper passivation layer 7 (Passivation) 7.
  • the strip electrode 8' is formed by processes such as exposure, development, etching, and lift-off. When a multi-dimensional electric field is generated between the color filter substrate 12 and the array substrate, light is transmitted through most of the area, so that a wide viewing angle with high brightness can be realized.
  • the transmittance of the ADS mode liquid crystal panel is related to the pitch (Pitch) a of the strip electrodes 8'.
  • the pitch a of the strip electrodes is equal to the sum of the width (CD) b of the strip electrodes and the gap (Spacer) c between the strip electrodes.
  • the pitch a of the strip electrodes is ⁇
  • the width b of the strip electrodes is 4 ⁇ m
  • the gap c between the strip electrodes is 6 ⁇ m
  • the pitch is 8 ⁇ m
  • the width b of the strip electrodes is 2.6 ⁇ m
  • the brightness characteristics are better.
  • the pitch a of the strip electrodes is 6 ⁇ m
  • the width b of the strip electrodes is 2 ⁇ m
  • the gap c is 4 ⁇ m
  • the brightness characteristics of the liquid crystal panel are very good, but the width of the exposure of the existing exposure machine is 3.0-5.0 ⁇ m. Therefore, it is difficult to achieve a width b of the strip electrode of less than 3 ⁇ m in the process.
  • the strip electrode width changes, the liquid crystal panel is liable to cause defects such as spots or waviness (Mura), and the display quality of the liquid crystal panel is lowered.
  • FIG. 3 simulation data showing changes in transmittance with changes in strip electrode width b are shown.
  • the two curves in the figure represent the case where the pitch a of the strip electrodes is 8 ⁇ m and the pitch a of the strip electrodes is ⁇ .
  • the pitch a of the strip electrodes is 8 ⁇ m
  • the transmittance of the former is ⁇ compared to the liquid crystal panel in which the pitch a of the strip electrodes is ⁇ .
  • the change is large, and it is easy to produce spots or ripples (Mura).
  • the brightness of the LCD panel is better. Summary of the invention
  • An embodiment of the present invention provides a method of fabricating an array substrate, comprising: forming a gate electrode and a common electrode on a substrate; forming a gate insulating layer and an active layer on the substrate on which the gate electrode and the common electrode are formed; Forming a source/drain electrode layer including a source electrode and a drain electrode on the substrate of the gate insulating layer and the active layer; forming a passivation layer on the substrate on which the source/drain electrode layer is formed, and on the passivation layer Forming a via hole; forming a pixel electrode on the substrate on which the passivation layer having the via hole is formed, the pixel electrode being connected to the drain electrode in the source/drain electrode layer through the via hole; wherein the process of forming the pixel electrode Including: primary etching process, ashing process and secondary etching process.
  • Another embodiment of the present invention further provides an array substrate, including: a substrate; a gate electrode and a common electrode formed on the substrate; a gate insulating layer formed on the substrate and covering the gate electrode and the common electrode An active layer and a source/drain electrode layer sequentially formed on the gate insulating layer and over the gate electrode, the source/drain electrode layer including a source electrode and a drain electrode; formed on the substrate and covering the a passivation layer of the source layer, the source/drain electrode layer and the gate insulating layer, and a via hole is formed on the passivation layer; Connected Pixels Electrical
  • a further embodiment of the present invention also provides a display device comprising the above array substrate.
  • FIG. 1 is a schematic structural view of a liquid crystal panel of an ADS mode in the prior art
  • FIG. 2 is a graph showing a light transmittance of a liquid crystal panel in an ADS mode as a function of a strip electrode width.
  • FIG. 3 is a graph showing a percentage change in a light transmittance of a liquid crystal panel in an ADS mode as a percentage of a strip electrode width. ;
  • FIG. 4 is a flow chart of a method for fabricating an array substrate according to an embodiment of the present invention.
  • FIG. 5 is a flow chart of step S5 of Figure 4.
  • 6a-6f are structural diagrams corresponding to the respective steps of step S5;
  • FIG. 7 is a partial structural schematic view of an array substrate according to an embodiment of the present invention.
  • One of the technical problems to be solved by the present invention is how to form a strip electrode having a smaller size to improve the transmittance of the display device and to improve the spot or ripple phenomenon.
  • the array substrate of the embodiment of the present invention includes a plurality of gate lines and a plurality of data lines, the gate lines and the data lines crossing each other thereby defining pixel units arranged in a matrix, each of the pixel units including a thin film transistor as a switching element and The pixel electrode and the common electrode that control the arrangement of the liquid crystals.
  • the gate of the thin film transistor of each pixel is electrically connected or integrally formed with the corresponding gate line
  • the source is electrically connected or integrally formed with the corresponding data line
  • the drain is electrically connected or integrally formed with the corresponding pixel electrode.
  • FIG. 4 which is a flowchart of a method for fabricating an array substrate according to an embodiment of the present invention, and as shown in FIG. 7, the method includes the following steps:
  • Step S1 forming a transparent electrode 31, a gate electrode 2, a gate line (not shown), and a common electrode line 32 on the substrate 1; wherein the gate electrode 2, the gate line, and the common electrode line 32 may be formed by a metal film through a patterning process Forming, the transparent electrode 31 and the common electrode line 32 are electrically connected to each other to constitute a common electrode 3, that is, a plate electrode;
  • the metal film in this step may comprise Mo, Cu, Al or an aluminum-nickel alloy and a combination thereof;
  • the substrate 1 may be a glass substrate, a resin substrate or the like;
  • Step S2 continuously depositing a gate insulating layer 4 and an amorphous silicon film on the substrate 1 of the step 1, forming an active layer 5 on the gate insulating layer 4 by a patterning process;
  • the material of the gate insulating layer 4 may be selected from silicon nitride or silicon oxide, etc.
  • the amorphous silicon film used to form the active layer 5 includes, for example, a lower n+a-Si amorphous silicon film 52, a-Si amorphous. a silicon film 51 and an upper n + a-Si amorphous silicon film 52;
  • Step S3 depositing a metal thin film on the substrate on which the step S2 is completed, and forming a source/drain electrode layer 6 including the source electrode 61 and the drain electrode 62 by a patterning process.
  • a gap between the source electrode 61 and the drain electrode 6 exposes a portion of the upper n+a-Si amorphous silicon film 52.
  • the exposed portion of the upper n+a-Si amorphous silicon film 52 is completely etched away, and a portion of the exposed a-Si amorphous silicon film 51 is etched away to form a TFT channel;
  • Step S4 depositing a passivation layer 7 on the substrate on which step S3 is completed, and forming a via hole H on the passivation layer 7;
  • Step S5 forming a pixel electrode 8 on the substrate on which the step S4 is completed, and the pixel electrode 8 is connected to the drain electrode 62 in the source/drain electrode layer 6 through the via hole H; wherein the pixel electrode 8 includes, for example, a plurality of overlapping electrodes 31
  • the strip electrode 81 for example, has a slit between two adjacent strip electrodes 81.
  • the strip electrodes 81 may be zigzag, linear, or the like.
  • the process of forming the pixel electrode 8 includes at least: a primary etching process, an ashing process, and a secondary etching process.
  • the patterning process involved in the above steps includes at least a series of processes such as coating, mask exposure, development, etching, and peeling.
  • the step S5 includes, for example:
  • Step S51 sequentially depositing a transparent conductive film 9 and a photoresist (Photoresist, PR) 10 on the passivation layer 7; as shown in FIG. 6a; wherein the transparent conductive film 9 may be an indium tin oxide (ITO) conductive film or an indium An oxide (IZO) conductive film or the like is described in the present embodiment by taking the ITO conductive film 9 as an example.
  • ITO indium tin oxide
  • IZO indium An oxide
  • Step S52 exposing and developing the photoresist 10 by using the mask 11 to form a photoresist pattern 10'; as shown in FIG. 6b;
  • Step S53 performing a first etching on the ITO conductive film 9 to form an ITO conductive pattern 9, as shown in FIG. 6c;
  • Step S54 performing ashing treatment on the photoresist pattern 10 to form a photoresist pattern 10"; as shown in FIG. 6d;
  • Step S55 performing a second etching on the ITO conductive pattern 9 with the photoresist pattern 10" as an etch mask to form an ITO conductive pattern 9"; as shown in FIG. 6e;
  • Step S56 the photoresist pattern 10" is subjected to a lift-off process to obtain an ITO conductive pattern 9" as a strip electrode 81, as shown in Fig. 6f.
  • FIG. 5 shows only an exemplary formation process of one strip electrode 81, those skilled in the art may understand that all or part of the strip electrodes 81 included in the pixel electrode 8 in the embodiment of the present application may be formed by the above process. .
  • the interval between the adjacent two strip electrodes 81 can be 4.5-6 ⁇ m, preferably 4.5 ⁇ m; the strip electrode 81
  • the width can be 1.5-2 ⁇ m, preferably 1.5 ⁇ m; the gap between two adjacent strip electrodes 81 can reach 3-4 ⁇ m, preferably 3 ⁇ m; in one embodiment of the invention, the pixel
  • the strip electrodes 81 included in the electrode 8 have a pitch of 4.5-6 ⁇ m, preferably 4.5 ⁇ m; each strip electrode 8 has a width of 1.5-2 ⁇ m, preferably 1.5 ⁇ m; each two adjacent strips
  • the gap between the electrodes 81 can reach 3-4 ⁇ m, preferably 3 ⁇ m; it has been experimentally proved that the brightness characteristics of the liquid crystal panel according to the embodiment of the present application can be improved by 20%-30% compared with the prior art. It also increases the light transmittance and improves the phenomenon of spots or ripples.
  • an embodiment of the present invention further provides an array substrate including a substrate 1 , a gate electrode 2 formed on the substrate 1 , a gate line (not shown), and a common electrode 32 formed on the substrate 1 .
  • a gate insulating layer 4 covering the gate electrode 2, the gate line and the common electrode; sequentially formed on the gate
  • An active layer 5 on the insulating layer 4 and above the gate electrode 2 and a source/drain electrode layer 6 including a source electrode 61 and a drain electrode 62 are formed on the passivation layer 7 on the substrate 1, and a passivation layer 7 is formed thereon.
  • the via hole H is formed in which the common electrode includes the transparent electrode 31 and the common electrode line 32; wherein, the pixel electrode 8 includes, for example, a plurality of strip electrodes 81 overlapping the transparent electrode 31, for example, between two adjacent strip electrodes 81 There is a slit.
  • the strip electrode 81 is, for example, a zigzag shape, a linear shape, or the like.
  • the pitch of the adjacent two strip electrodes 81 is 4.5-6 ⁇ m, preferably 4.5 ⁇ m; the strip electrode 81 can have a width of 1.5-2 ⁇ m, preferably 1.5 ⁇ m; two adjacent strip electrodes 81
  • the gap between the gaps can be 3-4 ⁇ m, preferably 3 ⁇ m; in one embodiment of the invention, the pitch of all the strip electrodes 81 included in the pixel electrode 8 is 4.5-6 ⁇ m, preferably 4.5 ⁇ m
  • Each strip electrode 8 has a width of 1.5-2 ⁇ m, preferably 1.5 ⁇ m; a gap between each two adjacent strip electrodes 81 can reach 3-4 ⁇ , preferably, 3 ⁇ ;
  • An embodiment of the present invention also provides a display device comprising the array substrate of any of the above embodiments.
  • the display device of the embodiment of the present invention may be a liquid crystal display device including a counter substrate, for example, for a liquid crystal television, a mobile phone, a liquid crystal display, GPS, or the like.
  • the array substrate and the opposite substrate are opposed to each other to form a liquid crystal cell, and the liquid crystal cell is filled with a liquid crystal material.
  • the opposite substrate is, for example, a color filter substrate.
  • the pixel electrode of each pixel unit of the array substrate is used to apply an electric field to control the degree of rotation of the liquid crystal material to perform a display operation.
  • the liquid crystal display device further includes a backlight that provides backlighting for the array substrate.
  • the display device of the embodiment of the present invention may also be other types of display devices not including a color filter substrate, such as an electronic paper display device.
  • Each of the embodiments of the present invention is applicable to an ADS type liquid crystal display device and an In-Plane Switching (IPS) type liquid crystal display device.
  • IPS In-Plane Switching
  • the pattern of the strip electrodes is made smaller by adding an ashing process and a second etching process after the initial etching process, thereby improving the display.
  • the brightness and transmittance of the device improve defects such as spots and ripples, and improve the display quality of the liquid crystal panel.
  • a gate insulating layer and an active layer on the substrate on which the gate electrode and the common electrode are formed Forming a gate insulating layer and an active layer on the substrate on which the gate electrode and the common electrode are formed; forming a source/drain electrode layer including a source electrode and a drain electrode on the substrate on which the gate insulating layer and the active layer are formed;
  • a pixel electrode on the substrate on which the passivation layer having via holes is formed the pixel electrode being connected to the drain electrode in the source/drain electrode layer through the via hole; wherein the process of forming the pixel electrode includes: initial engraving Etching process, ashing process and secondary etching process.
  • the first transparent conductive film is first etched to form a first transparent conductive pattern by using the first photoresist pattern as an etch mask;
  • the first transparent conductive pattern is etched a second time by using the second photoresist pattern as an etch mask to form a second transparent conductive pattern;
  • the second photoresist pattern is subjected to a lift-off process.
  • the array substrate produced by the method of (1) comprising: a substrate; formed on the substrate a gate electrode and a common electrode; a gate insulating layer formed on the substrate and covering the gate electrode and the common electrode; an active layer and a source drain sequentially formed on the gate insulating layer and over the gate electrode a drain layer, the source/drain electrode layer includes a source electrode and a drain electrode; a passivation layer formed on the substrate and covering the active layer, the source/drain electrode layer, and the gate insulating layer, the passivation layer being formed Have vias; and
  • the pixel electrode includes at least two adjacent strip electrodes, and a pitch of the at least two adjacent strip electrodes is 4.5-6 ⁇ m, and the at least At least one of the two adjacent strip electrodes has a width of 1.5-2 ⁇ m.
  • a display device comprising the array substrate according to (7).

Landscapes

  • Liquid Crystal (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

本发明的实施例公开了阵列基板及其制作方法、显示装置。该阵列基板的制作方法包括：在基板上形成栅电极和公共电极；在形成有所述栅电极和公共电极的基板上形成栅绝缘层和有源层；在形成有所述栅绝缘层和有源层的基板上形成包括源电极和漏电极的源漏电极层；在形成有所述源漏电极层的基板上形成钝化层，并在所述钝化层上形成过孔；在形成有所述具有过孔的钝化层的基板上形成像素电极，所述像素电极通过过孔与源漏电极层中的漏电极连接。所述形成像素电极的过程包括：初次刻蚀工艺、灰化工艺和二次刻蚀工艺。

Description

阵列基板及其制作方法、 显示装置 技术领域
本发明的实施例涉及阵列基板及其制作方法、 显示装置。 背景技术
薄膜晶体管液晶显示 ( Thin Film Transistor Liquid Crystal Display , TFT-LCD )技术在近些年来发展迅速。 然而， 液晶显示器在正面观看画面显 示效果很好， 而从侧面观看就会出现变色。 广视角 （ Wide Viewing Angle ) 技术由于降低了侧面看屏幕产生的变色程度， 而成为新的发展趋势。 高级超 维场转换技术（ Advanced Super Dimension Switch, ADSDS ) , 简称 ADS, 是液晶界为解决大尺寸、 高清晰度桌面显示器和液晶电视应用而开发的广视 角技术。 其通过同一平面内狭缝电极边缘所产生的电场以及狭缝电极层与板 状电极层间产生的电场形成多维电场， 使液晶盒内狭缝电极间、 电极正上方 所有取向液晶分子都能够产生旋转， 从而提高了液晶工作效率并增大了透光 效率。 高级超维场开关技术可以提高 TFT-LCD产品的画面品质， 具有高分 辨率、 高透过率、 低功耗、 宽视角、 高开口率、低色差、 无挤压水波紋（push Mura )等优点。
如图 1所示， ADS模式的液晶面板包括彩膜基板 12和阵列基板， 阵列 基板包括位于下部的形成于基板 1上的透明氧化铟锡（ ITO )公共电极（ Vcom, 可视为板状电极） 3' , 和位于上部的钝化层（Passivation ) 7上的作为像素电 极的条状电极 8' (可视为狭缝状电极） 。 其中条状电极 8'通过曝光、 显影、 刻蚀和剥离等工艺而形成。彩膜基板 12和阵列基板之间发生多维电场后在大 部分区域上使光透过， 从而可以实现高亮度的广视角。 ADS模式液晶面板的 透过率与条状电极 8'的间距（Pitch ) a相关。
在 ADS模式的液晶面板中，条状电极的间距 a等于条状电极的宽度（ CD ) b与条状电极之间的间隙（Spacer ) c之和。 当条状电极的间距 a为 ΙΟμπι时， 条状电极的宽度 b为 4μπι, 条状电极之间的间隙 c为 6μπι; 当间距为 8μπι, 条状电极的宽度 b为 2.6μπι, 条状电极之间的间隙 c为 5.4μπι时， 液晶面板 的亮度特性较好。 当条状电极的间距 a为 6μπι, 条状电极的宽度 b为 2μπι, 间隙 c为 4μπι时， 液晶面板的亮度特性非常好， 但由于现有的曝光机能够曝 光的宽度在 3.0-5.0μπι之间， 因此工艺上要实现条状电极的宽度 b小于 3μπι 较难， 随着条状电极宽度的变化液晶面板容易产生斑或波紋（ Mura )等不良， 降低液晶面板的显示品质。
如图 2所示，示出了液晶面板的透过率与条状电极的宽度 b之间的关系， 随着间距 = +0逐渐变小， 液晶面板的亮度（即透过率）会增加； 虽然亮度 在增加， 但维持亮度均一性的工艺范围在逐渐减 d、。
再如图 3所示，示出了透过率的变化随条状电极宽度 b的变化仿真数据。 图中两条曲线分别代表条状电极的间距 a为 8μπι和条状电极的间距 a为 ΙΟμπι 时的情形。 从图中可以看出， 当宽度 b的增加百分比相同的情况下， 条状电 极的间距 a为 8μπι与条状电极的间距 a为 ΙΟμπι的液晶面板相比， 前者透过 率随间距变化量的变化较大， 容易产生斑或波紋（Mura )等现象。
结合图 2和图 3中两个曲线图可知， 条状电极的间距 a越小， 液晶面板 的亮度越好； 在同样的条状电极的间距 a的情况下，条状电极的宽度 b越小， 液晶面板的亮度越好。 发明内容
本发明的一个实施例提供阵列基板的制作方法， 包括： 在基板上形成栅 电极和公共电极； 在形成有所述栅电极和公共电极的基板上形成栅绝缘层和 有源层； 在形成有所述栅绝缘层和有源层的基板上形成包括源电极和漏电极 的源漏电极层； 在形成有所述源漏电极层的基板上形成钝化层， 并在所述钝 化层上形成过孔； 在形成有所述具有过孔的钝化层的基板上形成像素电极， 所述像素电极通过过孔与源漏电极层中的漏电极连接； 其中， 所述形成像素 电极的过程包括： 初次刻蚀工艺、 灰化工艺和二次刻蚀工艺。
本发明的另一实施例还提供一种阵列基板， 包括： 基板； 形成于所述基 板上的栅电极和公共电极； 形成于所述基板上并覆盖所述栅电极和公共电极 的栅绝缘层； 依次形成在所述栅绝缘层上并位于栅电极之上的有源层和源漏 电极层， 所述源漏电极层包括源电极和漏电极； 形成在所述基板上并覆盖所 述有源层、 源漏电极层和栅绝缘层的钝化层， 所述钝化层上形成有过孔； 以 连接的像素电 本发明的又一实施例还提供了一种显示装置， 包括上述阵列基板。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例或现有技 术描述中所需要使用的附图作简单地介绍， 显而易见地， 下面描述中的附图 仅仅涉及本发明的一些实施例， 并非对本发明的限制。
图 1是现有技术中 ADS模式的液晶面板的结构示意图；
图 2是 ADS模式的液晶面板的光透过率随条状电极的宽度变化的曲线 图 3是 ADS模式的液晶面板的光透过率的降低百分比随条状电极宽度 增加的百分比变化的曲线图；
图 4是本发明实施例的阵列基板的制作方法流程图；
图 5是图 4中步骤 S5的流程图；
图 6a-图 6f是步骤 S5的各个步骤对应的结构图；
图 7是本发明实施例的阵列基板的局部结构示意图； 具体实施方式
下面将结合附图，对本发明实施例中的技术方案进行清楚、完整地描述， 显然， 所描述的实施例仅仅是本发明一部分实施例， 而不是全部的实施例。 基于本发明中的实施例， 本领域普通技术人员在没有做出创造性劳动前提下 所获得的所有其他实施例， 都属于本发明保护的范围。
本发明要解决的技术问题之一是如何形成尺寸更小的条状电极， 以提高 显示装置的透过率， 改善斑或波紋现象。
本发明实施例的阵列基板包括多条栅线和多条数据线， 这些栅线和数据 线彼此交叉由此限定了排列为矩阵的像素单元， 每个像素单元包括作为开关 元件的薄膜晶体管和用于控制液晶的排列的像素电极和公共电极。 例如， 每 个像素的薄膜晶体管的栅极与相应的栅线电连接或一体形成， 源极与相应的 数据线电连接或一体形成， 漏极与相应的像素电极电连接或一体形成。 下面 的描述主要针对单个或多个像素单元进行， 但是其他像素单元可以相同地形 成。
第一实施例
如图 4所示， 为本发明实施例的阵列基板的制作方法流程图， 并结合图 7所示， 本方法包括以下步骤：
步骤 Sl、 在基板 1上形成透明电极 31、 栅电极 2、 栅线（未示出）和公 共电极线 32; 其中栅电极 2、栅线和公共电极线 32可以由一金属薄膜通过构 图工艺而形成， 透明电极 31和公共电极线 32彼此电性连接以构成公共电极 3 , 即， 板状电极；
本步骤中的金属薄膜可以包含 Mo, Cu, A1或铝镍合金及其组合物； 基 板 1可以为玻璃基板、 树脂基板等等；
步骤 S2、 在完成步骤 1的基板 1上连续沉积栅绝缘层 4和非晶硅薄膜， 通过构图工艺在栅绝缘层 4上形成有源层 5;
本步骤中栅绝缘层 4的材料可选用氮化硅或氧化硅等， 用于形成有源层 5的非晶硅薄膜例如包括下 n+a-Si非晶硅薄膜 52、 a-Si非晶硅薄膜 51和上 n+a-Si非晶硅薄膜 52;
步骤 S3、 在完成步骤 S2的基板上沉积金属薄膜， 通过构图工艺形成包 括源电极 61和漏电极 62的源漏电极层 6。源电极 61和漏电极 6之间的间隙 暴露部分的上 n+a-Si非晶硅薄膜 52。 接着将上 n+a-Si非晶硅薄膜 52的暴露 部分完全刻蚀掉， 并将由此暴露的 a-Si非晶硅薄膜 51刻蚀掉一部分， 从而 形成 TFT沟道；
步骤 S4、 在完成步骤 S3的基板上沉积钝化层 7, 并在钝化层 7上形成 过孔 H;
步骤 S5、 在完成步骤 S4的基板上形成像素电极 8, 像素电极 8通过过 孔 H与源漏电极层 6中的漏电极 62连接； 其中， 像素电极 8例如包括与透 明电极 31重叠的多个条状电极 81 , 两个相邻的条状电极 81之间例如存在狭 缝。条状电极 81可以为之字形、直线形等。 所述形成像素电极 8的过程至少 包括： 初次刻蚀工艺、 灰化工艺和二次刻蚀工艺。
上述步骤中所涉及的构图工艺至少包括： 涂覆、掩模曝光、 显影、 刻蚀、 剥离等一系列过程。 如图 5所示， 该步骤 S5例如包括：
步骤 S51、 在钝化层 7上依次沉积透明导电膜 9和光刻胶（ Photoresist, PR ) 10; 如图 6a所示； 其中透明导电膜 9可以是氧化铟锡（ ITO )导电膜或 铟辞氧化物（IZO )导电膜等， 本实施例以 ITO导电膜 9为例进行说明。
步骤 S52、 釆用掩模板 11对光刻胶 10进行曝光和显影以形成光刻胶图 案 10'; 如图 6b所示;
步骤 S53、 对 ITO导电膜 9进行第一次刻蚀以形成 ITO导电图案 9，； 如 图 6c所示;
步骤 S54、对光刻胶图案 10，进行灰化处理以形成光刻胶图案 10"; 如图 6d所示；
步骤 S55、 以光刻胶图案 10"作为刻蚀掩模对 ITO导电图案 9，进行第二 次刻蚀以形成 ITO导电图案 9"; 如图 6e所示；
步骤 S56、对光刻胶图案 10"进行剥离处理， 得到 ITO导电图案 9"作为 一个条状电极 81 , 如图 6f所示。
尽管图 5仅示出了一个条状电极 81的示例性形成工艺，但是本领域技术 人员可以理解， 本申请实施例中的像素电极 8所包括的全部或部分条状电极 81均可由上述工艺形成。
在第一次刻蚀工艺之后追加灰化工艺和二次刻蚀工艺， 最后形成的相邻 两个条状电极 81的间距能够达到 4.5-6μηι, 优选地， 为 4.5μπι; 条状电极 81 的宽度能够达到 1.5-2μπι, 优选地， 为 1.5μπι; 两个相邻的条状电极 81之间 的间隙能够达到 3-4 μπι, 优选地， 为 3μηι; 在本发明的一个实施例中， 像素 电极 8所包括的全部条状电极 81的间距为 4.5-6μπι, 优选地， 为 4.5μπι; 每 个条状电极 8的宽度为 1.5-2μπι, 优选地， 为 1.5μπι; 每两个相邻条状电极 81之间的间隙能够达到 3-4 μπι, 优选地， 为 3μπι; 经试验证明， 与现有技术 相比， 根据本申请实施例的液晶面板的亮度特性能够改善 20%-30%, 并且提 高了光透过率， 改善了斑或波紋等现象。
第二实施例
如图 7所示， 本发明实施例还提供了一种阵列基板， 包括基板 1 , 形成 于基板 1上的栅电极 2、 栅线（未示出）和公共电极 32, 形成在基板 1上的 栅绝缘层 4,栅绝缘层 4覆盖在栅电极 2、栅线和公共电极上； 依次形成在栅 绝缘层 4上并位于栅电极 2之上的有源层 5和包括源电极 61和漏电极 62的 源漏电极层 6, 形成在基板 1上的钝化层 7 ,钝化层 7上形成有过孔 H, 形成 其中公共电极包括透明电极 31和公共电极线 32; 其中， 像素电极 8例如包 括与透明电极 31重叠的多个条状电极 81 , 两个相邻的条状电极 81之间例如 存在狭缝。 条状电极 81例如为之字形、 直线形等。
相邻两个条状电极 81的间距为 4.5-6μπι, 优选地， 为 4.5μπι; 条状电极 81的宽度能够达到 1.5-2μπι, 优选地， 为 1.5μπι; 两个相邻的条状电极 81之 间的间隙能够达到 3-4 μπι, 优选地， 为 3μπι; 在本发明的一个实施例中， 像 素电极 8所包括的全部条状电极 81的间距为 4.5-6μπι, 优选地， 为 4.5μπι; 每个条状电极 8的宽度为 1.5-2μπι, 优选地， 为 1.5μπι; 每两个相邻条状电极 81之间的间隙能够达到 3-4 μπι, 优选地， 为 3μπι;
第三实施例
本发明的实施例还提供了一种显示装置， 其包括上述任一实施例的阵列 基板。 本发明的实施例的显示装置可以为包括对置基板的液晶显示装置， 例 如， 用于液晶电视、 手机、 液晶显示器、 GPS等。 其中， 阵列基板与对置基 板彼此对置以形成液晶盒， 在液晶盒中填充有液晶材料。 该对置基板例如为 彩膜基板。 阵列基板的每个像素单元的像素电极用于施加电场对液晶材料的 旋转的程度进行控制从而进行显示操作。 在一些示例例中， 该液晶显示装置 还包括为阵列基板提供背光的背光源。
本发明的实施例的显示装置也可以是不包括彩膜基板的其他类型的显示 装置， 例如电子纸显示装置。
本发明的各个实施例均适用于 ADS 型液晶显示装置以及平面转换 ( In-Plane Switching, IPS )型液晶显示装置。
由以上实施例可以看出， 本发明实施例在形成条状电极时， 通过在初次 刻蚀工艺之后追加灰化工艺和二次刻蚀工艺， 使得条状电极的图案更微小， 从而提高了显示装置的亮度和透过率， 改善了斑和波紋等不良， 提高了液晶 面板的显示品质。 ( 1 ) 阵列基板的制作方法， 包括： 在基板上形成栅电极和公共电极；
在形成有所述栅电极和公共电极的基板上形成栅绝缘层和有源层； 在形成有所述栅绝缘层和有源层的基板上形成包括源电极和漏电极的源 漏电极层；
在形成有所述源漏电极层的基板上形成钝化层， 并在所述钝化层上形成 过孔；
在形成有所述具有过孔的钝化层的基板上形成像素电极， 所述像素电极 通过过孔与源漏电极层中的漏电极连接； 其中， 所述形成像素电极的过程包 括： 初次刻蚀工艺、 灰化工艺和二次刻蚀工艺。
( 2 )根据 ( 1 ) 的阵列基板的制作方法， 其中， 所述形成像素电极的步 骤包括：
在所述钝化层上依次沉积透明导电膜和光刻胶；
对所述光刻胶进行曝光和显影以形成第一光刻胶图案；
以第一光刻胶图案作为刻蚀掩模对其下方的所述透明导电膜进行第一次 刻蚀以形成第一透明导电图案；
对第一光刻胶图案进行灰化处理以形成第二光刻胶图案；
以第二光刻胶图案作为刻蚀掩模对所述第一透明导电图案进行第二次刻 蚀以形成第二透明导电图案；
对所述第二光刻胶图案进行剥离处理。
( 3 )根据（ 1 )或（ 2 )的阵列基板的制作方法， 其中， 所述像素电极形 成为包括至少两个相邻的条状电极， 所述至少两个相邻的条状电极的间距为 4.5-6μπι, 且所述至少两个相邻的条状电极的至少一个的宽度为 1.5-2μπι。
( 4 )根据 ( 3 ) 的阵列基板的制作方法， 其中， 所述至少两个相邻的条 状电极的间距为 4.5μπι, 且所述至少两个相邻的条状电极中的至少一个的宽 度为 1.5μπι。
( 5 )根据（ 1 ) 的阵列基板的制作方法 , 其中， 所述像素电极形成为与 所述公共电极至少部分重叠。
( 6 )根据（ 1 ) 的阵列基板的制作方法 , 其中， 所述公共电极形成为板 状。
( 7 )根据（ 1 ) 的方法制作的阵列基板 , 包括： 基板； 形成于所述基板 上的栅电极和公共电极； 形成于所述基板上并覆盖所述栅电极和公共电极的 栅绝缘层； 依次形成在所述栅绝缘层上并位于栅电极之上的有源层和源漏电 极层， 所述源漏电极层包括源电极和漏电极； 形成在所述基板上并覆盖所述 有源层、 源漏电极层和栅绝缘层的钝化层， 所述钝化层上形成有过孔； 以及
(8)根据 (7) 的阵列基板， 其中， 所述像素电极包括至少两个相邻的 条状电极， 所述至少两个相邻的条状电极的间距为 4.5-6μπι, 且所述至少两 个相邻的条状电极的至少一个的宽度为 1.5-2μπι。
(9)根据 (7) 的阵列基板， 其中， 所述至少两个相邻的条状电极的间 距为 4.5μπι, 且所述至少两个相邻的条状电极的至少一个的宽度为 1.5μπι。
(10)显示装置， 包括根据（7) 的阵列基板。
虽然上文中已经用一般性说明、 具体实施方式及实验， 对本发明作了详 尽的描述， 但在本发明基础上， 可以对之作一些修改或改进， 这对本领域技 术人员而言是显而易见的。 因此， 在不偏离本发明精神的基础上所做的这些 修改或改进， 均属于本发明要求保护的范围。

Claims

1、 阵列基板的制作方法， 包括：
在基板上形成栅电极和公共电极；
在形成有所述栅电极和公共电极的基板上形成栅绝缘层和有源层； 在形成有所述栅绝缘层和有源层的基板上形成包括源电极和漏电极的源 漏电极层；
在形成有所述源漏电极层的基板上形成钝化层， 并在所述钝化层上形成 过孔；
在形成有所述具有过孔的钝化层的基板上形成像素电极， 所述像素电极 通过过孔与源漏电极层中的漏电极连接； 其中， 所述形成像素电极的过程包 括： 初次刻蚀工艺、 灰化工艺和二次刻蚀工艺。
2、如权利要求 1所述的阵列基板的制作方法， 其中， 所述形成像素电极 的步骤包括：
在所述钝化层上依次沉积透明导电膜和光刻胶；
对所述光刻胶进行曝光和显影以形成第一光刻胶图案；
以第一光刻胶图案作为刻蚀掩模对其下方的所述透明导电膜进行第一次 刻蚀以形成第一透明导电图案；
对第一光刻胶图案进行灰化处理以形成第二光刻胶图案；
以第二光刻胶图案作为刻蚀掩模对所述第一透明导电图案进行第二次刻 蚀以形成第二透明导电图案；
对所述第二光刻胶图案进行剥离处理。
3、如权利要求 1所述的阵列基板的制作方法， 其中， 所述像素电极形成 为包括至少两个相邻的条状电极， 所述至少两个相邻的条状电极的间距为 4.5-6μπι, 且所述至少两个相邻的条状电极的至少一个的宽度为 1.5-2μπι。
4、如权利要求 2所述的阵列基板的制作方法， 其中， 所述像素电极形成 为包括至少两个相邻的条状电极， 所述至少两个相邻的条状电极的间距为 4.5-6μπι, 且所述至少两个相邻的条状电极中的至少一个的宽度为 1.5-2μπι。
5、如权利要求 3所述的阵列基板的制作方法， 其中， 所述至少两个相邻 的条状电极的间距为 4.5μπι, 且所述至少两个相邻的条状电极中的至少一个 的宽度为 1.5μπι。
6、如权利要求 4所述的阵列基板的制作方法， 其中， 所述至少两个相邻 的条状电极的间距为 4.5μπι, 且所述至少两个相邻的条状电极中的至少一个 的宽度为 1.5μπι。
7、如权利要求 1所述的阵列基板的制作方法， 其中， 所述像素电极形成 为与所述公共电极至少部分重叠。
8、如权利要求 1所述的阵列基板的制作方法， 其中， 所述公共电极形成 为板状。
9、 如权利要求 1所述的方法制作的阵列基板， 包括： 基板； 形成于所述 基板上的栅电极和公共电极； 形成于所述基板上并覆盖所述栅电极和公共电 极的栅绝缘层； 依次形成在所述栅绝缘层上并位于栅电极之上的有源层和源 漏电极层， 所述源漏电极层包括源电极和漏电极； 形成在所述基板上并覆盖 所述有源层、 源漏电极层和栅绝缘层的钝化层， 所述钝化层上形成有过孔； 极。
10、 如权利要求 9所述的阵列基板， 其中， 所述像素电极包括至少两个 相邻的条状电极， 所述至少两个相邻的条状电极的间距为 4.5-6μπι, 且所述 至少两个相邻的条状电极的至少一个的宽度为 1.5-2μπι。
11、如权利要求 10所述的阵列基板， 其中， 所述至少两个相邻的条状电 极的间距为 4.5μπι, 且所述至少两个相邻的条状电极的至少一个的宽度为
1.5μπι。
12、 显示装置， 包括权利要求 9所述的阵列基板。
PCT/CN2012/084404 2011-11-24 2012-11-09 阵列基板及其制作方法、显示装置 WO2013075591A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/806,182 US9147697B2 (en) 2011-11-24 2012-11-09 Manufacturing method of array substrate, array substrate, and display apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN2011103794663A CN102629587A (zh) 2011-11-24 2011-11-24 阵列基板及其制作方法、显示装置
CN201110379466.3 2011-11-24

Publications (1)

Publication Number Publication Date
WO2013075591A1 true WO2013075591A1 (zh) 2013-05-30

Family

ID=46587815

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2012/084404 WO2013075591A1 (zh) 2011-11-24 2012-11-09 阵列基板及其制作方法、显示装置

Country Status (3)

Country Link
US (1) US9147697B2 (zh)
CN (1) CN102629587A (zh)
WO (1) WO2013075591A1 (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102629587A (zh) * 2011-11-24 2012-08-08 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
CN103018978B (zh) * 2012-12-14 2016-08-17 京东方科技集团股份有限公司 一种液晶面板及显示装置
CN104419930B (zh) * 2013-08-27 2018-03-27 东友精细化工有限公司 蚀刻液组合物及液晶显示装置用阵列基板的制造方法
CN103488008B (zh) * 2013-10-09 2017-02-01 京东方科技集团股份有限公司 阵列基板及其驱动方法、显示装置
CN103972075A (zh) * 2014-05-05 2014-08-06 京东方科技集团股份有限公司 一种刻蚀方法和阵列基板

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070001961A1 (en) * 2005-06-30 2007-01-04 Lg.Philips Lcd Co., Ltd. Method of forming fine pattern, liquid crystal display device having a fine pattern and fabricating method thereof
CN101276106A (zh) * 2007-03-28 2008-10-01 Lg.菲利浦Lcd株式会社 共平面开关模式液晶显示面板及其制造方法
CN101290937A (zh) * 2007-04-19 2008-10-22 乐金显示有限公司 显示器件及其制造方法
CN101656230A (zh) * 2008-08-21 2010-02-24 乐金显示有限公司 制造薄膜晶体管阵列基板的方法
CN102087450A (zh) * 2009-12-07 2011-06-08 乐金显示有限公司 制造液晶显示装置的方法
CN102629587A (zh) * 2011-11-24 2012-08-08 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100857719B1 (ko) * 2001-03-26 2008-09-08 엘지디스플레이 주식회사 액정표시장치 및 그 제조방법
TW588171B (en) * 2001-10-12 2004-05-21 Fujitsu Display Tech Liquid crystal display device
KR20060133670A (ko) * 2005-06-21 2006-12-27 삼성전자주식회사 발광 소자 및 이의 제조 방법과, 이를 구비한 표시 기판
KR101281756B1 (ko) * 2006-10-18 2013-07-04 삼성디스플레이 주식회사 액정 표시 장치의 제조 방법 및 이 방법으로 제조된 액정표시 장치
KR101278477B1 (ko) * 2006-11-07 2013-06-24 삼성디스플레이 주식회사 박막 트랜지스터 기판의 제조 방법
US8125603B2 (en) * 2007-05-17 2012-02-28 Lg Display Co., Ltd. In-plane switching mode liquid crystal display device and method for fabricating the same
KR101159399B1 (ko) * 2009-02-18 2012-06-28 엘지디스플레이 주식회사 박막트랜지스터 어레이기판 및 그의 제조방법
KR20130017034A (ko) * 2011-08-09 2013-02-19 엘지디스플레이 주식회사 박막트랜지스터 어레이 기판 및 그 제조방법

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070001961A1 (en) * 2005-06-30 2007-01-04 Lg.Philips Lcd Co., Ltd. Method of forming fine pattern, liquid crystal display device having a fine pattern and fabricating method thereof
CN101276106A (zh) * 2007-03-28 2008-10-01 Lg.菲利浦Lcd株式会社 共平面开关模式液晶显示面板及其制造方法
CN101290937A (zh) * 2007-04-19 2008-10-22 乐金显示有限公司 显示器件及其制造方法
CN101656230A (zh) * 2008-08-21 2010-02-24 乐金显示有限公司 制造薄膜晶体管阵列基板的方法
CN102087450A (zh) * 2009-12-07 2011-06-08 乐金显示有限公司 制造液晶显示装置的方法
CN102629587A (zh) * 2011-11-24 2012-08-08 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置

Also Published As

Publication number Publication date
US20140054626A1 (en) 2014-02-27
CN102629587A (zh) 2012-08-08
US9147697B2 (en) 2015-09-29

Similar Documents

Publication Publication Date Title
US8692258B2 (en) Array substrate of TFT-LCD including a black matrix and method for manufacturing the same
KR101905757B1 (ko) 에프에프에스 방식 액정표시장치용 어레이기판 및 그 제조방법
US9530807B2 (en) Thin film transistor array substrate, manufacturing method thereof, and display device
US20110050672A1 (en) Tft-lcd array substrate and manufacturing method thereof
JP6572388B2 (ja) Ｉｐｓ型ｔｆｔ−ｌｃｄアレイ基板の製造方法及びｉｐｓ型ｔｆｔ−ｌｃｄアレイ基板
WO2017166341A1 (zh) Tft基板的制作方法及制得的tft基板
US9461078B1 (en) Array substrate, manufacturing method for the same, display device and electronic product
JP6043815B2 (ja) 薄膜トランジスタのアレイ基板及びその製造方法、並びに電子デバイス
US7599032B2 (en) Liquid crystal display device having common electrodes with reduced resistance
WO2013155830A1 (zh) 阵列基板的制造方法、阵列基板及显示装置
CN103309105B (zh) 阵列基板及其制备方法、显示装置
CN105137665A (zh) 显示基板及其制备方法、显示装置
WO2017054394A1 (zh) 阵列基板及其制作方法、显示装置
CN103413812A (zh) 阵列基板及其制备方法、显示装置
US20180046046A1 (en) Array substrate, method for manufacturing the same, and display device
WO2015003464A1 (zh) 阵列基板及其制作方法、显示装置
CN104932159A (zh) 显示基板及其制造方法、驱动方法和显示装置
WO2013075591A1 (zh) 阵列基板及其制作方法、显示装置
US9019462B2 (en) Array substrate and method for manufacturing the same, and display device
WO2019100494A1 (zh) Ips型薄膜晶体管阵列基板及其制作方法
CN105470266A (zh) Ffs型阵列基板及其制作方法
CN104020621B (zh) 一种阵列基板及其制备方法、显示装置
WO2017049865A1 (zh) 阵列基板、显示装置及其制作方法
KR20070000582A (ko) 프린지 필드 스위칭 모드 액정표시장치 및 그 제조방법
KR101146444B1 (ko) 프린지 필드 스위칭 모드 액정표시장치 제조방법

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 13806182

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12851174

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC - FORM 1205A (21.11.2014)

122 Ep: pct application non-entry in european phase

Ref document number: 12851174

Country of ref document: EP

Kind code of ref document: A1

点击 这是indexloc提供的php浏览器服务，不要输入任何密码和下载