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WO1990006595A1 - Transistor a effet de champ mos de grandeur inferieure au micron et a couche ultrafine avec canal intrinseque - Google Patents

Transistor a effet de champ mos de grandeur inferieure au micron et a couche ultrafine avec canal intrinseque Download PDF

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Publication number
WO1990006595A1
WO1990006595A1 PCT/US1989/005327 US8905327W WO9006595A1 WO 1990006595 A1 WO1990006595 A1 WO 1990006595A1 US 8905327 W US8905327 W US 8905327W WO 9006595 A1 WO9006595 A1 WO 9006595A1
Authority
WO
WIPO (PCT)
Prior art keywords
channel
fet
channel region
gate
voltage
Prior art date
Application number
PCT/US1989/005327
Other languages
English (en)
Inventor
Kyle W. Terrill
Prahalad K. Vasudev
Original Assignee
Hughes Aircraft Company
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hughes Aircraft Company filed Critical Hughes Aircraft Company
Publication of WO1990006595A1 publication Critical patent/WO1990006595A1/fr

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6744—Monocrystalline silicon

Definitions

  • the present inven ⁇ tion seeks to provide an ultrathin MOSFET with submicro- eter channel lengths that avoids punchthrough and other short-channel effects encountered in conventional bulk MOSFETs, but in addition has excellent turn-off, sub- threshold and transconductance characteristics.
  • FIG. 4 shows that, although the field lines emanating from the source and drain approach somewhat more closely with a channel region that is more nearly true intrinsic, punchthrough still does not occur.

Landscapes

  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

Le transistor à effet de champ MOS décrit, de grandeur inférieure au micron, est fabriqué sur une couche ultrafine (16) avec un canal généralement intrinsèque (14) ayant une concentration de dopant inférieure à environ 1016cm-3. L'épaisseur du canal (14) est de préférence inférieure ou égale à environ 0,2 micron. Le rapport entre l'épaisseur et la longueur du canal est inférieur à environ 1/4 et de préférence inférieur ou égal à environ 1/2. Les effets de tension de perçage et les effets produits par la longueur réduite du canal sont évités grâce à l'application d'une tension de gâchette arrière appropriée, qu'on peut également faire varier pour régler le seuil de tension.
PCT/US1989/005327 1988-12-09 1989-11-27 Transistor a effet de champ mos de grandeur inferieure au micron et a couche ultrafine avec canal intrinseque WO1990006595A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US28215088A 1988-12-09 1988-12-09
US282,150 1988-12-09

Publications (1)

Publication Number Publication Date
WO1990006595A1 true WO1990006595A1 (fr) 1990-06-14

Family

ID=23080318

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1989/005327 WO1990006595A1 (fr) 1988-12-09 1989-11-27 Transistor a effet de champ mos de grandeur inferieure au micron et a couche ultrafine avec canal intrinseque

Country Status (3)

Country Link
EP (1) EP0401356A1 (fr)
JP (1) JPH03503227A (fr)
WO (1) WO1990006595A1 (fr)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0473397A1 (fr) * 1990-08-27 1992-03-04 Sharp Kabushiki Kaisha Méthode de fabrication d'un transistor MOS à double grille
EP0480373A3 (en) * 1990-10-09 1993-03-10 Seiko Epson Corporation Thin-film semiconductor device
EP0534131A3 (en) * 1991-09-27 1993-10-06 Siemens Aktiengesellschaft Mos technique in soi technique
WO1993021659A1 (fr) * 1992-04-15 1993-10-28 British Technology Group Ltd. Dispositifs semi-conducteurs a grille double
EP0621644A3 (en) * 1993-04-23 1995-08-16 Ibm Semiconductor-on-insulator field-effect transistor.
EP1034568B1 (fr) * 1997-11-28 2013-03-13 QinetiQ Limited Transistor a effet de champ

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4748485A (en) * 1985-03-21 1988-05-31 Hughes Aircraft Company Opposed dual-gate hybrid structure for three-dimensional integrated circuits

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4748485A (en) * 1985-03-21 1988-05-31 Hughes Aircraft Company Opposed dual-gate hybrid structure for three-dimensional integrated circuits

Non-Patent Citations (5)

* Cited by examiner, † Cited by third party
Title
Electronics Letters, Volume 24, No. 4, 18 February 1988, (Hitchin, Herts, GB), S.S. TSAO et al.: "Gate Coupling and Floating-Body Effects in Thin-Film SOI MOSFETs", pages 238-239 *
Extended Abstracts of the 19th Conference on Solid State Devices and Materials, Tokyo, Japan, 25-27 August 1987, H. HAYASHI et al.: "High Performance Superthin Film Transistor (SFT) with Twin Gates", pages 59-62, see Abstract; paragraph 2 *
IEEE Electron Device Letters, Volume EDL-8, No. 9, September 1987, IEEE, (New York, US), F. BALESTRA et al.: "Double-Gate Silicon-on-Insulator Transistor with Volume Inversion: A New Device with Greatly Enhanced Performance", pages 410-412 *
International Electron Devices Meeting, Washington, D.C., IEEE, (US), 6-9 December 1987, M. TOSHIMI et al.: "High Performance SOIMOSFET using Ultra-Thin SOI Film", pages 640-643 *
PATENT ABSTRACTS OF JAPAN, Volume 9 No. 181 (E-331) (1904), 26 July 1985; & JP-A-6052058 (Komatsu Seisakusho K.K.) 23 March 1985 *

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0473397A1 (fr) * 1990-08-27 1992-03-04 Sharp Kabushiki Kaisha Méthode de fabrication d'un transistor MOS à double grille
EP0480373A3 (en) * 1990-10-09 1993-03-10 Seiko Epson Corporation Thin-film semiconductor device
US5294821A (en) * 1990-10-09 1994-03-15 Seiko Epson Corporation Thin-film SOI semiconductor device having heavily doped diffusion regions beneath the channels of transistors
EP0534131A3 (en) * 1991-09-27 1993-10-06 Siemens Aktiengesellschaft Mos technique in soi technique
WO1993021659A1 (fr) * 1992-04-15 1993-10-28 British Technology Group Ltd. Dispositifs semi-conducteurs a grille double
US5677550A (en) * 1992-04-15 1997-10-14 British Technology Group Limited Integrated circuit devices including insulated-gate transistor device having two separately biasable gates
EP0621644A3 (en) * 1993-04-23 1995-08-16 Ibm Semiconductor-on-insulator field-effect transistor.
EP1034568B1 (fr) * 1997-11-28 2013-03-13 QinetiQ Limited Transistor a effet de champ

Also Published As

Publication number Publication date
EP0401356A1 (fr) 1990-12-12
JPH03503227A (ja) 1991-07-18

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