US3001089A - Transistor memory system - Google Patents

Description

This invention relates to a circuit arrangement comprising a chain of transistors in which each transistor, in the presence of free charge storage in its base zone, determines the free charge storage in the base zone of a succeeding transistor of the chain by means of interrogating pulses which act as a collector supply voltage. Such a circuit arrangement -is described in co-pending patent specification Serial No. 625,726, liled December 3, 1956. The arrangement may be used yfor shifting infomation given in binary code, for example in calculating machines or in automatic telephony.

The arrangements described in said co-pending patent specification invariably require the use of a base separating rectifier in order to maintain the base at a floating potential during the occurrence of the said interrogating pulses. The present invention .provides a circuit arrangement in which these separating rectiiiers can be dispensed with. It is characterized in that the collector of a preceding transistor of the chain is connected, through a resistor conducting in both directions, to the base of a succeeding transistor, said resistor together with a resistor included in the collector circuit of the preceding transistor being sufficiently large to prevent any free charge storage lof the second transistor from flowing away in the interval between two interrogating pulses supplied to said second transistor.

The invention is based on the recognition that, if a succeeding transistor is controlled from the collector of a preceding transistor, the values of the resistors used can be made so high that even if the said separating rectiiier is omitted (the collector of the preceding transistor thus being connected to the base of the succeeding transistor through a resistor conducting in both directions) the base potential can be assumed to remain floating.

In order that the invention may readily be carried into etect, one embodiment thereof will now be described with reference to the accompanying diagrammatic drawings, in which FIG. l shows a circuit arrangement in accordance with the `invention and FIG. 2 shows voltage-time diagrams and current-time diagrams illustrating the arrangement shown in FIG. l.

In FIG. l, reference numerals 1, 2, 3, 4, 5, 6 designate a number of transistors which, in the presence of free charge storage in their base zones, by means of interrogatin-g pulses A, B acting as collector supply voltage pass current through corresponding collector resistors 7, 8, 9, 10, l1, 12. Erasing pulses supplied from sources A' and B' respectively carry off any 'free charge remaining in the base zones through separating rectifiers 13, 14, `15, 16, 17 and 18. The collector of each transistor is connected to the base of the succeeding transistor by resistors 19, 20, 21, 22 and 23 conducting in both directions.

The circuit arrangement operates as follows:

It is first assumed that initially no transistor contains -free charge storage. lf, now, the interrogating pulse A (FIG. 2) is received, currents ow via resistors 19, 2.1, 23 through the bases of the even-numbered transistors 2., yIt, 6 and inject a free charge storage into the base zones thereof. It, now, the interrogating pulse B (FIG. 2) is received, these transistors 2, l4, 6 will be so highly conductive that, also owing to the preceding resistors 20, Z2

States Patent ice and the base-emitter threshold voltage of these odd-numbered transistors 3, 5, a negligible current remains available yfor the basses of the odd-numbered transistors.

If, now, free charge storage is imparted to the transistor 1, for example by means of incident light or by supplying current to its base for a short period of time, a current I1 will pass through this transistor at the instant at which the interrogating pulse A is supplied, so that a negligible current ows through `the base of the transistor 2 and consequently this transistor 2 is not conductive at the instant at which the interrogating pulse B is received. Since at the end of an interrogating pulse any free charge storage is immediately removed by the erasing pulses A or B respectively, no current will subsequently flow through the transistor 1, so that each time subsequent to the rst pulse B free charge storage isl produced in the transistor 2 and a corresponding collector current flows in this transistor. Thus, the collector current of the transistor Z is shown as a function of time by I2 in FIG. 2. Since this transistor was non-conductive during the yfirst interrogating pulse B, at this instant base current is supplied to the transistor 3 through the resistor 20, so that this transistor passes the current I3 at the next subsequent interrogating pulse A, and so on.

Thus, during the interrogating pulses A the transistors 1, 3, 5 become conductive in sequence, that is to say, the ffree charge storage injected into the transistor 1 as information to the next odd-numbered transistor at each succeeding interrogating pulse A. Likewise, the absence of yfree charge storage of the even-numbered transistors is shifted to the next even-numbered transistor at each interrogating pulse B.

For satisfactory operation it is required that in the intenvals between two interrogating pulses any free charge storage which may have been injected has not leaked away. To this end, the resistors used, particularly the sum of the collector and 4the base resistors must be suiciently large. In practice, good results were obtained with resistors of 6009 at a repetition frequency of the interrogating pulses of kc./s. However, such large resistors can be used Without diiculty, ras has been described hereinbefore.

What is claimed is:

l. A transistor memory system comprising at least two stages connected in cascade arrangement, each stage including a transistor having an emitter, la collector and a base, said base having the property of storing a free charge in response to current passed therein, means connected to apply current to the base of a rst one of said transistors to cause a free charge to be stored therein, means for applying interrogating pulses to the respective emitter-collector circuits of said transistors,y said interro- -gating pulses being the sole means of potential supply for said emitter-collector circuits, load resistors connected respectively in the collector circuit of each transistor, and bi-directionally conducting coupling resistors each connected respectively between the base of each transistor and the collector of the transistor of the preceding stage, the value of each coupling resistor and its associated load resistor being sufficiently large to prevent a free charge stored in the base to which the coupling resistor is connected from leaking away during the time interval between two successive interrogating pulses applied to the transistor containing said base, each coupling resistor operating to couple pulses to the next one when an interrogating pulse is applied to the preceding stage dependent on the presence of free charge in the base of the transistor of the preceding stage.

2. A transistor memory system comprising a plurality of stages connected in cascade arrangement, each stage including a transistor having an emitter, a collector and 3 a ba'se,-said base having the property of storing a free charge in response to cur-rent passed therein, means connected -to apply current to the base of a rst one of said transistors Ito cause a free charge to =be stored therein, rneans for applying interrogating pulses to the respective emitteracollector circuits of said transistors, said interrogating pulses being supplied alternately in time to the oddand even-numbered stages respectively, said interro gating pulses being the sole means of potential supply -for said emitter-collector circuits, load resistors connected respectively in the collector circuit of each transistor, and bi-directionally conducting coupling resistors each connected respectively between the base of each transistor and the collector of the transistor of the next preceding stage, each coupling resistor and its associated load resistor having magnitudes suilicient to prevent any free charge stored in the base to which the coupling resistor is connected from leaking away during the time interval kefeienees Cited in the file of this patent UNITED STATES PATENTS `2,594,336 Mohr Apr. 29, 1952 2,644,892 Gehman July 7, 1953 2,548,658 AMitchell V Aug. 19,- 1958 2,877,357 Pears-all et al Mar. 10-, 1959 2,910,596 Carlson Oct. 27, 1959 FOREIGN PATENTS 733,638 e Greafritain T1/ July 13, 1955

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