+

US20230369448A1 - High electron mobility transistor and method for fabricating the same - Google Patents

High electron mobility transistor and method for fabricating the same Download PDF

Info

Publication number
US20230369448A1
US20230369448A1 US18/221,396 US202318221396A US2023369448A1 US 20230369448 A1 US20230369448 A1 US 20230369448A1 US 202318221396 A US202318221396 A US 202318221396A US 2023369448 A1 US2023369448 A1 US 2023369448A1
Authority
US
United States
Prior art keywords
barrier layer
type semiconductor
forming
semiconductor layer
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
US18/221,396
Inventor
Bo-Rong Chen
Che-Hung Huang
Chun-Ming Chang
Yi-Shan Hsu
Chih-Tung Yeh
Shin-Chuan Huang
Wen-Jung Liao
Chun-Liang Hou
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
United Microelectronics Corp
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to US18/221,396 priority Critical patent/US20230369448A1/en
Publication of US20230369448A1 publication Critical patent/US20230369448A1/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H01L29/66462—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H01L29/2003—
    • H01L29/7783—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/473—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT
    • H10D30/4732—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT using Group III-V semiconductor material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/343—Gate regions of field-effect devices having PN junction gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/824—Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions

Definitions

  • the invention relates to a high electron mobility transistor (HEMT) and method for fabricating the same.
  • HEMT high electron mobility transistor
  • High electron mobility transistor (HEMT) fabricated from GaN-based materials have various advantages in electrical, mechanical, and chemical aspects of the field. For instance, advantages including wide band gap, high break down voltage, high electron mobility, high elastic modulus, high piezoelectric and piezoresistive coefficients, and chemical inertness. All of these advantages allow GaN-based materials to be used in numerous applications including high intensity light emitting diodes (LEDs), power switching devices, regulators, battery protectors, display panel drivers, and communication devices.
  • LEDs high intensity light emitting diodes
  • a method for fabricating high electron mobility transistor includes the steps of: forming a first barrier layer on a substrate; forming a p-type semiconductor layer on the first barrier layer; forming a hard mask on the p-type semiconductor layer; patterning the hard mask and the p-type semiconductor layer; and forming a spacer adjacent to the hard mask and the p-type semiconductor layer.
  • a method for fabricating high electron mobility transistor includes the steps of: forming a first barrier layer on a substrate; forming a p-type semiconductor layer on the first barrier layer; patterning the p-type semiconductor layer; and forming a spacer adjacent to the p-type semiconductor layer.
  • a high electron mobility transistor includes: a buffer layer on a substrate; a first barrier layer on the buffer layer; a p-type semiconductor layer on the first barrier layer; and a spacer adjacent to the p-type semiconductor layer.
  • FIGS. 1 - 5 illustrate a method for fabricating a HEMT according to an embodiment of the present invention.
  • FIG. 6 illustrates a structural view of a HEMT according to an embodiment of the present invention.
  • FIGS. 7 - 12 illustrate a method for fabricating a HEMT according to an embodiment of the present invention.
  • FIGS. 1 - 5 illustrate a method for fabricating a HEMT according to an embodiment of the present invention.
  • a substrate 12 such as a substrate made from silicon, silicon carbide, or aluminum oxide (or also referred to as sapphire) is provided, in which the substrate 12 could be a single-layered substrate, a multi-layered substrate, gradient substrate, or combination thereof.
  • the substrate 12 could also include a silicon-on-insulator (SOI) substrate.
  • SOI silicon-on-insulator
  • the buffer layer 14 is preferably made of III-V semiconductors such as gallium nitride (GaN), in which a thickness of the buffer layer 14 could be between 0.5 microns to 10 microns.
  • the formation of the buffer layer 14 could be accomplished by a molecular-beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, a chemical vapor deposition (CVD) process, a hydride vapor phase epitaxy (HVPE) process, or combination thereof.
  • MBE molecular-beam epitaxy
  • MOCVD metal organic chemical vapor deposition
  • CVD chemical vapor deposition
  • HVPE hydride vapor phase epitaxy
  • a first barrier layer 16 is formed on the surface of the buffer layer 14 .
  • the first barrier layer 16 is preferably made of III-V semiconductor such as aluminum gallium nitride (Al x Ga 1-x N), in which 0 ⁇ x ⁇ 1, x being less than or equal to 20%, and the first barrier layer 16 preferably includes an epitaxial layer formed through epitaxial growth process. Similar to the buffer layer 14 , the formation of the first barrier layer 16 on the buffer layer 14 could be accomplished by a molecular-beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, a chemical vapor deposition (CVD) process, a hydride vapor phase epitaxy (HVPE) process, or combination thereof.
  • MBE molecular-beam epitaxy
  • MOCVD metal organic chemical vapor deposition
  • CVD chemical vapor deposition
  • HVPE hydride vapor phase epitaxy
  • the p-type semiconductor layer 18 is preferably a III-V compound layer including p-type GaN (p-GaN) and the formation of the p-type semiconductor layer 18 on the first barrier layer 16 could be accomplished by a molecular-beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, a chemical vapor deposition (CVD) process, a hydride vapor phase epitaxy (HVPE) process, or combination thereof.
  • the hard mask 20 could include dielectric, conductive, or metal material including but not limited to for example silicon nitride, silicon oxide, or titanium nitride.
  • a pattern transfer process is conducted to pattern the hard mask 20 and the p-type semiconductor layer 18 by first using a patterned mask (not shown) as mask to remove part of the hard mask 20 and part of the p-type semiconductor layer 18 for exposing the surface of the first barrier layer 16 adjacent to two sides of the patterned p-type semiconductor layer 18 , in which the patterned p-type semiconductor layer 18 preferably becomes a part of the gate structure of the HEMT in the later process.
  • the pattern transfer process conducted at this stage preferably removes all of the remaining p-type semiconductor layer 18 adjacent to two sides of the patterned p-type semiconductor layer 18 during the patterning process to expose the surface of the first barrier layer 16 so that the top surface of the first barrier layer 16 adjacent to two sides of the patterned p-type semiconductor layer 18 could be even with or slightly lower than the top surface of the first barrier layer 16 directly under the p-type semiconductor layer 18 .
  • a spacer 22 is formed adjacent to the hard mask 20 and the p-type semiconductor layer 18 .
  • the formation of the spacer 22 could be accomplished by first forming a liner (not shown) made of dielectric material on the substrate 12 to cover the first barrier layer 16 and the hard mask 20 , and an etching back process is conducted to remove part of the liner for forming a spacer 22 on sidewalls of the p-type semiconductor layer 18 and the hard mask 20 , in which the top surface of the spacer 22 is preferably even with the top surface of the hard mask 20 .
  • each of the spacers 22 could include an I-shape and/or L-shape cross-section and each of the spacers could include silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbon nitride (SiCN), or combination thereof.
  • a second barrier layer 24 is formed on the surface of the first barrier layer 16 adjacent to two sides of the spacer 22 .
  • the first barrier layer 16 and the second barrier layer 24 are made of III-V semiconductor such as aluminum gallium nitride (Al x Ga 1-x N) and each of the two layers includes an epitaxial layer formed through epitaxial growth process.
  • the first barrier layer 16 and the second barrier layer 24 preferably include different thicknesses such as the thickness of the first barrier layer 16 is preferably less than the thickness of the second barrier layer 24 .
  • the first barrier layer 16 and the second barrier layer 24 preferably include different concentrations of aluminum or more specifically the aluminum concentration of the first barrier layer 16 is less than the aluminum concentration of the second barrier layer 24 .
  • the first barrier layer 16 is made of III-V semiconductor such as aluminum gallium nitride (Al x Ga 1-x N), in which 0 ⁇ x ⁇ 1, x being 5-15% and the second barrier layer 24 is made of III-V semiconductor such as aluminum gallium nitride (Al x Ga 1-x N), in which 0 ⁇ x ⁇ 1, x being 15-50%.
  • the formation of the second barrier layer 24 on the first buffer layer 16 could be accomplished by a molecular-beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, a chemical vapor deposition (CVD) process, a hydride vapor phase epitaxy (HVPE) process, or combination thereof.
  • MBE molecular-beam epitaxy
  • MOCVD metal organic chemical vapor deposition
  • CVD chemical vapor deposition
  • HVPE hydride vapor phase epitaxy
  • a passivation layer 26 is formed on the surfaces of the second barrier layer 24 , the spacer 22 , and the hard mask 20 , and a gate electrode 28 is formed on the hard mask 20 and a source electrode 30 and a drain electrode 32 are formed adjacent to two sides of the gate electrode 28 , in which the p-type semiconductor layer 18 , the hard mask 20 , and the gate electrode 28 could constitute a gate structure 34 altogether.
  • the hard mask 20 in this embodiment is preferably made of conductive material such as titanium nitride (TiN) so that the gate electrode 28 could be disposed directly on the surface of the hard mask 20 without contacting the p-type semiconductor layer 18 directly.
  • the gate electrode 28 , the source electrode 30 , and the drain electrode 32 are preferably made of metal, in which the gate electrode 28 is preferably made of Schottky metal while the source electrode 30 and the drain electrode 32 are preferably made of ohmic contact metals.
  • each of the gate electrode 28 , source electrode 30 , and drain electrode 32 could include gold (Au), Silver (Ag), platinum (Pt), titanium (Ti), aluminum (Al), tungsten (W), palladium (Pd), or combination thereof.
  • gold Au
  • Silver Au
  • platinum Pt
  • titanium Ti
  • aluminum Al
  • tungsten W
  • palladium Pd
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • FIG. 6 illustrates a structural view of a HEMT according to an embodiment of the present invention.
  • the HEMT similar to the embodiment disclosed in FIG. 5 also includes a buffer layer 14 disposed on the substrate 12 , a first barrier layer 16 disposed on the buffer layer 14 , a p-type semiconductor layer 18 disposed on the first barrier layer 16 , a gate electrode 28 disposed on the p-type semiconductor layer 18 , a hard mask 20 disposed on the p-type semiconductor layer 18 , a spacer 22 disposed adjacent to the p-type semiconductor layer 18 and the hard mask 20 , a second barrier layer 24 disposed on the first barrier layer 16 adjacent to the spacer 22 , and a source electrode 30 and drain electrode 32 disposed on the second barrier layer 24 adjacent to two sides of the spacer 22 .
  • the hard mask 20 in this embodiment could be made of conductive or dielectric material including but not limited to for example TiN, silicon oxide, or silicon nitride.
  • the gate electrode 28 penetrating the hard mask 20 and contacting the surface of the p-type semiconductor layer 18 directly, or if viewed from another perspective the hard mask 20 is disposed on the p-type semiconductor layer 18 and surrounding the gate electrode 28 .
  • FIGS. 7 - 12 illustrate a method for fabricating a HEMT according to an embodiment of the present invention.
  • a substrate 42 such as a substrate made from silicon, silicon carbide, or aluminum oxide (or also referred to as sapphire) is provided, in which the substrate 42 could be a single-layered substrate, a multi-layered substrate, gradient substrate, or combination thereof.
  • the substrate 42 could also include a silicon-on-insulator (SOI) substrate.
  • SOI silicon-on-insulator
  • the buffer layer 44 is preferably made of III-V semiconductors such as gallium nitride (GaN), in which a thickness of the buffer layer 44 could be between 0.5 microns to 10 microns.
  • the formation of the buffer layer 44 could be accomplished by a molecular-beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, a chemical vapor deposition (CVD) process, a hydride vapor phase epitaxy (HVPE) process, or combination thereof.
  • MBE molecular-beam epitaxy
  • MOCVD metal organic chemical vapor deposition
  • CVD chemical vapor deposition
  • HVPE hydride vapor phase epitaxy
  • a first barrier layer 46 is formed on the surface of the buffer layer 44 .
  • the first barrier layer 46 is preferably made of III-V semiconductor such as aluminum gallium nitride (Al x Ga 1-x N), in which 0 ⁇ x ⁇ 1, x being less than or equal to 20%, and the first barrier layer 46 preferably includes an epitaxial layer formed through epitaxial growth process. Similar to the buffer layer 44 , the formation of the first barrier layer 46 on the buffer layer 44 could be accomplished by a molecular-beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, a chemical vapor deposition (CVD) process, a hydride vapor phase epitaxy (HVPE) process, or combination thereof.
  • MBE molecular-beam epitaxy
  • MOCVD metal organic chemical vapor deposition
  • CVD chemical vapor deposition
  • HVPE hydride vapor phase epitaxy
  • a p-type semiconductor layer 48 is formed on the surface of the first barrier layer 46 .
  • the p-type semiconductor layer 48 is preferably a III-V compound layer including p-type GaN (p-GaN) and the formation of the p-type semiconductor layer 48 on the first barrier layer 46 could be accomplished by a molecular-beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, a chemical vapor deposition (CVD) process, a hydride vapor phase epitaxy (HVPE) process, or combination thereof.
  • MBE molecular-beam epitaxy
  • MOCVD metal organic chemical vapor deposition
  • CVD chemical vapor deposition
  • HVPE hydride vapor phase epitaxy
  • a pattern transfer process is conducted to pattern the p-type semiconductor layer 48 by first using a patterned mask (not shown) as mask to remove part of part of the p-type semiconductor layer 48 for exposing the surface of the first barrier layer 46 adjacent to two sides of the patterned p-type semiconductor layer 48 , in which the patterned p-type semiconductor layer 48 preferably becomes a part of the gate structure of the HEMT in the later process.
  • a patterned mask not shown
  • the pattern transfer process conducted at this stage preferably removes all of the remaining p-type semiconductor layer 48 adjacent to two sides of the patterned p-type semiconductor layer 48 during the patterning process to expose the surface of the first barrier layer 46 so that the top surface of the first barrier layer 46 adjacent to two sides of the patterned p-type semiconductor layer 48 could be even with or slightly lower than the top surface of the first barrier layer 46 directly under the p-type semiconductor layer 48 .
  • a spacer 50 is formed adjacent to the p-type semiconductor layer 48 .
  • the formation of the spacer 50 could be accomplished by first forming a liner (not shown) made of dielectric material on the substrate 42 to cover the first barrier layer 46 and p-type semiconductor layer 48 , and an etching back process is conducted to remove part of the liner for forming a spacer 50 on sidewalls of the p-type semiconductor layer 48 . Since no hard mask is formed on top of the p-type semiconductor layer 48 , the top surface of the spacer 50 is preferably even with the top surface of the p-type semiconductor layer 48 .
  • each of the spacers 50 could include an I-shape and/or L-shape cross-section and each of the spacers could include silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbon nitride (SiCN), or combination thereof, which are all within the scope of the present invention.
  • a second barrier layer 52 is formed on the surface of the first barrier layer 46 adjacent to two sides of the spacer 50 and the top surface of the p-type semiconductor layer 48 .
  • the first barrier layer 46 and the second barrier layer 52 are made of III-V semiconductor such as aluminum gallium nitride (Al x Ga 1-x N) and each of the two layers includes an epitaxial layer formed through epitaxial growth process.
  • the first barrier layer 46 and the second barrier layer 52 preferably include different thicknesses such as the thickness of the first barrier layer 46 is preferably less than the thickness of the second barrier layer 52 .
  • the first barrier layer 46 and the second barrier layer 52 preferably include different concentrations of aluminum or more specifically the aluminum concentration of the first barrier layer 46 is less than the aluminum concentration of the second barrier layer 52 .
  • the first barrier layer 46 is made of III-V semiconductor such as aluminum gallium nitride (Al x Ga 1-x N), in which 0 ⁇ x ⁇ 1, x being 5-15% and the second barrier layer 52 is made of III-V semiconductor such as aluminum gallium nitride (Al x Ga 1-x N), in which 0 ⁇ x ⁇ 1, x being 15-50%.
  • the formation of the second barrier layer 52 on the first buffer layer 46 could be accomplished by a molecular-beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, a chemical vapor deposition (CVD) process, a hydride vapor phase epitaxy (HVPE) process, or combination thereof.
  • MBE molecular-beam epitaxy
  • MOCVD metal organic chemical vapor deposition
  • CVD chemical vapor deposition
  • HVPE hydride vapor phase epitaxy
  • a hard mask 54 is formed to cover the second barrier layer 52 and the exposed spacer 50 entirely.
  • the hard mask 54 could include be made of conductive or dielectric material including but not limited to for example silicon oxide, silicon nitride, TiN, or aluminum oxide (AlO).
  • a planarizing process such as chemical mechanical polishing (CMP) process is conducted to remove part of the hard mask 54 and the entire second barrier layer 52 disposed directly on top of the p-type semiconductor layer 48 so that the top surface of the remaining hard mask 54 adjacent to two sides of the spacer 50 is even with the top surface of the p-type semiconductor layer 48 .
  • CMP chemical mechanical polishing
  • a passivation layer 56 is formed on the surface of the hard mask 54 , and a gate electrode 58 is formed in the passivation layer 56 on top of the p-type semiconductor layer 48 and a source electrode 60 and a drain electrode 62 are formed adjacent to two sides of the gate electrode 58 , in which the p-type semiconductor layer 48 and the gate electrode 58 could constitute a gate structure 64 altogether.
  • the gate electrode 58 , the source electrode 60 , and the drain electrode 62 are preferably made of metal, in which the gate electrode 58 is preferably made of Schottky metal while the source electrode 60 and the drain electrode 62 are preferably made of ohmic contact metals.
  • each of the gate electrode 58 , source electrode 60 , and drain electrode 62 could include gold (Au), Silver (Ag), platinum (Pt), titanium (Ti), aluminum (Al), tungsten (W), palladium (Pd), or combination thereof.
  • a HEMT HEMT
  • electroplating process sputtering process, resistance heating evaporation process, electron beam evaporation process, physical vapor deposition (PVD) process, chemical vapor deposition (CVD) process, or combination thereof to form electrode materials in the aforementioned recesses, and then pattern the electrode materials through one or more etching processes to form the gate electrode 58 , source electrode 60 , and the drain electrode 62 .
  • PVD physical vapor deposition
  • CVD chemical vapor deposition

Landscapes

  • Junction Field-Effect Transistors (AREA)
  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Materials Engineering (AREA)

Abstract

A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a first barrier layer on a substrate; forming a p-type semiconductor layer on the first barrier layer; forming a hard mask on the p-type semiconductor layer; patterning the hard mask and the p-type semiconductor layer; and forming a spacer adjacent to the hard mask and the p-type semiconductor layer.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This application is a division of U.S. application Ser. No. 16/731,058, filed on Dec. 31, 2019. The content of the application is incorporated herein by reference.
    • BACKGROUND OF THE INVENTION 1. Field of the Invention
  • The invention relates to a high electron mobility transistor (HEMT) and method for fabricating the same.
    • 2. Description of the Prior Art
  • High electron mobility transistor (HEMT) fabricated from GaN-based materials have various advantages in electrical, mechanical, and chemical aspects of the field. For instance, advantages including wide band gap, high break down voltage, high electron mobility, high elastic modulus, high piezoelectric and piezoresistive coefficients, and chemical inertness. All of these advantages allow GaN-based materials to be used in numerous applications including high intensity light emitting diodes (LEDs), power switching devices, regulators, battery protectors, display panel drivers, and communication devices.
    • SUMMARY OF THE INVENTION
  • According to an embodiment of the present invention, a method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a first barrier layer on a substrate; forming a p-type semiconductor layer on the first barrier layer; forming a hard mask on the p-type semiconductor layer; patterning the hard mask and the p-type semiconductor layer; and forming a spacer adjacent to the hard mask and the p-type semiconductor layer.
  • According to another aspect of the present invention, a method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a first barrier layer on a substrate; forming a p-type semiconductor layer on the first barrier layer; patterning the p-type semiconductor layer; and forming a spacer adjacent to the p-type semiconductor layer.
  • According to yet another aspect of the present invention, a high electron mobility transistor (HEMT) includes: a buffer layer on a substrate; a first barrier layer on the buffer layer; a p-type semiconductor layer on the first barrier layer; and a spacer adjacent to the p-type semiconductor layer.
  • These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGS. 1-5 illustrate a method for fabricating a HEMT according to an embodiment of the present invention.
  • FIG. 6 illustrates a structural view of a HEMT according to an embodiment of the present invention.
  • FIGS. 7-12 illustrate a method for fabricating a HEMT according to an embodiment of the present invention.
    •  DETAILED DESCRIPTION
  • Referring to the FIGS. 1-5 , FIGS. 1-5 illustrate a method for fabricating a HEMT according to an embodiment of the present invention. As shown in the FIG. 1 , a substrate 12 such as a substrate made from silicon, silicon carbide, or aluminum oxide (or also referred to as sapphire) is provided, in which the substrate 12 could be a single-layered substrate, a multi-layered substrate, gradient substrate, or combination thereof. According to other embodiment of the present invention, the substrate 12 could also include a silicon-on-insulator (SOI) substrate.
  • Next, a buffer layer 14 is formed on the substrate 12. According to an embodiment of the present invention, the buffer layer 14 is preferably made of III-V semiconductors such as gallium nitride (GaN), in which a thickness of the buffer layer 14 could be between 0.5 microns to 10 microns. According to an embodiment of the present invention, the formation of the buffer layer 14 could be accomplished by a molecular-beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, a chemical vapor deposition (CVD) process, a hydride vapor phase epitaxy (HVPE) process, or combination thereof.
  • Next, a first barrier layer 16 is formed on the surface of the buffer layer 14. In this embodiment, the first barrier layer 16 is preferably made of III-V semiconductor such as aluminum gallium nitride (AlxGa1-xN), in which 0<x<1, x being less than or equal to 20%, and the first barrier layer 16 preferably includes an epitaxial layer formed through epitaxial growth process. Similar to the buffer layer 14, the formation of the first barrier layer 16 on the buffer layer 14 could be accomplished by a molecular-beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, a chemical vapor deposition (CVD) process, a hydride vapor phase epitaxy (HVPE) process, or combination thereof.
  • Next, a p-type semiconductor layer 18 and a hard mask 20 are sequentially formed on the surface of the first barrier layer 16. In this embodiment, the p-type semiconductor layer 18 is preferably a III-V compound layer including p-type GaN (p-GaN) and the formation of the p-type semiconductor layer 18 on the first barrier layer 16 could be accomplished by a molecular-beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, a chemical vapor deposition (CVD) process, a hydride vapor phase epitaxy (HVPE) process, or combination thereof. The hard mask 20 could include dielectric, conductive, or metal material including but not limited to for example silicon nitride, silicon oxide, or titanium nitride.
  • Next, as shown in FIG. 2 , a pattern transfer process is conducted to pattern the hard mask 20 and the p-type semiconductor layer 18 by first using a patterned mask (not shown) as mask to remove part of the hard mask 20 and part of the p-type semiconductor layer 18 for exposing the surface of the first barrier layer 16 adjacent to two sides of the patterned p-type semiconductor layer 18, in which the patterned p-type semiconductor layer 18 preferably becomes a part of the gate structure of the HEMT in the later process. It should be noted that to prevent a continuous p-type semiconductor layer 18 from inducing a micro loading effect, the pattern transfer process conducted at this stage preferably removes all of the remaining p-type semiconductor layer 18 adjacent to two sides of the patterned p-type semiconductor layer 18 during the patterning process to expose the surface of the first barrier layer 16 so that the top surface of the first barrier layer 16 adjacent to two sides of the patterned p-type semiconductor layer 18 could be even with or slightly lower than the top surface of the first barrier layer 16 directly under the p-type semiconductor layer 18.
  • Next, as shown in FIG. 3 , a spacer 22 is formed adjacent to the hard mask 20 and the p-type semiconductor layer 18. Specifically, the formation of the spacer 22 could be accomplished by first forming a liner (not shown) made of dielectric material on the substrate 12 to cover the first barrier layer 16 and the hard mask 20, and an etching back process is conducted to remove part of the liner for forming a spacer 22 on sidewalls of the p-type semiconductor layer 18 and the hard mask 20, in which the top surface of the spacer 22 is preferably even with the top surface of the hard mask 20. It should be noted that even though the spacer 22 pertains to be a single spacer in this embodiment, it would also be desirable to adjust the number of the liner being deposited to form one or more spacers including two, three, or even four spacers on sidewalls of the p-type semiconductor layer 18 and the hard mask 20. Preferably, each of the spacers 22 could include an I-shape and/or L-shape cross-section and each of the spacers could include silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbon nitride (SiCN), or combination thereof.
  • Next, as shown in FIG. 4 , a second barrier layer 24 is formed on the surface of the first barrier layer 16 adjacent to two sides of the spacer 22. Preferably, the first barrier layer 16 and the second barrier layer 24 are made of III-V semiconductor such as aluminum gallium nitride (AlxGa1-xN) and each of the two layers includes an epitaxial layer formed through epitaxial growth process. In this embodiment, the first barrier layer 16 and the second barrier layer 24 preferably include different thicknesses such as the thickness of the first barrier layer 16 is preferably less than the thickness of the second barrier layer 24.
  • Moreover, the first barrier layer 16 and the second barrier layer 24 preferably include different concentrations of aluminum or more specifically the aluminum concentration of the first barrier layer 16 is less than the aluminum concentration of the second barrier layer 24. For instance, the first barrier layer 16 is made of III-V semiconductor such as aluminum gallium nitride (AlxGa1-xN), in which 0<x<1, x being 5-15% and the second barrier layer 24 is made of III-V semiconductor such as aluminum gallium nitride (AlxGa1-xN), in which 0<x<1, x being 15-50%. Similar to the formation of the first barrier layer 16, the formation of the second barrier layer 24 on the first buffer layer 16 could be accomplished by a molecular-beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, a chemical vapor deposition (CVD) process, a hydride vapor phase epitaxy (HVPE) process, or combination thereof.
  • Next, as shown in FIG. 5 , a passivation layer 26 is formed on the surfaces of the second barrier layer 24, the spacer 22, and the hard mask 20, and a gate electrode 28 is formed on the hard mask 20 and a source electrode 30 and a drain electrode 32 are formed adjacent to two sides of the gate electrode 28, in which the p-type semiconductor layer 18, the hard mask 20, and the gate electrode 28 could constitute a gate structure 34 altogether. In this embodiment, it would be desirable to conduct a photo-etching process to remove part of the passivation layer 26 directly on top of the p-type semiconductor layer 18 or hard mask 20 to form a recess (not shown), form a gate electrode 28 in the recess, remove part of the passivation layer 26 adjacent to two sides of the spacer 22 to form two recesses, and then form source electrode 30 and drain electrode 32 in the two recesses adjacent to two sides of the gate electrode 28.
  • It should be noted that the hard mask 20 in this embodiment is preferably made of conductive material such as titanium nitride (TiN) so that the gate electrode 28 could be disposed directly on the surface of the hard mask 20 without contacting the p-type semiconductor layer 18 directly. Moreover, the gate electrode 28, the source electrode 30, and the drain electrode 32 are preferably made of metal, in which the gate electrode 28 is preferably made of Schottky metal while the source electrode 30 and the drain electrode 32 are preferably made of ohmic contact metals. According to an embodiment of the present invention, each of the gate electrode 28, source electrode 30, and drain electrode 32 could include gold (Au), Silver (Ag), platinum (Pt), titanium (Ti), aluminum (Al), tungsten (W), palladium (Pd), or combination thereof. Preferably, it would be desirable to conduct an electroplating process, sputtering process, resistance heating evaporation process, electron beam evaporation process, physical vapor deposition (PVD) process, chemical vapor deposition (CVD) process, or combination thereof to form electrode materials in the aforementioned recesses, and then pattern the electrode materials through one or more etching processes to form the gate electrode 28, source electrode 30, and the drain electrode 32. This completes the fabrication of a HEMT according to an embodiment of the present invention.
  • Referring to FIG. 6 , FIG. 6 illustrates a structural view of a HEMT according to an embodiment of the present invention. As shown in FIG. 6 , the HEMT similar to the embodiment disclosed in FIG. 5 also includes a buffer layer 14 disposed on the substrate 12, a first barrier layer 16 disposed on the buffer layer 14, a p-type semiconductor layer 18 disposed on the first barrier layer 16, a gate electrode 28 disposed on the p-type semiconductor layer 18, a hard mask 20 disposed on the p-type semiconductor layer 18, a spacer 22 disposed adjacent to the p-type semiconductor layer 18 and the hard mask 20, a second barrier layer 24 disposed on the first barrier layer 16 adjacent to the spacer 22, and a source electrode 30 and drain electrode 32 disposed on the second barrier layer 24 adjacent to two sides of the spacer 22.
  • In contrast to the hard mask 20 in FIG. 5 made of conductive material, the hard mask 20 in this embodiment could be made of conductive or dielectric material including but not limited to for example TiN, silicon oxide, or silicon nitride. In this approach, it would be desirable to have the gate electrode 28 penetrating the hard mask 20 and contacting the surface of the p-type semiconductor layer 18 directly, or if viewed from another perspective the hard mask 20 is disposed on the p-type semiconductor layer 18 and surrounding the gate electrode 28.
  • Referring to FIGS. 7-12 , FIGS. 7-12 illustrate a method for fabricating a HEMT according to an embodiment of the present invention. As shown in the FIG. 7 , a substrate 42 such as a substrate made from silicon, silicon carbide, or aluminum oxide (or also referred to as sapphire) is provided, in which the substrate 42 could be a single-layered substrate, a multi-layered substrate, gradient substrate, or combination thereof. According to other embodiment of the present invention, the substrate 42 could also include a silicon-on-insulator (SOI) substrate.
  • Next, a buffer layer 44 is formed on the substrate 12. According to an embodiment of the present invention, the buffer layer 44 is preferably made of III-V semiconductors such as gallium nitride (GaN), in which a thickness of the buffer layer 44 could be between 0.5 microns to 10 microns. According to an embodiment of the present invention, the formation of the buffer layer 44 could be accomplished by a molecular-beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, a chemical vapor deposition (CVD) process, a hydride vapor phase epitaxy (HVPE) process, or combination thereof.
  • Next, a first barrier layer 46 is formed on the surface of the buffer layer 44. In this embodiment, the first barrier layer 46 is preferably made of III-V semiconductor such as aluminum gallium nitride (AlxGa1-xN), in which 0<x<1, x being less than or equal to 20%, and the first barrier layer 46 preferably includes an epitaxial layer formed through epitaxial growth process. Similar to the buffer layer 44, the formation of the first barrier layer 46 on the buffer layer 44 could be accomplished by a molecular-beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, a chemical vapor deposition (CVD) process, a hydride vapor phase epitaxy (HVPE) process, or combination thereof.
  • Next, a p-type semiconductor layer 48 is formed on the surface of the first barrier layer 46. In this embodiment, the p-type semiconductor layer 48 is preferably a III-V compound layer including p-type GaN (p-GaN) and the formation of the p-type semiconductor layer 48 on the first barrier layer 46 could be accomplished by a molecular-beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, a chemical vapor deposition (CVD) process, a hydride vapor phase epitaxy (HVPE) process, or combination thereof.
  • Next similar to FIG. 2 , a pattern transfer process is conducted to pattern the p-type semiconductor layer 48 by first using a patterned mask (not shown) as mask to remove part of part of the p-type semiconductor layer 48 for exposing the surface of the first barrier layer 46 adjacent to two sides of the patterned p-type semiconductor layer 48, in which the patterned p-type semiconductor layer 48 preferably becomes a part of the gate structure of the HEMT in the later process. Similar to the aforementioned embodiment of preventing a continuous p-type semiconductor layer 48 from inducing a micro loading effect, the pattern transfer process conducted at this stage preferably removes all of the remaining p-type semiconductor layer 48 adjacent to two sides of the patterned p-type semiconductor layer 48 during the patterning process to expose the surface of the first barrier layer 46 so that the top surface of the first barrier layer 46 adjacent to two sides of the patterned p-type semiconductor layer 48 could be even with or slightly lower than the top surface of the first barrier layer 46 directly under the p-type semiconductor layer 48.
  • Next, as shown in FIG. 8 , a spacer 50 is formed adjacent to the p-type semiconductor layer 48. Specifically, the formation of the spacer 50 could be accomplished by first forming a liner (not shown) made of dielectric material on the substrate 42 to cover the first barrier layer 46 and p-type semiconductor layer 48, and an etching back process is conducted to remove part of the liner for forming a spacer 50 on sidewalls of the p-type semiconductor layer 48. Since no hard mask is formed on top of the p-type semiconductor layer 48, the top surface of the spacer 50 is preferably even with the top surface of the p-type semiconductor layer 48. It should be noted that even though the spacer 50 pertains to be a single spacer in this embodiment, it would also be desirable to adjust the number of the liner being deposited to form one or more spacers including two, three, or even four spacers on sidewalls of the p-type semiconductor layer 48, which each of the spacers 50 could include an I-shape and/or L-shape cross-section and each of the spacers could include silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbon nitride (SiCN), or combination thereof, which are all within the scope of the present invention.
  • Next, as shown in FIG. 9 , a second barrier layer 52 is formed on the surface of the first barrier layer 46 adjacent to two sides of the spacer 50 and the top surface of the p-type semiconductor layer 48. Preferably, the first barrier layer 46 and the second barrier layer 52 are made of III-V semiconductor such as aluminum gallium nitride (AlxGa1-xN) and each of the two layers includes an epitaxial layer formed through epitaxial growth process. In this embodiment, the first barrier layer 46 and the second barrier layer 52 preferably include different thicknesses such as the thickness of the first barrier layer 46 is preferably less than the thickness of the second barrier layer 52.
  • Moreover, the first barrier layer 46 and the second barrier layer 52 preferably include different concentrations of aluminum or more specifically the aluminum concentration of the first barrier layer 46 is less than the aluminum concentration of the second barrier layer 52. For instance, the first barrier layer 46 is made of III-V semiconductor such as aluminum gallium nitride (AlxGa1-xN), in which 0<x<1, x being 5-15% and the second barrier layer 52 is made of III-V semiconductor such as aluminum gallium nitride (AlxGa1-xN), in which 0<x<1, x being 15-50%. Similar to the formation of the first barrier layer 46, the formation of the second barrier layer 52 on the first buffer layer 46 could be accomplished by a molecular-beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, a chemical vapor deposition (CVD) process, a hydride vapor phase epitaxy (HVPE) process, or combination thereof.
  • Next, as shown in FIG. 10 , a hard mask 54 is formed to cover the second barrier layer 52 and the exposed spacer 50 entirely. In this embodiment, the hard mask 54 could include be made of conductive or dielectric material including but not limited to for example silicon oxide, silicon nitride, TiN, or aluminum oxide (AlO).
  • Next, as shown in FIG. 11 , a planarizing process such as chemical mechanical polishing (CMP) process is conducted to remove part of the hard mask 54 and the entire second barrier layer 52 disposed directly on top of the p-type semiconductor layer 48 so that the top surface of the remaining hard mask 54 adjacent to two sides of the spacer 50 is even with the top surface of the p-type semiconductor layer 48.
  • Next, as shown in FIG. 12 , a passivation layer 56 is formed on the surface of the hard mask 54, and a gate electrode 58 is formed in the passivation layer 56 on top of the p-type semiconductor layer 48 and a source electrode 60 and a drain electrode 62 are formed adjacent to two sides of the gate electrode 58, in which the p-type semiconductor layer 48 and the gate electrode 58 could constitute a gate structure 64 altogether. In this embodiment, it would be desirable to conduct a photo-etching process to remove part of the passivation layer 56 directly on top of the p-type semiconductor layer 48 to form a recess (not shown), form a gate electrode 58 in the recess, remove part of the passivation layer 56 and part of the hard mask 54 adjacent to two sides of the spacer 50 to form two recesses, and then form the source electrode 60 and drain electrode 62 in the two recesses adjacent to two sides of the gate electrode 58.
  • In this embodiment, the gate electrode 58, the source electrode 60, and the drain electrode 62 are preferably made of metal, in which the gate electrode 58 is preferably made of Schottky metal while the source electrode 60 and the drain electrode 62 are preferably made of ohmic contact metals. According to an embodiment of the present invention, each of the gate electrode 58, source electrode 60, and drain electrode 62 could include gold (Au), Silver (Ag), platinum (Pt), titanium (Ti), aluminum (Al), tungsten (W), palladium (Pd), or combination thereof. Preferably, it would be desirable to conduct an electroplating process, sputtering process, resistance heating evaporation process, electron beam evaporation process, physical vapor deposition (PVD) process, chemical vapor deposition (CVD) process, or combination thereof to form electrode materials in the aforementioned recesses, and then pattern the electrode materials through one or more etching processes to form the gate electrode 58, source electrode 60, and the drain electrode 62. This completes the fabrication of a HEMT according to an embodiment of the present invention.
  • Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims (12)

What is claimed is:
1. A method for fabricating high electron mobility transistor (HEMT), comprising:
forming a first barrier layer on a substrate;
forming a p-type semiconductor layer on the first barrier layer;
forming a hard mask on the p-type semiconductor layer;
patterning the hard mask and the p-type semiconductor layer; and
forming a spacer adjacent to the hard mask and the p-type semiconductor layer.
2. The method of claim 1, further comprising forming a buffer layer on the substrate before forming the first barrier layer.
3. The method of claim 1, further comprising:
forming a second barrier layer on the first barrier layer adjacent to the spacer;
forming a gate electrode on the hard mask; and
forming a source electrode and a drain electrode adjacent to two sides of the spacer.
4. The method of claim 3, wherein the hard mask comprises a conductive material.
5. The method of claim 1, further comprising:
forming a second barrier layer on the first barrier layer adjacent to the spacer;
forming a gate electrode in the hard mask and on the p-type semiconductor layer; and
forming a source electrode and a drain electrode adjacent to two sides of the spacer.
6. The method of claim 5, wherein the hard mask comprises a dielectric material.
7. The method of claim 1, wherein the first barrier layer comprise AlxGa1-xN.
8. A method for fabricating high electron mobility transistor (HEMT), comprising:
forming a first barrier layer on a substrate;
forming a p-type semiconductor layer on the first barrier layer;
patterning the p-type semiconductor layer; and
forming a spacer adjacent to the p-type semiconductor layer.
9. The method of claim 8, further comprising forming a buffer layer on the substrate before forming the first barrier layer.
10. The method of claim 8, further comprising:
forming a second barrier layer on the p-type semiconductor layer and the first barrier layer adjacent to the spacer;
forming a hard mask on the second barrier layer;
planarizing the hard mask;
forming a gate electrode on the p-type semiconductor layer; and
forming a source electrode and a drain electrode adjacent to two sides of the spacer.
11. The method of claim 10, further comprising planarizing the hard mask and the second barrier layer so that top surfaces of the hard mask and the p-type semiconductor layer are coplanar.
12. The method of claim 8, wherein the first barrier layer comprise AlxGa1-xN.
US18/221,396 2019-12-06 2023-07-13 High electron mobility transistor and method for fabricating the same Pending US20230369448A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US18/221,396 US20230369448A1 (en) 2019-12-06 2023-07-13 High electron mobility transistor and method for fabricating the same

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CN201911241221.7 2019-12-06
CN201911241221.7A CN112928161B (en) 2019-12-06 2019-12-06 High electron mobility transistor and manufacturing method thereof
US16/731,058 US11749740B2 (en) 2019-12-06 2019-12-31 High electron mobility transistor and method for fabricating the same
US18/221,396 US20230369448A1 (en) 2019-12-06 2023-07-13 High electron mobility transistor and method for fabricating the same

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US16/731,058 Division US11749740B2 (en) 2019-12-06 2019-12-31 High electron mobility transistor and method for fabricating the same

Publications (1)

Publication Number Publication Date
US20230369448A1 true US20230369448A1 (en) 2023-11-16

Family

ID=76161530

Family Applications (3)

Application Number Title Priority Date Filing Date
US16/731,058 Active US11749740B2 (en) 2019-12-06 2019-12-31 High electron mobility transistor and method for fabricating the same
US18/221,404 Pending US20230378314A1 (en) 2019-12-06 2023-07-13 High electron mobility transistor and method for fabricating the same
US18/221,396 Pending US20230369448A1 (en) 2019-12-06 2023-07-13 High electron mobility transistor and method for fabricating the same

Family Applications Before (2)

Application Number Title Priority Date Filing Date
US16/731,058 Active US11749740B2 (en) 2019-12-06 2019-12-31 High electron mobility transistor and method for fabricating the same
US18/221,404 Pending US20230378314A1 (en) 2019-12-06 2023-07-13 High electron mobility transistor and method for fabricating the same

Country Status (2)

Country Link
US (3) US11749740B2 (en)
CN (2) CN117855265A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113611736B (en) * 2020-05-29 2022-11-22 联芯集成电路制造(厦门)有限公司 Semiconductor element and manufacturing method thereof
CN117198877A (en) * 2022-05-30 2023-12-08 联华电子股份有限公司 High electron mobility transistor and manufacturing method thereof
TWI842078B (en) * 2022-09-02 2024-05-11 力晶積成電子製造股份有限公司 High electron mobility transistor device and manufacturing method thereof

Family Cites Families (72)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5161235A (en) * 1990-02-20 1992-11-03 University Of Virginia Alumni Patents Foundation Field-effect compound semiconductive transistor with GaAs gate to increase barrier height and reduce turn-on threshold
EP1410444B1 (en) 2001-07-24 2012-08-22 Cree, Inc. Insulating Gate AlGaN/GaN HEMT
JP4041075B2 (en) * 2004-02-27 2008-01-30 株式会社東芝 Semiconductor device
JP2006032552A (en) * 2004-07-14 2006-02-02 Toshiba Corp Nitride-containing semiconductor device
JP4705412B2 (en) * 2005-06-06 2011-06-22 パナソニック株式会社 Field effect transistor and manufacturing method thereof
JP4712459B2 (en) * 2005-07-08 2011-06-29 パナソニック株式会社 Transistor and method of operating the same
JP4705481B2 (en) * 2006-01-25 2011-06-22 パナソニック株式会社 Nitride semiconductor device
JP2007220895A (en) * 2006-02-16 2007-08-30 Matsushita Electric Ind Co Ltd Nitride semiconductor device and manufacturing method thereof
JP5147197B2 (en) * 2006-06-06 2013-02-20 パナソニック株式会社 Transistor
JP5186096B2 (en) * 2006-10-12 2013-04-17 パナソニック株式会社 Nitride semiconductor transistor and manufacturing method thereof
US7838904B2 (en) * 2007-01-31 2010-11-23 Panasonic Corporation Nitride based semiconductor device with concave gate region
WO2008151138A1 (en) * 2007-06-01 2008-12-11 The Regents Of The University Of California P-gan/algan/aln/gan enhancement-mode field effect transistor
US7795642B2 (en) * 2007-09-14 2010-09-14 Transphorm, Inc. III-nitride devices with recessed gates
US7915643B2 (en) * 2007-09-17 2011-03-29 Transphorm Inc. Enhancement mode gallium nitride power devices
JP5032965B2 (en) * 2007-12-10 2012-09-26 パナソニック株式会社 Nitride semiconductor transistor and manufacturing method thereof
US7851825B2 (en) * 2007-12-10 2010-12-14 Transphorm Inc. Insulated gate e-mode transistors
JP2010103478A (en) * 2008-09-25 2010-05-06 Panasonic Corp Nitride semiconductor device and method for manufacturing the same
JP5468768B2 (en) * 2008-12-05 2014-04-09 パナソニック株式会社 Field effect transistor and manufacturing method thereof
KR101666910B1 (en) * 2009-04-08 2016-10-17 이피션트 파워 컨버젼 코퍼레이션 ENHANCEMENT MODE GaN HEMT DEVICE AND METHOD FOR FABRICATING THE SAME
JP5663000B2 (en) * 2009-04-08 2015-02-04 エフィシエント パワー コンヴァーション コーポレーション Reverse diffusion suppression structure
US8823012B2 (en) * 2009-04-08 2014-09-02 Efficient Power Conversion Corporation Enhancement mode GaN HEMT device with gate spacer and method for fabricating the same
WO2010118090A1 (en) * 2009-04-08 2010-10-14 Efficient Power Conversion Corporation Enhancement mode gallium nitride transistor with improved gate characteristics
KR102065115B1 (en) * 2010-11-05 2020-01-13 삼성전자주식회사 High Electron Mobility Transistor having E-mode and method of manufacturing the same
US9214538B2 (en) * 2011-05-16 2015-12-15 Eta Semiconductor Inc. High performance multigate transistor
CN103620751B (en) * 2011-07-12 2017-08-01 松下知识产权经营株式会社 Nitride semiconductor device and manufacturing method thereof
WO2013011617A1 (en) * 2011-07-15 2013-01-24 パナソニック株式会社 Semiconductor device and method for manufacturing same
GB201112330D0 (en) * 2011-07-18 2011-08-31 Epigan Nv Method for growing III-V epitaxial layers and semiconductor structure
JP5896667B2 (en) * 2011-09-26 2016-03-30 トランスフォーム・ジャパン株式会社 Compound semiconductor device and manufacturing method thereof
KR101882997B1 (en) * 2011-09-30 2018-07-30 삼성전기주식회사 Nitride semiconductor device and manufacturing method thereof
US9543391B2 (en) * 2011-10-19 2017-01-10 Samsung Electronics Co., Ltd. High electron mobility transistor having reduced threshold voltage variation and method of manufacturing the same
US8946771B2 (en) * 2011-11-09 2015-02-03 Taiwan Semiconductor Manufacturing Co., Ltd. Gallium nitride semiconductor devices and method making thereof
JP5950643B2 (en) * 2012-03-19 2016-07-13 トランスフォーム・ジャパン株式会社 Compound semiconductor device and manufacturing method thereof
CN102683394B (en) * 2012-04-17 2014-12-10 苏州晶湛半导体有限公司 Enhanced device and manufacturing method thereof
JP2013235873A (en) * 2012-05-02 2013-11-21 Renesas Electronics Corp Semiconductor device and method of manufacturing the same
JP6087552B2 (en) * 2012-09-21 2017-03-01 トランスフォーム・ジャパン株式会社 Compound semiconductor device and manufacturing method thereof
JP6161246B2 (en) * 2012-09-28 2017-07-12 トランスフォーム・ジャパン株式会社 Semiconductor device and manufacturing method of semiconductor device
JP2014072426A (en) * 2012-09-28 2014-04-21 Fujitsu Ltd Semiconductor device and semiconductor device manufacturing method
KR101922121B1 (en) * 2012-10-09 2018-11-26 삼성전자주식회사 High electron mobility transistor and method of manufacturing the same
JP6167889B2 (en) * 2012-12-21 2017-07-26 日亜化学工業株式会社 Field effect transistor and manufacturing method thereof
JP6161910B2 (en) * 2013-01-30 2017-07-12 ルネサスエレクトロニクス株式会社 Semiconductor device
JP6174874B2 (en) * 2013-03-15 2017-08-02 ルネサスエレクトロニクス株式会社 Semiconductor device
TW201513341A (en) * 2013-08-01 2015-04-01 Efficient Power Conversion Corp Gate with self-aligned bumps for enhanced mode gallium nitride transistors
US9076854B2 (en) * 2013-08-26 2015-07-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device
US9847401B2 (en) * 2014-02-20 2017-12-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of forming the same
JP6439789B2 (en) * 2014-02-21 2018-12-19 パナソニック株式会社 Field effect transistor
US9425301B2 (en) * 2014-04-30 2016-08-23 Taiwan Semiconductor Manufacturing Co., Ltd. Sidewall passivation for HEMT devices
CN104269434B (en) * 2014-09-19 2018-01-05 苏州捷芯威半导体有限公司 A kind of HEMT
CN104377241B (en) * 2014-09-30 2017-05-03 苏州捷芯威半导体有限公司 Power semiconductor device and manufacturing method thereof
US9601608B2 (en) * 2014-11-13 2017-03-21 Taiwan Semiconductor Manufacturing Co., Ltd. Structure for a gallium nitride (GaN) high electron mobility transistor
US9917195B2 (en) * 2015-07-29 2018-03-13 International Business Machines Corporation High doped III-V source/drain junctions for field effect transistors
JP6767741B2 (en) * 2015-10-08 2020-10-14 ローム株式会社 Nitride semiconductor device and its manufacturing method
WO2017073047A1 (en) * 2015-10-27 2017-05-04 パナソニックＩｐマネジメント株式会社 Semiconductor device
ITUB20155862A1 (en) * 2015-11-24 2017-05-24 St Microelectronics Srl NORMALLY OFF TYPE TRANSISTOR WITH REDUCED RESISTANCE IN THE STATE ON AND RELATIVE MANUFACTURING METHOD
US10038085B2 (en) * 2016-01-08 2018-07-31 Infineon Technologies Austria Ag High electron mobility transistor with carrier injection mitigation gate structure
WO2017171873A1 (en) * 2016-04-01 2017-10-05 Intel Corporation Dopant diffusion barrier for source/drain to curb dopant atom diffusion
KR102150007B1 (en) * 2016-06-01 2020-09-01 이피션트 파워 컨버젼 코퍼레이션 Passivation structure of multi-stage surface and manufacturing method thereof
TWI648858B (en) * 2016-06-14 2019-01-21 黃知澍 Ga-face III group / nitride epitaxial structure, its active element and manufacturing method thereof
US9741840B1 (en) * 2016-06-14 2017-08-22 Semiconductor Components Industries, Llc Electronic device including a multiple channel HEMT and an insulated gate electrode
DE102017210711A1 (en) * 2016-06-27 2017-12-28 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Semiconductor device
WO2018063489A1 (en) * 2016-09-30 2018-04-05 Hrl Laboratories, Llc Doped gate dielectric materials
US10014402B1 (en) * 2016-12-14 2018-07-03 Taiwan Semiconductor Manufacturing Co., Ltd. High electron mobility transistor (HEMT) device structure
DE112018003057T5 (en) * 2017-06-15 2020-04-09 Efficient Power Conversion Corporation GAN TRANSISTOR IN ENRICHMENT MODE WITH SELECTIVE AND NON-SELECTIVE ETCH LAYERS FOR IMPROVED GAN SPACER THICKNESS
US10553712B2 (en) * 2017-07-12 2020-02-04 Indian Institute Of Technology High-electron-mobility transistor (HEMT)
CN107946358B (en) * 2017-11-21 2025-01-24 华南理工大学 An AlGaN/GaN heterojunction HEMT device compatible with Si-CMOS process and a manufacturing method thereof
US10804384B2 (en) * 2017-12-27 2020-10-13 Rohm Co., Ltd. Semiconductor device and manufacturing method thereof
US11302808B2 (en) * 2017-12-29 2022-04-12 Intel Corporation III-V transistors with resistive gate contacts
CN110034186B (en) * 2018-01-12 2021-03-16 中国科学院苏州纳米技术与纳米仿生研究所 Group III-nitride-enhanced HEMT based on composite barrier structure and its fabrication method
US10985259B2 (en) * 2018-12-07 2021-04-20 Gan Systems Inc. GaN HEMT device structure and method of fabrication
TWI679770B (en) * 2018-12-26 2019-12-11 杰力科技股份有限公司 Gallium nitride hemt and gate structure thereof
US20200251582A1 (en) * 2019-02-04 2020-08-06 Qualcomm Incorporated High electron mobility transistor (hemt) fin field-effect transistor (finfet)
US11476359B2 (en) * 2019-03-18 2022-10-18 Wolfspeed, Inc. Structures for reducing electron concentration and process for reducing electron concentration
CN112531025B (en) * 2019-09-17 2024-01-30 联华电子股份有限公司 High electron mobility transistor

Also Published As

Publication number Publication date
US20210175343A1 (en) 2021-06-10
CN112928161A (en) 2021-06-08
CN112928161B (en) 2024-01-02
CN117855265A (en) 2024-04-09
US11749740B2 (en) 2023-09-05
US20230378314A1 (en) 2023-11-23

Similar Documents

Publication Publication Date Title
US20230369448A1 (en) High electron mobility transistor and method for fabricating the same
US12107157B2 (en) High electron mobility transistor and method for fabricating the same
US20240322008A1 (en) High electron mobility transistor and method for fabricating the same
US20240234539A9 (en) High electron mobility transistor and method for fabricating the same
US20250113523A1 (en) High electron mobility transistor and method for fabricating the same
US20240387720A1 (en) High electron mobility transistor and method for fabricating the same
US20230231022A1 (en) High electron mobility transistor and method for fabricating the same
US12040380B2 (en) High electron mobility transistor and method for fabricating the same
US20240071758A1 (en) High electron mobility transistor and method for fabricating the same
US20230387280A1 (en) High electron mobility transistor and method for fabricating the same
US20240038871A1 (en) High electron mobility transistor and method for fabricating the same
US20240038844A1 (en) High electron mobility transistor and method for fabricating the same

Legal Events

Date Code Title Description
STPP Information on status: patent application and granting procedure in general

Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: FINAL REJECTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

点击 这是indexloc提供的php浏览器服务，不要输入任何密码和下载