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US20180331131A1 - Method for manufacturing thin film transistor, method for manufacturing array substrate, array substrate and display device - Google Patents

Method for manufacturing thin film transistor, method for manufacturing array substrate, array substrate and display device Download PDF

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US20180331131A1
US20180331131A1 US15/328,155 US201615328155A US2018331131A1 US 20180331131 A1 US20180331131 A1 US 20180331131A1 US 201615328155 A US201615328155 A US 201615328155A US 2018331131 A1 US2018331131 A1 US 2018331131A1
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Prior art keywords
intermediate layer
layer
region
photoresist
substrate
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US10297449B2 (en
Inventor
Zijin Lin
Haisheng Zhao
Xiaoguang PEI
Zhilong PENG
Dongjiang SUN
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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Assigned to BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD. reassignment BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LIN, ZIJIN, PEI, XIAOGUANG, PENG, ZHILONG, SUN, Dongjiang, ZHAO, Haisheng
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L27/1288
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0272Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
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    • H01ELECTRIC ELEMENTS
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/0273Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274Photolithographic processes
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/18, H10D48/04 and H10D48/07, with or without impurities, e.g. doping materials
    • H01L21/46Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/469Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers
    • H01L21/47Organic layers, e.g. photoresist
    • H01L27/1262
    • H01L29/66742
    • H01L29/786
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    • H10D30/031Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
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    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
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    • H10D30/00Field-effect transistors [FET]
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    • H10D30/67Thin-film transistors [TFT]
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    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213Channel regions of field-effect devices
    • H10D62/221Channel regions of field-effect devices of FETs
    • H10D62/235Channel regions of field-effect devices of FETs of IGFETs
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    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01Manufacture or treatment
    • H10D86/021Manufacture or treatment of multiple TFTs
    • H10D86/0212Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
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    • H10D86/01Manufacture or treatment
    • H10D86/021Manufacture or treatment of multiple TFTs
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    • H10D86/01Manufacture or treatment
    • H10D86/021Manufacture or treatment of multiple TFTs
    • H10D86/0231Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
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    • H10D86/40Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
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    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • a display device including the array substrate hereinabove.
  • FIG. 4 is a schematic view where an active layer is deposited on the photoresist in some embodiments of the present disclosure
  • Step 9 applying a stripping liquid onto the photoresist 10 to remove the photoresist 10 , as shown in FIG. 5 .

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

A method for manufacturing thin film transistor, a method for manufacturing array substrate, an array substrate and a display device are provided. The method for manufacturing thin film transistor includes forming an intermediate layer on a substrate, patterning the intermediate layer to form an intermediate layer reserved region and an intermediate layer unreserved region, where the intermediate layer unreserved region corresponds to a pattern of a first structure layer, forming, on the substrate with a pattern of the intermediate layer, a material layer from which the first structure layer is formed, and removing the intermediate layer, and forming the pattern of the first structure layer through a portion of the material layer remaining on the substrate.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This application claims a priority to Chinese Patent Application No. 201610073355.2 filed on Feb. 2, 2016, the disclosures of which are incorporated in their entirety by reference herein.
  • TECHNICAL FIELD
  • The present disclosure relates to the field of display technology, and in particular to a method for manufacturing a thin film transistor, a method for manufacturing an array substrate, an array substrate and a display device.
  • BACKGROUND
  • A method for manufacturing an array substrate in the related art includes forming on a base substrate a pattern of a gate metal layer, a pattern of an active layer, a pattern of a source and drain metal layer, a pattern of a passivation layer and a pattern of a transparent conductive layer in order, and each pattern of the above layers is manufactured through such steps as depositing and coating a photoresist, exposing, developing, etching and removing the photoresist and the like.
  • In a manufacturing process, foreign matters such as dust and chippings are inescapably attached onto the film layers due to the environment, device and other abnormal factors. Theses foreign matters may be attached during the depositing process, the photoresist coating process or the dry etching process. When etching the active layer by the dry etching process, an etching gas may not contact the active layer and react with the same due to the foreign matters attached thereon, and then the portions of the active layer attached with the foreign matters may be remained. As a result, light spots may occur, and the yield of the array substrate may be affected adversely.
  • SUMMARY
  • An object of the present disclosure is to provide a method for manufacturing a thin film transistor, a method for manufacturing an array substrate, an array substrate and a display device, so as to avoid the residual film layer and improve the yield of the array substrate.
  • To achieve the above object, the present disclosure provides the following solutions.
  • A method for manufacturing a thin film transistor is provided, including: forming an intermediate layer on a substrate; patterning the intermediate layer to form an intermediate layer reserved region and an intermediate layer unreserved region, where the intermediate layer unreserved region corresponds to a pattern of a first structure layer; forming, on the substrate with a pattern of the intermediate layer, a material layer from which the first structure layer is formed; and removing the intermediate layer, and forming the pattern of the first structure layer through a portion of the material layer remaining on the substrate.
  • Optionally, the intermediate layer reserved region has a surface with a concave-convex structure.
  • Optionally, a height difference between a convex portion and a concave portion of the concave-convex structure is larger than a thickness of the first structure layer.
  • Optionally, a material of the intermediate layer includes a photoresist.
  • Optionally, the first structure layer is an active layer.
  • Optionally, the intermediate layer is a positive photoresist, and the step of forming the intermediate layer reserved region with the concave-convex structure includes: exposing the intermediate layer by a grey tone mask plate including an opaque region, a semi-transparent region and a transparent region; and forming, after a developing process, a first portion of the intermediate layer reserved region corresponding to the opaque region, a second portion of the intermediate layer reserved region corresponding to the semi-transparent region and the intermediate layer unreserved region corresponding to the transparent region. A thickness of the first portion is larger than a thickness of the second portion.
  • Optionally, the intermediate layer is a negative photoresist, and the step of forming the intermediate layer reserved region with the concave-convex structure includes: exposing the intermediate layer by a grey tone mask plate including an opaque region, a semi-transparent region and a transparent region; and forming, after a developing process, a first portion of the intermediate layer reserved region corresponding to the transparent region, a second portion of the intermediate layer reserved region corresponding to the semi-transparent region and the intermediate layer unreserved region corresponding to the opaque region. A thickness of the first portion is larger than a thickness of the second portion.
  • Optionally, the step of removing the intermediate layer includes: applying a stripping liquid onto an exposed portion of the intermediate layer, and removing the intermediate layer from the substrate through a chemical reaction between the stripping liquid and the intermediate layer.
  • Optionally, the step of removing the intermediate layer, and forming the pattern of the first structure layer through a portion of the material layer remaining on the substrate includes: coating a photoresist onto the material layer; exposing the photoresist using a mask plate, and forming, after a developing process, a photoresist reserved region and a photoresist unreserved region, where the photoresist reserved region correspond to the pattern of the first structure layer; removing the material layer corresponding to the photoresist unreserved region by a dry etching process; and applying a stripping liquid onto an exposed portion of the intermediate layer, and removing the intermediate layer from the substrate through a chemical reaction between the stripping liquid and the intermediate layer.
  • Optionally, a material of the intermediate layer includes a photoresist.
  • Optionally, the first structure layer is an active layer.
  • Optionally, the intermediate layer is a positive photoresist, and the step of forming the intermediate layer reserved region with the concave-convex structure includes: exposing the intermediate layer by a grey tone mask plate including an opaque region, a semi-transparent region and a transparent region; and forming, after a developing process, a first portion of the intermediate layer reserved region corresponding to the opaque region, a second portion of the intermediate layer reserved region corresponding to the semi-transparent region and the intermediate layer unreserved region corresponding to the transparent region. A thickness of the first portion is larger than a thickness of the second portion.
  • Optionally, the intermediate layer is a negative photoresist, and the step of forming the intermediate layer reserved region with the concave-convex structure includes: exposing the intermediate layer by a grey tone mask plate including an opaque region, a semi-transparent region and a transparent region; and forming, after a developing, a first portion of the intermediate layer reserved region corresponding to the transparent region, a second portion of the intermediate layer reserved region corresponding to the semi-transparent region and the intermediate layer unreserved region corresponding to the opaque region. A thickness of the first portion is larger than a thickness of the second portion.
  • Optionally, the step of removing the intermediate layer includes: applying a stripping liquid onto an exposed portion of the intermediate layer, and removing the intermediate layer from the substrate through a chemical reaction between the stripping liquid and the intermediate layer.
  • Optionally, a material of the material layer includes a-Si and N+a-Si.
  • Optionally, prior to forming an intermediate layer on a substrate, the method further includes: providing a base substrate; forming a pattern of a gate metal layer on the substrate; and depositing a gate insulating layer onto the base substrate provided with the pattern of the gate metal layer.
  • A method for manufacturing an array substrate is provided, including forming a thin film transistor on a substrate by the method hereinabove.
  • An array substrate is provided, including a thin film transistor formed on a substrate by the method hereinabove.
  • A display device is provided, including the array substrate hereinabove.
  • According to the present disclosure, a pattern of an intermediate layer is formed on a substrate. The pattern of the intermediate layer includes an intermediate layer reserved region and an intermediate layer unreserved region. The intermediate layer unreserved region corresponds to a pattern of an active layer. A material of the active layer is deposited onto the substrate with the pattern of the intermediate layer. Therefore, the pattern of the active layer may be formed after the intermediate layer is removed. According to the present disclosure, the pattern of the active layer is formed by removing the intermediate layer rather than etching the material of the active layer by a dry etching process, therefore the residue of the active layer film may be avoided even though there are foreign matters attached on the material of the active layer, thereby improving the yield of the array substrate.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a schematic view of a base substrate with a pattern of a gate metal layer arranged thereon in some embodiments of the present disclosure;
  • FIG. 2 is a schematic view where a gate insulating layer is formed in some embodiments of the present disclosure;
  • FIG. 3 is a schematic view where a photoresist is formed in some embodiments of the present disclosure;
  • FIG. 4 is a schematic view where an active layer is deposited on the photoresist in some embodiments of the present disclosure;
  • FIG. 5 is a schematic view where a photoresist is removed and a pattern of an active layer is formed in some embodiments of the present disclosure;
  • FIG. 6 is a schematic view where a photoresist is coated on a gate insulating layer in some embodiments of the present disclosure;
  • FIG. 7 is a schematic view where a photoresist is etched in some embodiments of the present disclosure;
  • FIG. 8 is a schematic view where an active layer is deposited on a photoresist in some embodiments of the present disclosure;
  • FIG. 9 is a schematic view where a photoresist is coated on the active layer in some embodiments of the present disclosure;
  • FIG. 10 is a schematic view where a photoresist coated on the active layer is etched in some embodiments of the present disclosure; and
  • FIG. 11 is a schematic view where an active layer is etched in some embodiments of the present disclosure.
  • DRAWING REFERENCES
    • 1: base substrate; 2: gate metal layer; 3: gate insulating layer; 4: active layer; 10: photoresist
    DETAILED DESCRIPTION
  • In order to make the objects, the technical solutions and the advantages of the present disclosure more apparent, the present disclosure will be described hereinafter in details in conjunction with the drawings and embodiments. Obviously, the following embodiments merely relate to a part of, rather than all of, the embodiments of the present disclosure, and based on these embodiments, a person skilled in the art may, without any creative effort, obtain the other embodiments, which also fall within the scope of the present disclosure.
  • Unless otherwise defined, any technical or scientific term used herein shall have the common meaning understood by a person of ordinary skills. Such words as “first” and “second” used in the specification and claims are merely used to differentiate different components rather than to represent any order, number or importance. Similarly, such words as “one” or “one of” are merely used to represent the existence of at least one member, rather than to limit the number thereof. Such words as “connect” or “connected to” may include electrical connection, direct or indirect, rather than to be limited to physical or mechanical connection. Such words as “on”, “under”, “left” and “right” are merely used to represent relative position relationship, and when an absolute position of the object is changed, the relative position relationship will be changed too.
  • In the related art, an a-Si layer and an N+a-Si layer are deposited in order onto an gate insulating layer (which may be made of SiNx) while forming a pattern of an active layer. Then, a photoresist is coated onto the N+a-Si layer. After an exposing process and a developing process, the photoresist above a region of the active layer pattern is remained, and the photoresist above the other regions is removed. Then, the a-Si layer and the N+a-Si layer which are not protected by the photoresist are removed by a dry etching process. At last, the remained photoresist is removed by a liquid reaction, so as to form the pattern of the active layer. In a manufacturing process, foreign matters such as dust and chippings are inescapably attached onto the film layers due to the environment, device and other abnormal factors. Theses foreign matters may be attached during the depositing process, the photoresist coating process or the dry etching process. When etching the active layer by the dry etching process, an etching gas may not contact the active layer and react with the same due to the foreign matters attached thereon, and then the portions of the active layer attached with the foreign matters may be remained. As a result, light spots may occur, and the yield of the array substrate may be affected adversely.
  • A method for manufacturing a thin film transistor, a method for manufacturing array substrate, an array substrate and a display device are provided in some embodiments of the present disclosure, to solve the issues in the related art that the residue of the active layer film results in light spots and adversely affects the yield of the array substrate, so as to avoid the residue of the film layer and improve the yield of the array substrate.
  • A method for manufacturing a thin film transistor is provided in some embodiments of the present disclosure, including: forming an intermediate layer on a substrate; patterning the intermediate layer to form an intermediate layer reserved region and an intermediate layer unreserved region, where the intermediate layer unreserved region corresponds to a pattern of a first structure layer and the intermediate layer reserved region has a surface with a concave-convex structure; forming, on the substrate with a pattern of the intermediate layer, a material layer from which the first structure layer is formed; and removing the intermediate layer, and forming the pattern of the first structure layer through a portion of the material layer remaining on the substrate.
  • According to the embodiments of the present disclosure, a pattern of an intermediate layer is formed on a substrate. The pattern of the intermediate layer includes an intermediate layer reserved region and an intermediate layer unreserved region. The intermediate layer unreserved region corresponds to a pattern of an active layer. A material of the active layer is deposited onto the substrate with the pattern of the intermediate layer. Therefore, the pattern of the active layer may be formed after the intermediate layer is removed. According to the embodiments of the present disclosure, the pattern of the active layer is formed by removing the intermediate layer rather than etching the material of the active layer by a dry etching process, therefore the residue of the active layer film may be avoided even though foreign matters are attached on the material of the active layer, thereby improving the yield of the array substrate.
  • In some embodiments of the present disclosure, the intermediate layer may be made of a photoresist.
  • In some embodiments of the present disclosure, the first structure layer may be but not limited to an active layer. In the case that the first structure layer is an active layer, the residue of the active layer film may be avoided and the yield of the array substrate may be improved effectively.
  • Optionally, the intermediate layer is a positive photoresist, and the step of forming the intermediate layer reserved region with the concave-convex structure includes: exposing the intermediate layer by a grey tone mask plate including an opaque region, a semi-transparent region and a transparent region; and forming, after a developing process, a first portion of the intermediate layer reserved region corresponding to the opaque region, a second portion of the intermediate layer reserved region corresponding to the semi-transparent region and the intermediate layer unreserved region corresponding to the transparent region. Here, a thickness of the first portion is larger than a thickness of the second portion.
  • Optionally, the intermediate layer is a negative photoresist, and the step of forming the intermediate layer reserved region with the concave-convex structure includes: exposing the intermediate layer by a grey tone mask plate including an opaque region, a semi-transparent region and a transparent region; and forming, after a developing process, a first portion of the intermediate layer reserved region corresponding to the transparent region, a second portion of the intermediate layer reserved region corresponding to the semi-transparent region and the intermediate layer unreserved region corresponding to the opaque region. Here, a thickness of the first portion is larger than a thickness of the second portion.
  • Optionally, the step of removing the intermediate layer includes: applying a stripping liquid onto an exposed portion of the intermediate layer, and removing the intermediate layer from the substrate through a chemical reaction between the stripping liquid and the intermediate layer.
  • Optionally, the step of removing the intermediate layer, and forming the pattern of the first structure layer through a portion of the material layer remaining on the substrate, includes: coating a photoresist onto the material layer; exposing the photoresist using a mask plate, and forming, after a developing process, a photoresist reserved region and a photoresist unreserved region, where the photoresist reserved region correspond to the pattern of the first structure layer; removing the material layer corresponding to the photoresist unreserved region by a dry etching process; and applying a stripping liquid onto an exposed portion of the intermediate layer, and removing the intermediate layer from the substrate through a chemical reaction between the stripping liquid and the intermediate layer.
  • Accordingly, even though the residue of the active layer film occurs due to the foreign matters at the photoresist unreserved region, the residue of the active layer film may be guaranteed to be peeled off in the subsequent process of removing the intermediate layer. According to the method hereinabove, it is not required to form an intermediate layer reserved region having a concave-convex surface, thereby simplifying the manufacturing process.
  • In some embodiments of the present disclosure, the material layer may be made of a-Si layer and N+a-Si.
  • A method for manufacturing an array substrate is provided in some embodiments of the present disclosure, including forming a thin film transistor on a substrate by the method hereinabove.
  • According to the embodiments of the present disclosure, a pattern of an intermediate layer is formed on a substrate. The pattern of the intermediate layer includes an intermediate layer reserved region and an intermediate layer unreserved region. The intermediate layer unreserved region corresponds to a pattern of an active layer. A material of the active layer is deposited onto the substrate with the pattern of the intermediate layer. Therefore, the pattern of the active layer may be formed after the intermediate layer is removed. According to the embodiments of the present disclosure, the pattern of the active layer is formed by removing the intermediate layer rather than etching the material of the active layer by a dry etching process, therefore the residue of the active layer film may be avoided even though foreign matters are attached on the material of the active layer, thereby improving the yield of the array substrate.
  • An array substrate is provided in some embodiments, including a thin film transistor formed on a substrate by the method hereinabove. According to the array substrate provided, the residue of the active layer film may not occur and the yield of the array substrate may be improved effectively.
  • A display device is provided in some embodiments, including the array substrate hereinabove. The display device may be any product or component with a display function, such as a liquid crystal television, a liquid crystal display, a digital photo frame, a cell phone and a tablet PC. The display device may include a flexible circuit board, a printed circuit board and a back plate.
  • A method for manufacturing an array substrate is provided in some embodiments of the present disclosure, so as to avoid the light spots due to the residue of the active layer film. The method includes Steps 1-5 in the following.
  • Step 1: providing a base substrate 1 and forming a pattern of a gate metal layer 2 on the base substrate 1, as shown in FIG. 1;
  • Step 2: depositing a gate insulating layer 3 on the resultant base substrate 1 in Step 1, to avoid a short circuiting of the gate metal layer 2, as shown in FIG. 2;
  • Step 3: coating a photoresist 10 on the resultant base substrate 1 in Step 2 and exposing the photoresist 10 by a grey tone mask plate, and forming, after a developing process, a photoresist unreserved region corresponding to a pattern of an active layer and a photoresist reserved region corresponding to the other regions, where the photoresist reserved region includes a first portion 11 and a second portion 12, and the first portion 11 and the second portion 12 have different thicknesses, so as to form a pit-like photoresist reserved region, i.e., the photoresist reserved region has an uneven surface, as shown in FIG. 3;
  • Step 4: depositing an active layer 4 on the resultant base substrate 1 in Step 3, as shown in FIG. 4. The active layer 4 includes an a-Si layer and an N+a-Si layer. There is no photoresist at the photoresist unreserved region, so the deposited active layer 4 may be in direct contact with the gate insulating layer 3. The active layer at the other regions is deposited onto the photoresist 10. The photoresist reserved region has the surface with the concave-convex structure, and a height different between a top and a bottom of the concave-convex structure is larger than a thickness of the active layer 4, so the film of the active layer 4 may be in a disconnected state i.e., loss of continuity, during the depositing of the active layer 4. And then some photoresist covered by the active layer 4 may be exposed, thereby the stripping liquid may by in contact with the photoresist and reacts with the same in the subsequent removing process;
  • Step 5: applying a stripping liquid onto the photoresist 10 to remove the photoresist 10. According to the embodiments of the present disclosure, the active layer 4 is deposited on the photoresist 10, so there is no need to etch the deposited active layer 4 by a dry etching process. After removing the photoresist 10, the active layer 4 at the photoresist reserved region may be removed correspondingly, and then the pattern of the active layer 4 is formed.
  • According to the embodiments of the present disclosure, a layer of photoresist is coated on the gate insulating layer, the photoresist at the region of the active layer pattern is removed, the photoresist at the other regions is formed to have a concave-convex surface, and then the active layer is deposited. Since the photoresist has a concave-convex surface, during the depositing of the active layer, parts of the active layer may be disconnected at interfaces of an upper portion and a lower portion of the photoresist, such that the photoresist under the active layer may be exposed. The photoresist is removed through a chemical reaction between the stripping liquid and the photoresist, and then the active layer deposited on the photoresist is removed, while the active layer deposited on the photoresist unreserved region is not removed, so as to form the pattern of the active layer. According to the embodiments of the present disclosure, the pattern of the active layer is formed by removing the intermediate layer rather than etching the material of the active layer by a dry etching process. Therefore the residue of the active layer film may be avoided even though foreign matters are attached on the material of the active layer, thereby improving the yield of the array substrate.
  • In some embodiments of the present disclosure, a method for manufacturing an array substrate is provided in some embodiments of the present disclosure, so as to avoid the light spots due to the residue of the active layer film. The method includes Steps 1-9 in the following.
  • Step 1: providing a base substrate 1 and forming a pattern of a gate metal layer 2 on the base substrate 1, as shown in FIG. 1;
  • Step 2: depositing a gate insulating layer 3 on the resultant base substrate 1 in Step 1, to avoid a short circuiting of the gate metal layer 2, as shown in FIG. 2;
  • Step 3: coating a photoresist 10 on the resultant base substrate 1 in Step 2, as shown in FIG. 6;
  • Step 4: exposing the photoresist 10, and forming, after a developing process, a photoresist unreserved region corresponding to a pattern of an active layer and a photoresist reserved region corresponding to the other regions, as shown in FIG. 7;
  • Step 5: depositing an active layer 4 on the resultant base substrate 1 in Step 4, as shown in FIG. 8, where the active layer 4 includes an a-Si layer and an N+a-Si layer. There is no photoresist at the photoresist unreserved region, so the active layer 4 deposited at the photoresist unreserved region may be in direct contact with the gate insulating layer 3;
  • Step 6: depositing a photoresist 10 on the resultant base substrate 1 in Step 5, as shown in FIG. 9;
  • Step 7: exposing the photoresist 10, and forming, after a developing process, a photoresist reserved region corresponding to the pattern of the active layer and a photoresist unreserved region corresponding to the other regions, as shown in FIG. 10;
  • Step 8: removing the active layer 4 at the photoresist unreserved region by a dry etching process, to form a pattern of the active layer 4, as shown in FIG. 11;
  • Step 9: applying a stripping liquid onto the photoresist 10 to remove the photoresist 10, as shown in FIG. 5.
  • Accordingly, even though the residue of the active layer film occurs due to the foreign matters at the other region, the residue of the active layer film may be guaranteed to be peeled off in the subsequent process of removing the intermediate layer since the active layer is formed on the photoresist. According to the method hereinabove, it is not required to form an intermediate layer reserved region having a concave-convex surface, thereby simplifying the manufacturing process.
  • The above are merely the preferred embodiments of the present disclosure. A person skilled in the art may make further modifications and improvements without departing from the principle of the present disclosure, and these modifications and improvements shall also fall within the scope of the present disclosure.

Claims (20)

1. A method for manufacturing a thin film transistor, comprising:
forming an intermediate layer on a substrate;
patterning the intermediate layer to form an intermediate layer reserved region and an intermediate layer unreserved region, wherein the intermediate layer unreserved region corresponds to a pattern of a first structure layer;
forming, on the substrate with a pattern of the intermediate layer, a material layer from which the first structure layer is formed; and
removing the intermediate layer, and forming the pattern of the first structure layer through a portion of the material layer remaining on the substrate.
2. The method according to claim 1, wherein the intermediate layer reserved region has a surface with a concave-convex structure.
3. The method according to claim 2, wherein a height difference between a convex portion and a concave portion of the concave-convex structure is larger than a thickness of the first structure layer.
4. The method according to claim 2, wherein a material of the intermediate layer comprises a photoresist.
5. The method according to claim 2, wherein the first structure layer is an active layer.
6. The method according to claim 5, wherein the intermediate layer is a positive photoresist, and the step of forming the intermediate layer reserved region with the concave-convex structure comprises:
exposing the intermediate layer by a grey tone mask plate comprising an opaque region, a semi-transparent region and a transparent region; and
forming, after a developing process, a first portion of the intermediate layer reserved region corresponding to the opaque region, a second portion of the intermediate layer reserved region corresponding to the semi-transparent region and the intermediate layer unreserved region corresponding to the transparent region, wherein a thickness of the first portion is larger than a thickness of the second portion.
7. The method according to claim 5, wherein the intermediate layer is a negative photoresist, and the step of forming the intermediate layer reserved region with the concave-convex structure comprises:
exposing the intermediate layer by a grey tone mask plate comprising an opaque region, a semi-transparent region and a transparent region; and
forming, after a developing process, a first portion of the intermediate layer reserved region corresponding to the transparent region, a second portion of the intermediate layer reserved region corresponding to the semi-transparent region and the intermediate layer unreserved region corresponding to the opaque region, wherein a thickness of the first portion is larger than a thickness of the second portion.
8. The method according to claim 5, wherein the step of removing the intermediate layer comprises:
applying a stripping liquid onto an exposed portion of the intermediate layer, and removing the intermediate layer from the substrate through a chemical reaction between the stripping liquid and the intermediate layer.
9. The method according to claim 1, wherein the step of removing the intermediate layer, and forming the pattern of the first structure layer through a portion of the material layer remaining on the substrate comprises:
coating a photoresist onto the material layer;
exposing the photoresist using a mask plate, and forming, after a developing process, a photoresist reserved region and a photoresist unreserved region, wherein the photoresist reserved region correspond to the pattern of the first structure layer;
removing the material layer corresponding to the photoresist unreserved region by a dry etching process; and
applying a stripping liquid onto an exposed portion of the intermediate layer, and removing the intermediate layer from the substrate through a chemical reaction between the stripping liquid and the intermediate layer.
10. The method according to claim 9, wherein a material of the intermediate layer comprises a photoresist.
11. The method according to claim 9, wherein the first structure layer is an active layer.
12. The method according to claim 11, wherein the intermediate layer is a positive photoresist, and the step of forming the intermediate layer reserved region with the concave-convex structure comprises:
exposing the intermediate layer by a grey tone mask plate comprising an opaque region, a semi-transparent region and a transparent region; and
forming, after a developing process, a first portion of the intermediate layer reserved region corresponding to the opaque region, a second portion of the intermediate layer reserved region corresponding to the semi-transparent region and the intermediate layer unreserved region corresponding to the transparent region, wherein a thickness of the first portion is larger than a thickness of the second portion.
13. The method according to claim 11, wherein the intermediate layer is a negative photoresist, and the step of forming the intermediate layer reserved region with the concave-convex structure comprises:
exposing the intermediate layer by a grey tone mask plate comprising an opaque region, a semi-transparent region and a transparent region; and
forming, after a developing, a first portion of the intermediate layer reserved region corresponding to the transparent region, a second portion of the intermediate layer reserved region corresponding to the semi-transparent region and the intermediate layer unreserved region corresponding to the opaque region, wherein a thickness of the first portion is larger than a thickness of the second portion.
14. The method according to claim 11, wherein the step of removing the intermediate layer comprises:
applying a stripping liquid onto an exposed portion of the intermediate layer, and removing the intermediate layer from the substrate through a chemical reaction between the stripping liquid and the intermediate layer.
15. The method according to claim 1, wherein a material of the material layer comprises a-Si and N+a-Si.
16. The method according to claim 1, wherein prior to forming an intermediate layer on a substrate, the method further comprises:
providing a base substrate;
forming a pattern of a gate metal layer on the substrate; and
depositing a gate insulating layer onto the base substrate provided with the pattern of the gate metal layer.
17. A method for manufacturing an array substrate, comprising forming a thin film transistor on a substrate by the method according to claim 1.
18. An array substrate, comprising a thin film transistor formed on a substrate by the method according to claim 1.
19. A display device, comprising the array substrate according to claim 18.
20. The method according to claim 2, wherein prior to forming an intermediate layer on a substrate, the method further comprises:
providing a base substrate;
forming a pattern of a gate metal layer on the substrate; and
depositing a gate insulating layer onto the base substrate provided with the pattern of the gate metal layer.
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