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US20180114858A1 - Transistor structure - Google Patents

Transistor structure Download PDF

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Publication number
US20180114858A1
US20180114858A1 US15/631,820 US201715631820A US2018114858A1 US 20180114858 A1 US20180114858 A1 US 20180114858A1 US 201715631820 A US201715631820 A US 201715631820A US 2018114858 A1 US2018114858 A1 US 2018114858A1
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Prior art keywords
contact
transistor structure
dielectric layer
doped region
gate
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US9954099B1 (en
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Cheng-Hsun Chung
Shih-Teng HUANG
Tien-SHang Kuo
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United Microelectronics Corp
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United Microelectronics Corp
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Assigned to UNITED MICROELECTRONICS CORP. reassignment UNITED MICROELECTRONICS CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHUNG, CHENG-HSUN, HUANG, SHIH-TENG, KUO, TIEN-SHANG
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    • H01L29/7816—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65—Lateral DMOS [LDMOS] FETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H01L29/36—
    • H01L29/4983—
    • H01L29/512—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0281—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65—Lateral DMOS [LDMOS] FETs
    • H10D30/657—Lateral DMOS [LDMOS] FETs having substrates comprising insulating layers, e.g. SOI-LDMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/60—Impurity distributions or concentrations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/025—Manufacture or treatment forming recessed gates, e.g. by using local oxidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/671—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor having lateral variation in doping or structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/683—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being parallel to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes) consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts

Definitions

  • the invention relates to a semiconductor device, and particularly relates to a transistor structure.
  • the high voltage transistor device (such as lateral diffused metal-oxide semiconductor (LDMOS) etc.) is broadly applied to various integrated circuits (ICs).
  • LDMOS lateral diffused metal-oxide semiconductor
  • the charge and the electric field is easy to concentrate at the sharp edge or the sharp point of the high voltage transistor device, and thus the leakage current is occurred and the electrical performance is reduced.
  • the invention provides a transistor structure, wherein the leakage current of the transistor structure can be inhibited and the transistor structure can have the superior electrical performance.
  • the invention provides a transistor structure including a substrate, a gate, a first dielectric layer, a first contact and a second contact.
  • the gate is disposed on the substrate.
  • the first dielectric layer is disposed on the substrate.
  • the first dielectric layer covers a portion of a top surface of the gate.
  • the first contact is electrically connected to the gate.
  • the second contact is disposed on the first dielectric layer. The second contact is electrically connected with the first contact.
  • a material of the gate is doped polysilicon, for example.
  • the first dielectric layer in the transistor structure, can be a single layer structure or a multi-layer structure.
  • the single layer structure is an oxide layer, for example.
  • the multi-layer structure is an ONO layer, for example.
  • a material of the first contact is tungsten, for example.
  • a distance between a bottom of the second contact and the substrate is 50 nm or more, for example.
  • a material of the second contact is tungsten, for example.
  • the transistor structure can further include a second dielectric layer.
  • the second dielectric layer is disposed between the gate and the substrate.
  • the transistor structure can further include a first doped region and a second doped region.
  • the first doped region and the second doped region are respectively disposed in the substrate at one side and another side of the gate and have a first conductive type.
  • the first doped region in the transistor structure, can be located at one side of the first dielectric layer away from the gate.
  • the transistor structure can further include a third doped region.
  • the third doped region is disposed in the substrate at the another side of the gate and has a second conductive type.
  • the second doped region is located in the third doped region.
  • the transistor structure can further include a fourth doped region.
  • the fourth doped region is disposed in the substrate and has the first conductive type.
  • the first doped region, the second doped region and the third doped region are located in the fourth doped region.
  • the first conductive type is one of an N-type and a P-type
  • the second conductive type is another one of the N-type and the P-type, for example.
  • the transistor structure can further include a third dielectric layer.
  • the third dielectric layer covers the gate and the first dielectric layer.
  • the first contact and the second contact are located in the third dielectric layer.
  • a material of the third dielectric layer is silicon oxide, silicon nitride or a combination thereof, for example.
  • the first contact is electrically connected to the gate
  • the second contact is disposed on the first dielectric layer
  • the second contact is electrically connected with the first contact. Therefore, the second contact can prevent the charge and the electric field from concentrating at the sharp edge or the sharp point of the transistor structure, and thus the leakage current of the transistor structure can be inhibited and the transistor structure can have the superior electrical performance.
  • FIG. 1 is a cross-sectional view illustrating a transistor structure according to an embodiment of the invention.
  • FIG. 2 is a cross-sectional view illustrating a transistor structure according to another embodiment of the invention.
  • FIG. 1 is a cross-sectional view illustrating a transistor structure according to an embodiment of the invention.
  • a transistor structure 100 including a substrate 102 , a gate 104 , a dielectric layer 106 , a contact 108 and a contact 110 .
  • the transistor structure 100 can be a high voltage transistor device.
  • the high voltage transistor device is a lateral diffused metal-oxide semiconductor (LDMOS) device or a double diffused drain metal-oxide semiconductor (DDDMOS) device, for example.
  • LDMOS lateral diffused metal-oxide semiconductor
  • DDDMOS double diffused drain metal-oxide semiconductor
  • the transistor structure 100 is exemplified as the LDMOS device, but the invention is not limited thereto.
  • the substrate 102 is a silicon substrate, for example.
  • the gate 104 is disposed on the substrate 102 .
  • the material of the gate 104 is doped polysilicon, for example.
  • the method for forming the gate 104 is a chemical vapor deposition (CVD) method, for example.
  • the dielectric layer 106 is disposed on the substrate 102 .
  • the dielectric layer 106 covers a portion of a top surface of the gate 104 .
  • the thickness of the dielectric layer 106 is 50 nm to 150 nm, for example.
  • the dielectric layer 106 can be a single layer structure or a multi-layer structure.
  • the single layer structure is an oxide layer, for example.
  • the multi-layer structure is an ONO layer, for example.
  • the dielectric layer 106 is exemplified as the single layer structure, but the invention is not limited thereto.
  • the method for forming the dielectric layer 106 is the CVD method, for example.
  • the contact 108 is electrically connected to the gate 104 .
  • the material of the contact 108 is tungsten, for example.
  • the method for forming the contact 108 is a physical vapor deposition (PVD) method or the CVD method, for example.
  • the contact 110 is disposed on the dielectric layer 106 .
  • the contact 110 is electrically connected with the contact 108 .
  • the contact 110 can prevent the charge and the electric field from concentrating at the sharp edge or the sharp point of the transistor structure 100 .
  • the distance D 1 between a bottom of the contact 110 and the substrate 102 is 50 nm or more, for example.
  • the material of the contact 110 is tungsten, for example.
  • the method for forming the contact 110 is the PVD method or the CVD method, for example.
  • the contact 110 can be electrically connected with the contact 108 by an interconnect 112 .
  • the interconnect 112 includes a contact, a conductive line or a combination thereof.
  • the transistor structure 100 can further include at least one of a dielectric layer 114 , a spacer 116 , a doped region 118 , a doped region 120 , a doped region 122 , a doped region 124 , a contact 126 , a contact 128 and a dielectric layer 130 .
  • the dielectric layer 114 is disposed between the gate 104 and the substrate 102 .
  • the dielectric layer 114 can be used as gate dielectric layer.
  • the material of the dielectric layer 114 is silicon oxide, for example.
  • the method for forming the dielectric layer 114 is the CVD method or a thermal oxidation method, for example.
  • the spacer 116 is disposed on sidewalls of the gate 104 .
  • the material of the spacer 116 is silicon nitride, for example.
  • the method for forming the spacer 116 can include following steps. A spacer material layer covering the gate 104 is formed first, and then an etching-back process is performed on the spacer material layer. Additionally, the dielectric layer 106 can cover the spacer 116 .
  • the doped region 118 and the doped region 120 are respectively disposed in the substrate 102 at one side and another side of the gate 104 and have a first conductive type.
  • One of the doped region 118 and the doped region 120 can be used as a source region, and the other one of the doped region 118 and the doped region 120 can be used as a drain region.
  • the doped region 118 can be located at one side of the dielectric layer 106 away from the gate 104 .
  • the doped region 122 is disposed in the substrate 102 at the another side of the gate 104 and has a second conductive type.
  • the doped region 120 is located in the doped region 122 .
  • the doped region 124 is disposed in the substrate 102 and has the first conductive type.
  • the doped region 118 , the doped region 120 and the doped region 122 are located in the doped region 124 .
  • the method for forming the doped region 118 , the doped region 120 , the doped region 122 and the doped region 124 is an ion implantation method, for example.
  • first conductive type and second conductive type used in this embodiment refer to different conductive types.
  • the first conductive type is one of an N-type and a P-type
  • the second conductive type is another one of the N-type and the P-type, for example.
  • the first conductive type is exemplified as the N-type
  • the second conductive type is exemplified as the P-type, but the invention is not limited thereto.
  • the contact 126 and the contact 128 are electrically connected to the doped region 118 and the doped region 120 respectively.
  • the material of the contact 126 and the contact 128 is tungsten, for example.
  • the method for forming the contact 126 and the contact 128 is the PVD method or the CVD method, for example.
  • the dielectric layer 130 covers the gate 104 and the dielectric layer 106 .
  • the contact 108 , the contact 110 , the contact 126 and the contact 128 are located in the dielectric layer 130 .
  • the dielectric layer 130 can be a single layer structure or a multi-layer structure. In this embodiment, the dielectric layer 130 is exemplified as the single layer structure, but the invention is not limited thereto.
  • the material of the dielectric layer 130 is silicon oxide, silicon nitride or a combination thereof, for example.
  • the method for forming the dielectric layer 130 is the CVD method, for example.
  • the contact 108 is electrically connected to the gate 104
  • the contact 110 is disposed on the dielectric layer 106
  • the contact 110 is electrically connected with the contact 108 . Therefore, the contact 110 can prevent the charge and the electric field from concentrating at the sharp edge or the sharp point of the transistor structure 100 , and thus the leakage current of the transistor structure 100 can be inhibited and the transistor structure 100 can have the superior electrical performance.
  • FIG. 2 is a cross-sectional view illustrating a transistor structure according to another embodiment of the invention.
  • the transistor structure 200 can further include an etch stop layer 132 .
  • the etch stop layer 132 is disposed on the dielectric layer 106 .
  • the contact 110 is disposed on the etch stop layer 132 .
  • the distance D 2 between the bottom of the contact 110 and the substrate 102 is 50 nm or more, for example.
  • the thickness of the etch stop layer 132 is 20 nm to 100 nm, for example.
  • the material of the etch stop layer 132 is polysilicon, for example.
  • the polysilicon can be undoped polysilicon or doped polysilicon.
  • the etch stop layer 132 can be used as a filed plate when the material of the etch stop layer 132 is the polysilicon (for example, doped polysilicon or undoped polysilicon) and the filed plate is capable of further reducing the electric field.
  • the material of the etch stop layer 132 is the polysilicon (for example, doped polysilicon or undoped polysilicon) and the filed plate is capable of further reducing the electric field.
  • Components of the transistor structure 200 of FIG. 2 that are similar to those of the transistor structure 100 of FIG. 1 are assigned with the same reference numerals and detailed description thereof is omitted here.
  • the contact 110 can prevent the charge and the electric field from concentrating at the sharp edge or the sharp point of the transistor structures 100 and 200 , and thus the leakage current of the transistor structures 100 and 200 can be inhibited and the transistor structures 100 and 200 can have the superior electrical performance.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A transistor structure including a gate, a first dielectric layer, a first contact and a second contact is provided. The gate is disposed on a substrate. The first dielectric layer is disposed on the substrate. The first dielectric layer covers a portion of a top surface of the gate. The first contact is electrically connected to the gate. The second contact is disposed on the first dielectric layer. The second contact is electrically connected with the first contact.

Description

    CROSS REFERENCE TO RELATED APPLICATION
  • This application is a continuation application of and claims the priority benefit of U.S. application Ser. No. 15/299,268, filed on Oct. 20, 2016. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of specification.
    • BACKGROUND OF THE INVENTION Field of the Invention
  • The invention relates to a semiconductor device, and particularly relates to a transistor structure.
    • Description of Related Art
  • The high voltage transistor device (such as lateral diffused metal-oxide semiconductor (LDMOS) etc.) is broadly applied to various integrated circuits (ICs). However, the charge and the electric field is easy to concentrate at the sharp edge or the sharp point of the high voltage transistor device, and thus the leakage current is occurred and the electrical performance is reduced.
    • SUMMARY OF THE INVENTION
  • The invention provides a transistor structure, wherein the leakage current of the transistor structure can be inhibited and the transistor structure can have the superior electrical performance.
  • The invention provides a transistor structure including a substrate, a gate, a first dielectric layer, a first contact and a second contact. The gate is disposed on the substrate. The first dielectric layer is disposed on the substrate. The first dielectric layer covers a portion of a top surface of the gate. The first contact is electrically connected to the gate. The second contact is disposed on the first dielectric layer. The second contact is electrically connected with the first contact.
  • According to an embodiment of the invention, in the transistor structure, a material of the gate is doped polysilicon, for example.
  • According to an embodiment of the invention, in the transistor structure, the first dielectric layer can be a single layer structure or a multi-layer structure.
  • According to an embodiment of the invention, in the transistor structure, the single layer structure is an oxide layer, for example.
  • According to an embodiment of the invention, in the transistor structure, the multi-layer structure is an ONO layer, for example.
  • According to an embodiment of the invention, in the transistor structure, a material of the first contact is tungsten, for example.
  • According to an embodiment of the invention, in the transistor structure, a distance between a bottom of the second contact and the substrate is 50 nm or more, for example.
  • According to an embodiment of the invention, in the transistor structure, a material of the second contact is tungsten, for example.
  • According to an embodiment of the invention, the transistor structure can further include a second dielectric layer. The second dielectric layer is disposed between the gate and the substrate.
  • According to an embodiment of the invention, the transistor structure can further include a first doped region and a second doped region. The first doped region and the second doped region are respectively disposed in the substrate at one side and another side of the gate and have a first conductive type.
  • According to an embodiment of the invention, in the transistor structure, the first doped region can be located at one side of the first dielectric layer away from the gate.
  • According to an embodiment of the invention, the transistor structure can further include a third doped region. The third doped region is disposed in the substrate at the another side of the gate and has a second conductive type. The second doped region is located in the third doped region.
  • According to an embodiment of the invention, the transistor structure can further include a fourth doped region. The fourth doped region is disposed in the substrate and has the first conductive type. The first doped region, the second doped region and the third doped region are located in the fourth doped region.
  • According to an embodiment of the invention, in the transistor structure, the first conductive type is one of an N-type and a P-type, and the second conductive type is another one of the N-type and the P-type, for example.
  • According to an embodiment of the invention, the transistor structure can further include a third dielectric layer. The third dielectric layer covers the gate and the first dielectric layer. The first contact and the second contact are located in the third dielectric layer.
  • According to an embodiment of the invention, in the transistor structure, a material of the third dielectric layer is silicon oxide, silicon nitride or a combination thereof, for example.
  • Based on the above description, in the transistor structure, the first contact is electrically connected to the gate, the second contact is disposed on the first dielectric layer, and the second contact is electrically connected with the first contact. Therefore, the second contact can prevent the charge and the electric field from concentrating at the sharp edge or the sharp point of the transistor structure, and thus the leakage current of the transistor structure can be inhibited and the transistor structure can have the superior electrical performance.
  • In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, a preferred embodiment accompanied with figures is described in detail below.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
  • FIG. 1 is a cross-sectional view illustrating a transistor structure according to an embodiment of the invention.
  • FIG. 2 is a cross-sectional view illustrating a transistor structure according to another embodiment of the invention.
    •  DESCRIPTION OF THE EMBODIMENTS
  • FIG. 1 is a cross-sectional view illustrating a transistor structure according to an embodiment of the invention.
  • Referring to FIG. 1, a transistor structure 100 including a substrate 102, a gate 104, a dielectric layer 106, a contact 108 and a contact 110. The transistor structure 100 can be a high voltage transistor device. The high voltage transistor device is a lateral diffused metal-oxide semiconductor (LDMOS) device or a double diffused drain metal-oxide semiconductor (DDDMOS) device, for example. In this embodiment, the transistor structure 100 is exemplified as the LDMOS device, but the invention is not limited thereto.
  • The substrate 102 is a silicon substrate, for example. The gate 104 is disposed on the substrate 102. The material of the gate 104 is doped polysilicon, for example. The method for forming the gate 104 is a chemical vapor deposition (CVD) method, for example.
  • The dielectric layer 106 is disposed on the substrate 102. The dielectric layer 106 covers a portion of a top surface of the gate 104. The thickness of the dielectric layer 106 is 50 nm to 150 nm, for example. The dielectric layer 106 can be a single layer structure or a multi-layer structure. The single layer structure is an oxide layer, for example. The multi-layer structure is an ONO layer, for example. In this embodiment, the dielectric layer 106 is exemplified as the single layer structure, but the invention is not limited thereto. The method for forming the dielectric layer 106 is the CVD method, for example.
  • The contact 108 is electrically connected to the gate 104. The material of the contact 108 is tungsten, for example. The method for forming the contact 108 is a physical vapor deposition (PVD) method or the CVD method, for example.
  • The contact 110 is disposed on the dielectric layer 106. The contact 110 is electrically connected with the contact 108. The contact 110 can prevent the charge and the electric field from concentrating at the sharp edge or the sharp point of the transistor structure 100. The distance D1 between a bottom of the contact 110 and the substrate 102 is 50 nm or more, for example. The material of the contact 110 is tungsten, for example. The method for forming the contact 110 is the PVD method or the CVD method, for example. The contact 110 can be electrically connected with the contact 108 by an interconnect 112. The interconnect 112 includes a contact, a conductive line or a combination thereof.
  • Furthermore, the transistor structure 100 can further include at least one of a dielectric layer 114, a spacer 116, a doped region 118, a doped region 120, a doped region 122, a doped region 124, a contact 126, a contact 128 and a dielectric layer 130.
  • The dielectric layer 114 is disposed between the gate 104 and the substrate 102. The dielectric layer 114 can be used as gate dielectric layer. The material of the dielectric layer 114 is silicon oxide, for example. The method for forming the dielectric layer 114 is the CVD method or a thermal oxidation method, for example.
  • The spacer 116 is disposed on sidewalls of the gate 104. The material of the spacer 116 is silicon nitride, for example. The method for forming the spacer 116 can include following steps. A spacer material layer covering the gate 104 is formed first, and then an etching-back process is performed on the spacer material layer. Additionally, the dielectric layer 106 can cover the spacer 116.
  • The doped region 118 and the doped region 120 are respectively disposed in the substrate 102 at one side and another side of the gate 104 and have a first conductive type. One of the doped region 118 and the doped region 120 can be used as a source region, and the other one of the doped region 118 and the doped region 120 can be used as a drain region. The doped region 118 can be located at one side of the dielectric layer 106 away from the gate 104. The doped region 122 is disposed in the substrate 102 at the another side of the gate 104 and has a second conductive type. The doped region 120 is located in the doped region 122. The doped region 124 is disposed in the substrate 102 and has the first conductive type. The doped region 118, the doped region 120 and the doped region 122 are located in the doped region 124. The method for forming the doped region 118, the doped region 120, the doped region 122 and the doped region 124 is an ion implantation method, for example.
  • Moreover, the terms “first conductive type” and “second conductive type” used in this embodiment refer to different conductive types. The first conductive type is one of an N-type and a P-type, and the second conductive type is another one of the N-type and the P-type, for example. In this embodiment, the first conductive type is exemplified as the N-type, and the second conductive type is exemplified as the P-type, but the invention is not limited thereto.
  • The contact 126 and the contact 128 are electrically connected to the doped region 118 and the doped region 120 respectively. The material of the contact 126 and the contact 128 is tungsten, for example. The method for forming the contact 126 and the contact 128 is the PVD method or the CVD method, for example.
  • The dielectric layer 130 covers the gate 104 and the dielectric layer 106. The contact 108, the contact 110, the contact 126 and the contact 128 are located in the dielectric layer 130. The dielectric layer 130 can be a single layer structure or a multi-layer structure. In this embodiment, the dielectric layer 130 is exemplified as the single layer structure, but the invention is not limited thereto. The material of the dielectric layer 130 is silicon oxide, silicon nitride or a combination thereof, for example. The method for forming the dielectric layer 130 is the CVD method, for example.
  • Based on the aforementioned embodiment, in the transistor structure 100, the contact 108 is electrically connected to the gate 104, the contact 110 is disposed on the dielectric layer 106, and the contact 110 is electrically connected with the contact 108. Therefore, the contact 110 can prevent the charge and the electric field from concentrating at the sharp edge or the sharp point of the transistor structure 100, and thus the leakage current of the transistor structure 100 can be inhibited and the transistor structure 100 can have the superior electrical performance.
  • FIG. 2 is a cross-sectional view illustrating a transistor structure according to another embodiment of the invention.
  • Referring to FIG. 1 and FIG. 2, a difference between the embodiments of FIG. 1 and FIG. 2 is described as follows. The transistor structure 200 can further include an etch stop layer 132. The etch stop layer 132 is disposed on the dielectric layer 106. The contact 110 is disposed on the etch stop layer 132. The distance D2 between the bottom of the contact 110 and the substrate 102 is 50 nm or more, for example. The thickness of the etch stop layer 132 is 20 nm to 100 nm, for example. The material of the etch stop layer 132 is polysilicon, for example. The polysilicon can be undoped polysilicon or doped polysilicon. The etch stop layer 132 can be used as a filed plate when the material of the etch stop layer 132 is the polysilicon (for example, doped polysilicon or undoped polysilicon) and the filed plate is capable of further reducing the electric field. Components of the transistor structure 200 of FIG. 2 that are similar to those of the transistor structure 100 of FIG. 1 are assigned with the same reference numerals and detailed description thereof is omitted here.
  • In summary, in the transistor structures 100 and 200 of the aforementioned embodiments, the contact 110 can prevent the charge and the electric field from concentrating at the sharp edge or the sharp point of the transistor structures 100 and 200, and thus the leakage current of the transistor structures 100 and 200 can be inhibited and the transistor structures 100 and 200 can have the superior electrical performance.
  • Although the invention has been described with reference to the above embodiments, it will be apparent to one of ordinary skill in the art that modifications to the described embodiments may be made without departing from the spirit of the invention. Accordingly, the scope of the invention is defined by the attached claims not by the above detailed descriptions.

Claims (16)

What is claimed is:
1. A transistor structure comprising:
a gate disposed on a substrate;
a first dielectric layer disposed on the substrate, wherein the first dielectric layer covers a portion of a top surface of the gate;
a first contact electrically connected to the gate; and
a second contact disposed on the first dielectric layer, wherein the second contact is electrically connected with the first contact.
2. The transistor structure of claim 1, wherein a material of the gate comprises doped polysilicon.
3. The transistor structure of claim 1, wherein the first dielectric layer comprises a single layer structure or a multi-layer structure.
4. The transistor structure of claim 3, wherein the single layer structure comprises an oxide layer.
5. The transistor structure of claim 3, wherein the multi-layer structure comprises an ONO layer.
6. The transistor structure of claim 1, wherein a material of the first contact comprises tungsten.
7. The transistor structure of claim 1, wherein a distance between a bottom of the second contact and the substrate is 50 nm or more.
8. The transistor structure of claim 1, wherein a material of the second contact comprises tungsten.
9. The transistor structure of claim 1, further comprising a second dielectric layer disposed between the gate and the substrate.
10. The transistor structure of claim 1, further comprising a first doped region and a second doped region respectively disposed in the substrate at one side and another side of the gate and having a first conductive type.
11. The transistor structure of claim 10, wherein the first doped region is located at one side of the first dielectric layer away from the gate.
12. The transistor structure of claim 10, further comprising a third doped region disposed in the substrate at the another side of the gate and having a second conductive type, wherein the second doped region is located in the third doped region.
13. The transistor structure of claim 12, further comprising a fourth doped region disposed in the substrate and having the first conductive type, wherein the first doped region, the second doped region and the third doped region are located in the fourth doped region.
14. The transistor structure of claim 13, wherein the first conductive type is one of an N-type and a P-type, and the second conductive type is another one of the N-type and the P-type.
15. The transistor structure of claim 1, further comprising a third dielectric layer covering the gate and the first dielectric layer, wherein the first contact and the second contact are located in the third dielectric layer.
16. The transistor structure of claim 15, wherein a material of the third dielectric layer comprises silicon oxide, silicon nitride or a combination thereof.
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US11444194B2 (en) * 2020-11-04 2022-09-13 Taiwan Semiconductor Manufacturing Co., Ltd. LDMOS with enhanced safe operating area and method of manufacture

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US9741826B1 (en) * 2016-10-20 2017-08-22 United Microelectronics Corp. Transistor structure
KR20190087786A (en) * 2018-01-17 2019-07-25 주식회사 디비하이텍 Semiconductor device and method of manufacturing the same
CN114944425A (en) * 2022-07-22 2022-08-26 合肥新晶集成电路有限公司 Power device and manufacturing method thereof

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US8878275B2 (en) 2013-02-18 2014-11-04 Fairchild Semiconductor Corporation LDMOS device with double-sloped field plate
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11444194B2 (en) * 2020-11-04 2022-09-13 Taiwan Semiconductor Manufacturing Co., Ltd. LDMOS with enhanced safe operating area and method of manufacture
US11764297B2 (en) 2020-11-04 2023-09-19 Taiwan Semiconductor Manufacturing Co., Ltd LDMOS with enhanced safe operating area and method of manufacture
US12237413B2 (en) 2020-11-04 2025-02-25 Taiwan Semiconductor Manufacturing Co., Ltd. LDMOS with enhanced safe operating area and method of manufacture

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