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US20180047662A1 - Interposer substrate and method of manufacturing the same - Google Patents

Interposer substrate and method of manufacturing the same Download PDF

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Publication number
US20180047662A1
US20180047662A1 US15/796,713 US201715796713A US2018047662A1 US 20180047662 A1 US20180047662 A1 US 20180047662A1 US 201715796713 A US201715796713 A US 201715796713A US 2018047662 A1 US2018047662 A1 US 2018047662A1
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US
United States
Prior art keywords
insulating layer
carrier
wiring layer
conductive pillars
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US15/796,713
Inventor
Che-Wei Hsu
Shih-Ping Hsu
Chih-Wen Liu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Phoenix Pioneer Technology Co Ltd
Original Assignee
Phoenix Pioneer Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Phoenix Pioneer Technology Co Ltd filed Critical Phoenix Pioneer Technology Co Ltd
Priority to US15/796,713 priority Critical patent/US20180047662A1/en
Publication of US20180047662A1 publication Critical patent/US20180047662A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/145—Organic substrates, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09563—Metal filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10378—Interposers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0147—Carriers and holders
    • H05K2203/0152—Temporary metallic carrier, e.g. for transferring material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs

Definitions

  • the present invention relates to interposer substrates, and, more particularly, to an interposer substrate used in stacked packages and a method of manufacturing the interposer substrate.
  • PoP Package on Package
  • SiP System in Package
  • an interposer substrate is disposed between the memory package and logic package, such that the logic package having logic chips with higher distance therebetween is coupled to the bottom surface of the interposer substrate while the memory package having memory chips with smaller distance therebetween is coupled to the top surface of the interposer substrate.
  • FIGS. 1A-1F are cross-sectional views showing a process of manufacturing a conventional interposer substrate 1 , 1 ′.
  • a carrier 10 having a metal material formed on two sides thereof is provided.
  • a plurality of electrical connecting pads 11 are formed on the carrier 10 through the pattering process.
  • a plurality of first conductive pillars 12 are electro-platted on the electrical connection pads 11 through the patterning process.
  • a first insulating layer 13 is formed on the carrier 10 for encapsulating the first conductive pillars 12 and the electrical connection pads 11 , and a terminal surface of the first conductive pillars 12 is flush with the surface of the first insulating layer 13 .
  • a wiring layer 14 is formed on the first insulating layer 13 and the first conductive pillars 12 , a plurality of second conductive pillars 15 are formed on the wiring layer 14 , and a second insulating layer 16 is then formed on the first insulating layer 13 for encapsulating the second conductive pillars 15 and the circuit layer 14 .
  • a portion of the surface of second conductive pillars 15 is exposed, for the solder ball pads to be formed thereon.
  • the entire carrier 10 is removed, allowing the electrical connection pads 11 to be exposed from the surface of the first insulating layer 13 .
  • a portion of the carrier 10 is etched away through patterning, allowing a remaining potion of the carrier to act as a supporting structure 10 ′.
  • a second insulating layer 16 acts as a solder mask layer, and it is required to have second conductive pillars 15 for the solder ball pads to be disposed thereon. As a result, the overall manufacturing steps and overall cost are undesirably increased.
  • the present invention provides an interposer substrate, comprising: a first insulating layer having a first surface and a second surface opposing the first surface; a first wiring layer formed on the first surface of the first insulating layer; a plurality of conductive pillars formed in the first insulating layer and on the first wiring layer, and connected to the second surface of the first insulating layer; a second wiring layer formed on the second surface of the first insulating layer and electrically connected with the conductive pillars; a second insulating layer formed on the second surface of the first insulating layer and the second wiring layer, wherein a portion of a surface of the second wiring layer is exposed from the second insulating layer.
  • the present invention further provides a method of manufacturing an interposer substrate, comprising: providing a carrier having a first wiring layer and a plurality of conductive pillars disposed on the first wiring layer; forming on the carrier a first insulating layer that has a first surface and a second surface opposing the first surface and is coupled to the carrier via the first surface thereof, with the conductive pillars being exposed from the second surface of the first insulating layer; forming on the second surface of the first insulating layer and the conductive pillars a second wiring layer that is electrically connected with the conductive pillars; forming on the second surface of the first insulating layer and the second wiring layer a second insulating layer, from which a portion of a surface of the second wiring is exposed; and removing the carrier to allow the first wiring layer to be exposed from the first surface of the first insulating layer.
  • the first insulating layer is formed on the carrier through a molding, coating, or lamination method, and the first insulating layer is made of a molding compound, a primer material, or a dielectric material.
  • the surface of the first wiring layer is lower than the first surface of the first insulating layer.
  • the terminal surface of each of the conductive pillars is flush with the second surface of the first insulating layer.
  • the second wiring layer acts as a plurality of solder ball pads.
  • the surface of the second wiring layer is flush with the surface of the second insulating layer.
  • the second insulating layer is formed by a molding, coating or lamination method
  • the first insulating layer is made of a molding compound, a primer, or a dielectric materials.
  • a portion of the carrier is retained and acts as the supporting structure for the first surface of the first insulating layer.
  • the second wiring layer is formed with solder ball pads therein, without the need of conventional conductive pillars.
  • the steps of the manufacturing process can be reduced, as well as the cost.
  • FIGS. 1A-1F are cross-sectional views showing a method of manufacturing a conventional interposer substrate, wherein FIG. 1F ′ is another embodiment of FIG. 1F ;
  • FIGS. 2A-2F are cross-sectional views showing a method of manufacturing an interposer substrate according to the present invention, wherein FIG. 2F ′ is another embodiment of FIG. 2F .
  • FIGS. 2A-2F are cross-sectional views showing a method of manufacturing an interposer substrate (coreless) according to the present invention.
  • the interposer substrate 2 is a carrier used in a flip-chip chip scale package (FCCSP).
  • FCCSP flip-chip chip scale package
  • a carrier 20 is provided.
  • the carrier 20 is a substrate such as a copper foil substrate, but the present invention is not limited thereto.
  • An embodiment uses the copper foil substrate having a metal material 20 a on the two sides thereof as an example.
  • a first wiring layer 21 is formed on the carrier 20 through a patterning process.
  • the first wiring layer 21 comprises a plurality of electrical connecting pads 210 and a plurality of conductive traces 211 .
  • a plurality of conductive pillars 22 are electro-patterned on electrical connection pads 210 of the first wiring layer 21 through a patterning process.
  • the conductive pillars 22 are in contact and electrically connected with the electrical connection pads 210 of the first wiring layer 21 .
  • a first insulating layer 23 is formed on the carrier 20 , the first insulating layer 23 has a first surface 23 a and second surface 23 b opposing the first surface 23 a , the first insulating layer 23 is coupled to the carrier 20 via the first surface 23 a of the insulating layer 23 , and the conductive pillars 22 are exposed from the second surface 23 b of the first insulating layer 23 .
  • the first insulating layer 23 is formed on the carrier 20 by a molding, coating or lamination method, and the first insulating layer 23 is made of a molding compound, a primer, or a dielectric material such as epoxy.
  • the terminal surface 22 a of each of the conductive pillars 22 is flush with second surface 23 b of the first insulating layer 23 .
  • a second wiring layer 24 is formed on the second surface 23 b of the first insulating layer 23 and the conductive pillars 22 , and a second insulating layer 26 is formed on the second surface 23 b of the first insulating layer 23 for encapsulating the second wiring layer 24 .
  • the second wiring layer 24 is a plurality of solder ball pads for coupling with the solder balls (not shown), and a portion of the surface of the second wiring layer 24 is exposed from the second insulating layer 26 .
  • the surface 24 a of the second wiring layer 24 is flush with or lower than the surface 26 a of the second insulating layer 26 .
  • the second insulating layer 26 is formed by a molding, coating or lamination method, and the second insulating layer 26 is made of a molding compound, epoxy, or a dielectric material.
  • the entire carrier 20 is removed, allowing the surface 21 a of the first wiring layer 21 to be exposed from the first surface 23 a of the first insulating layer 23 , and the surface 21 a of the first wiring layer 21 is lower than the first surface 23 a of the first insulating layer 23 .
  • the metal material 20 a is removed by etching.
  • the upper surface 21 a of the first wiring layer 21 is slightly etched away, allowing the upper surface 21 a of the first wiring layer 21 to be recessed on the first surface 23 a of the first insulating layer 23 .
  • a portion of the carrier 20 is etched away, allowing the remaining carrier to act as a supporting structure 20 ′, and the surface 21 a of the first wiring layer 21 is exposed from the first surface 23 a of the first insulating layer 23 .
  • the second wiring layer 24 having solder ball pads can be directly formed after forming a plurality of conductive pillars 22 , so as to reduce the manufacturing process and cost.
  • the present invention further provides an interposer substrate 2 , 2 ′: having a first insulating layer 23 , a first wiring layer 21 , a plurality of conductive pillars 22 , a second wiring layer 24 , and a second insulating layer 26 .
  • the first insulating layer 23 has a first surface 23 a and a second surface 23 b opposing the first surface 23 a , and the first insulating layer 23 is made of a molding compound, epoxy, or a dielectric material.
  • the first wiring layer 21 is embedded in the first surface 23 a of the first insulating layer 23 , and the surface 21 a of the first wiring layer 21 is lower than the first surface 23 a of the first insulating layer 23 .
  • the conductive pillars 22 are formed in the first insulating layer 23 and coupled to the second surface 23 b of the first insulating layer 23 , and the terminal surface 22 a of each of the conductive pillars 22 is flush with the second surface 23 b of the first insulating layer 23 .
  • the second wiring layer 24 is formed on the second surface 23 b of the first insulating layer 23 and the conductive pillars 22 and electrically connected with the conductive pillars 22 , and is formed by a plurality of solder balls.
  • the second insulating layer 26 is formed on the second surface 23 b of the first insulating layer 23 and the second wiring layer 24 , allowing a portion of the surface of the second wiring layer 24 to be exposed from the second insulating layer 26 .
  • the surface 24 a of the second wiring layer 24 may be flush with or lower than the surface 26 a of the second insulating layer 26 .
  • the interposer substrate 2 ′ further comprises a supporting structure 20 ′ formed on the first surface 23 a of the first insulating layer 23 .
  • the interposer substrate and the method of manufacturing the same according to the present invention are applied in products having a stacked structure with fine pitch and high pin number, such as a smart phone, tablet, internet, and laptop.
  • the interposer substrate according to the present invention is highly desirable to be used in products that require high speed operation, low profile, high functionality, and high storage.
  • the interposer substrate 2 , 2 ′ according to the present invention can be coupled to a logic package or memory package via the first wiring layer 21 .

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

A method of manufacturing an interposer substrate, including providing a carrier having a first circuit layer formed thereon, forming a plurality of conductive pillars on the first circuit layer, forming a first insulating layer on the carrier, with the conductive pillars being exposed from the first insulating layer, forming, on the conductive pillars a second circuit layer that is electrically connected to the conductive pillars, forming a second insulating layer on the second surface of the first insulating layer and the second circuit layer, exposing a portion of a surface of the second circuit layer from the second insulating layer, and removing the carrier. The invention further provides the interposer substrate as described above.

Description

    BACKGROUND OF THE INVENTION 1. Field of the Invention
  • The present invention relates to interposer substrates, and, more particularly, to an interposer substrate used in stacked packages and a method of manufacturing the interposer substrate.
    • 2. Description of Related Art
  • As the semiconductor packaging technology continues to advance, various types of packages of the semiconductor device have been developed, in order to increase electrical functionality and reduce packaging space. For instance, a Package on Package (PoP) is developed having multiple packaging structures stacked on one another. This type of package has the property of heterogeneous integration of a System in Package (SiP), and is capable of incorporating and integrating various electronic components of different functions, such as memory, central processing unit, graphic processor, image processor, etc., in a package through stacking, thereby is very suitable to be used in various low-profile electronic products.
  • Early stacked packages are formed by stacking memory packages (memory IC) over the logic packages (logic IC) via a plurality of solder balls. As the demand for light-weight and low profile electronic products, the density of wiring on the memory package increases. The memory package is measured in nanometers; the distance between the contact points are further shortened. However, the distances between the logic packages are measured in micrometers, and cannot be miniaturized further to comply with the distances between the memory packages. As a result, even a memory package with high density wiring is provided, there is no suitable logic package to go in concert with the memory package, thereby unable to achieve efficient production of the electronic products.
  • Accordingly, in order to overcome the above mentioned drawbacks, an interposer substrate is disposed between the memory package and logic package, such that the logic package having logic chips with higher distance therebetween is coupled to the bottom surface of the interposer substrate while the memory package having memory chips with smaller distance therebetween is coupled to the top surface of the interposer substrate.
  • FIGS. 1A-1F are cross-sectional views showing a process of manufacturing a conventional interposer substrate 1, 1′.
  • As shown in FIG. 1A, a carrier 10 having a metal material formed on two sides thereof is provided.
  • As shown in FIG. 1B, a plurality of electrical connecting pads 11 are formed on the carrier 10 through the pattering process.
  • As shown in FIG. 1C, a plurality of first conductive pillars 12 are electro-platted on the electrical connection pads 11 through the patterning process.
  • As shown in FIG. 1D, a first insulating layer 13 is formed on the carrier 10 for encapsulating the first conductive pillars 12 and the electrical connection pads 11, and a terminal surface of the first conductive pillars 12 is flush with the surface of the first insulating layer 13.
  • As shown in FIG. 1E, a wiring layer 14 is formed on the first insulating layer 13 and the first conductive pillars 12, a plurality of second conductive pillars 15 are formed on the wiring layer 14, and a second insulating layer 16 is then formed on the first insulating layer 13 for encapsulating the second conductive pillars 15 and the circuit layer 14. A portion of the surface of second conductive pillars 15 is exposed, for the solder ball pads to be formed thereon.
  • As shown in FIG. 1F, the entire carrier 10 is removed, allowing the electrical connection pads 11 to be exposed from the surface of the first insulating layer 13. Alternatively, as shown in FIG. 1F′, a portion of the carrier 10 is etched away through patterning, allowing a remaining potion of the carrier to act as a supporting structure 10′.
  • However, in the method of manufacturing a conventional interposer substrate 1, a second insulating layer 16 acts as a solder mask layer, and it is required to have second conductive pillars 15 for the solder ball pads to be disposed thereon. As a result, the overall manufacturing steps and overall cost are undesirably increased.
  • Hence, there is an urgent need to solve the foregoing problems encountered in the prior art.
    • SUMMARY OF THE INVENTION
  • In view of the foregoing problems, the present invention provides an interposer substrate, comprising: a first insulating layer having a first surface and a second surface opposing the first surface; a first wiring layer formed on the first surface of the first insulating layer; a plurality of conductive pillars formed in the first insulating layer and on the first wiring layer, and connected to the second surface of the first insulating layer; a second wiring layer formed on the second surface of the first insulating layer and electrically connected with the conductive pillars; a second insulating layer formed on the second surface of the first insulating layer and the second wiring layer, wherein a portion of a surface of the second wiring layer is exposed from the second insulating layer.
  • The present invention further provides a method of manufacturing an interposer substrate, comprising: providing a carrier having a first wiring layer and a plurality of conductive pillars disposed on the first wiring layer; forming on the carrier a first insulating layer that has a first surface and a second surface opposing the first surface and is coupled to the carrier via the first surface thereof, with the conductive pillars being exposed from the second surface of the first insulating layer; forming on the second surface of the first insulating layer and the conductive pillars a second wiring layer that is electrically connected with the conductive pillars; forming on the second surface of the first insulating layer and the second wiring layer a second insulating layer, from which a portion of a surface of the second wiring is exposed; and removing the carrier to allow the first wiring layer to be exposed from the first surface of the first insulating layer.
  • In an embodiment, the entire carrier is removed.
  • In an embodiment, the first insulating layer is formed on the carrier through a molding, coating, or lamination method, and the first insulating layer is made of a molding compound, a primer material, or a dielectric material.
  • In an embodiment, the surface of the first wiring layer is lower than the first surface of the first insulating layer.
  • In an embodiment, the terminal surface of each of the conductive pillars is flush with the second surface of the first insulating layer.
  • In an embodiment, the second wiring layer acts as a plurality of solder ball pads.
  • In an embodiment, the surface of the second wiring layer is flush with the surface of the second insulating layer.
  • In an embodiment, the second insulating layer is formed by a molding, coating or lamination method, and the first insulating layer is made of a molding compound, a primer, or a dielectric materials.
  • In an embodiment, a portion of the carrier is retained and acts as the supporting structure for the first surface of the first insulating layer.
  • Accordingly, in the interposer substrate and the method of manufacturing the same according the present invention, the second wiring layer is formed with solder ball pads therein, without the need of conventional conductive pillars. As a result, the steps of the manufacturing process can be reduced, as well as the cost.
    • BRIEF DESCRIPTION OF DRAWINGS
  • The present invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein:
  • FIGS. 1A-1F are cross-sectional views showing a method of manufacturing a conventional interposer substrate, wherein FIG. 1F′ is another embodiment of FIG. 1F; and
  • FIGS. 2A-2F are cross-sectional views showing a method of manufacturing an interposer substrate according to the present invention, wherein FIG. 2F′ is another embodiment of FIG. 2F.
    •  DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
  • The present invention is described in the following with specific embodiments, so that one skilled in the pertinent art can easily understand other advantages and effects of the present invention from the disclosure of the present invention.
  • It should be noted that all the drawings are not intended to limit the present invention. Various modification and variations can be made without departing from the spirit of the present invention. Further, terms, such as “upper”, “first”, “second” and “one” etc., are merely for illustrative purpose and should not be construed to limit the scope of the present invention.
  • FIGS. 2A-2F are cross-sectional views showing a method of manufacturing an interposer substrate (coreless) according to the present invention. In an embodiment, the interposer substrate 2 is a carrier used in a flip-chip chip scale package (FCCSP).
  • As shown in FIG. 2A, a carrier 20 is provided. In an embodiment, the carrier 20 is a substrate such as a copper foil substrate, but the present invention is not limited thereto. An embodiment uses the copper foil substrate having a metal material 20 a on the two sides thereof as an example.
  • As shown in FIG. 2B, a first wiring layer 21 is formed on the carrier 20 through a patterning process.
  • In an embodiment, the first wiring layer 21 comprises a plurality of electrical connecting pads 210 and a plurality of conductive traces 211.
  • As shown in FIG. 2C, a plurality of conductive pillars 22 are electro-patterned on electrical connection pads 210 of the first wiring layer 21 through a patterning process.
  • In an embodiment, the conductive pillars 22 are in contact and electrically connected with the electrical connection pads 210 of the first wiring layer 21.
  • As shown in FIG. 2D, a first insulating layer 23 is formed on the carrier 20, the first insulating layer 23 has a first surface 23 a and second surface 23 b opposing the first surface 23 a, the first insulating layer 23 is coupled to the carrier 20 via the first surface 23 a of the insulating layer 23, and the conductive pillars 22 are exposed from the second surface 23 b of the first insulating layer 23.
  • In an embodiment, the first insulating layer 23 is formed on the carrier 20 by a molding, coating or lamination method, and the first insulating layer 23 is made of a molding compound, a primer, or a dielectric material such as epoxy.
  • In an embodiment, the terminal surface 22 a of each of the conductive pillars 22 is flush with second surface 23 b of the first insulating layer 23.
  • As shown in FIG. 2E, a second wiring layer 24 is formed on the second surface 23 b of the first insulating layer 23 and the conductive pillars 22, and a second insulating layer 26 is formed on the second surface 23 b of the first insulating layer 23 for encapsulating the second wiring layer 24.
  • In an embodiment, the second wiring layer 24 is a plurality of solder ball pads for coupling with the solder balls (not shown), and a portion of the surface of the second wiring layer 24 is exposed from the second insulating layer 26. For example, the surface 24 a of the second wiring layer 24 is flush with or lower than the surface 26 a of the second insulating layer 26.
  • In an embodiment, the second insulating layer 26 is formed by a molding, coating or lamination method, and the second insulating layer 26 is made of a molding compound, epoxy, or a dielectric material.
  • As shown in FIG. 2F, the entire carrier 20 is removed, allowing the surface 21 a of the first wiring layer 21 to be exposed from the first surface 23 a of the first insulating layer 23, and the surface 21 a of the first wiring layer 21 is lower than the first surface 23 a of the first insulating layer 23.
  • In an embodiment, the metal material 20 a is removed by etching. The upper surface 21 a of the first wiring layer 21 is slightly etched away, allowing the upper surface 21 a of the first wiring layer 21 to be recessed on the first surface 23 a of the first insulating layer 23.
  • As shown in FIG. 2F′, a portion of the carrier 20 is etched away, allowing the remaining carrier to act as a supporting structure 20′, and the surface 21 a of the first wiring layer 21 is exposed from the first surface 23 a of the first insulating layer 23.
  • Accordingly, the second wiring layer 24 having solder ball pads can be directly formed after forming a plurality of conductive pillars 22, so as to reduce the manufacturing process and cost.
  • The present invention further provides an interposer substrate 2, 2′: having a first insulating layer 23, a first wiring layer 21, a plurality of conductive pillars 22, a second wiring layer 24, and a second insulating layer 26.
  • The first insulating layer 23 has a first surface 23 a and a second surface 23 b opposing the first surface 23 a, and the first insulating layer 23 is made of a molding compound, epoxy, or a dielectric material.
  • The first wiring layer 21 is embedded in the first surface 23 a of the first insulating layer 23, and the surface 21 a of the first wiring layer 21 is lower than the first surface 23 a of the first insulating layer 23.
  • The conductive pillars 22 are formed in the first insulating layer 23 and coupled to the second surface 23 b of the first insulating layer 23, and the terminal surface 22 a of each of the conductive pillars 22 is flush with the second surface 23 b of the first insulating layer 23.
  • The second wiring layer 24 is formed on the second surface 23 b of the first insulating layer 23 and the conductive pillars 22 and electrically connected with the conductive pillars 22, and is formed by a plurality of solder balls.
  • The second insulating layer 26 is formed on the second surface 23 b of the first insulating layer 23 and the second wiring layer 24, allowing a portion of the surface of the second wiring layer 24 to be exposed from the second insulating layer 26.
  • In an embodiment, the surface 24 a of the second wiring layer 24 may be flush with or lower than the surface 26 a of the second insulating layer 26.
  • In an embodiment, the interposer substrate 2′ further comprises a supporting structure 20′ formed on the first surface 23 a of the first insulating layer 23.
  • In summary, the interposer substrate and the method of manufacturing the same according to the present invention are applied in products having a stacked structure with fine pitch and high pin number, such as a smart phone, tablet, internet, and laptop. The interposer substrate according to the present invention is highly desirable to be used in products that require high speed operation, low profile, high functionality, and high storage.
  • In an embodiment, the interposer substrate 2, 2′ according to the present invention can be coupled to a logic package or memory package via the first wiring layer 21.
  • The present invention has been described using exemplary preferred embodiments. However, it is to be understood that the scope of the present invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements. The scope of the claims, therefore, should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Claims (11)

1.-9. (canceled)
10. A method of manufacturing an interposer substrate, comprising:
providing a carrier having a first wiring layer and a plurality of conductive pillars disposed on the first wiring layer;
forming on the carrier a first insulating layer that has a first surface and a second surface opposing the first surface and is coupled to the carrier via the first surface thereof, with the conductive pillars being exposed from the second surface of the first insulating layer;
forming on the second surface of the first insulating layer and the conductive pillars a second wiring layer that is electrically connected with the conductive pillars;
forming on the second surface of the first insulating layer and the second wiring layer a second insulating layer, from which a portion of a surface of the second wiring is exposed; and
removing the carrier to allow the first wiring layer to be exposed from the first surface of the first insulating layer.
11. The method of claim 10, wherein the first insulating layer is formed on the carrier by a molding, coating, or lamination process.
12. The method of claim 10, wherein the first wiring layer has a surface lower than the first surface of the first insulating layer.
13. The method of claim 10, wherein each of the conductive pillars has a terminal surface flush with the second surface of the first insulating layer.
14. The method of claim 10, wherein the second wiring layer is formed by a plurality of solder ball pads.
15. The method of claim 10, wherein the surface of the second wiring layer is flush with a surface of the second insulating layer.
16. The method of claim 10, wherein the surface of the second wiring layer is lower than a surface of the second insulating layer.
17. The method of claim 10, wherein the second insulating layer is formed by a molding, coating or lamination process.
18. The method of claim 10, wherein the entire carrier is removed.
19. The method of claim 10, wherein a portion of the carrier is retained for acting as a supporting structure.
US15/796,713 2014-08-29 2017-10-27 Interposer substrate and method of manufacturing the same Abandoned US20180047662A1 (en)

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US9831165B2 (en) 2017-11-28

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