US20170307468A1

US20170307468A1 - Semiconductor device and wafer with reference circuit and related methods

Info

Publication number: US20170307468A1
Application number: US15/133,614
Authority: US
Inventors: Jean-Francois Carpentier; Patrick LeMaitre; Jean-Robert Manouvrier; Charles Baudot; Bertrand Borot
Original assignee: STMicroelectronics SA; STMicroelectronics Crolles 2 SAS
Current assignee: STMicroelectronics International NV Switzerland
Priority date: 2016-04-20
Filing date: 2016-04-20
Publication date: 2017-10-26
Anticipated expiration: 2036-04-20
Also published as: US10274395B2; US10677684B2; US20190113415A1; US20170363507A1; US20220050010A1; US20170307687A1; US20200256759A1; US11680870B2; US9791346B1; US11187613B2; US10180373B2

Abstract

A semiconductor device may include a semiconductor wafer, and a reference circuit carried by the semiconductor wafer. The reference circuit may include optical DUTs, a first set of photodetectors coupled to outputs of the optical DUTs, an optical splitter coupled to inputs of the optical DUTs, and a second set of photodetectors coupled to the optical splitter. The optical splitter is to be coupled to an optical source and configured to transmit a reference optical signal to the first set of photodetectors via the optical DUTs and the second set of photodetectors.

Description

TECHNICAL FIELD

The present disclosure relates to the field of photonics, and, more particularly, to an electro-optic device and related methods.

BACKGROUND

Integrated optical devices (i.e. photonic chip) for directly processing optical signals have become of greater importance as optical fiber communications increasingly replace metallic cable and microwave transmission links. Integrated optical devices can advantageously be implemented as silicon optical circuits having compact dimensions at relatively low cost. Silicon optical circuits employ integrated waveguide structures formed in a silicon layer of silicon-on-insulator (SOI) substrates, forming a silicon photonic chip.
In some applications, the optical signal is injected in/extracted from the photonic chip in a near perpendicular fashion, with respect to the photonic chip substrate plane, by way of grating couplers formed in the silicon photonic chip for input-output of the photonic signal. When using the silicon substrate in such a coupling fashion, such as when coupling to an optical fiber, the optical fiber is mounted in near perpendicular fashion.
During manufacture of integrated optical devices, a large number of integrated optical devices are fabricated on a typical semiconductor wafer. As part of a rigorous manufacturing process, it may be helpful to measure optical loss for quality control at the wafer level. Since optical loss in individual optical components is relatively low, testing for loss is typically performed on a special purposed test structure (i.e. the test structure will not be functional for the customer) comprising a plurality of optical components daisy chained together. During testing, a known/reference optical input is injected into the test structure and the optical output is measured, and compared with the known/reference optical input. One potential issue with testing individual devices at the wafer level is that optical inputs and outputs must be precisely aligned to accurately measure device loss. This may cause the testing process to be quite long and difficult.

SUMMARY

Generally speaking, a semiconductor device may include a semiconductor wafer, and at least one reference circuit carried by the semiconductor wafer. The at least one reference circuit may include a plurality of a plurality of optical devices under tests (DUTs), a first set of photodetectors coupled to outputs of the plurality of optical DUTs, at least one optical splitter coupled to inputs of the plurality of optical DUTs, and a second set of photodetectors coupled to the at least one optical splitter. The at least one optical splitter is to be coupled to an optical source and configured to transmit a reference optical signal to the first set of photodetectors via the plurality of optical DUTs and the second set of photodetectors. Advantageously, the at least one reference circuit may be readily tested for determining optical loss.
In some embodiments, the at least one optical splitter may comprise first and second optical splitters. The first optical splitter may be coupled to the inputs of the plurality of optical DUTs, and the second optical splitter may be coupled to inputs of the second set of photodetectors. In other embodiments, the at least one optical splitter may comprise a single optical splitter.
Also, the at least one reference circuit may comprise a first plurality of output terminals respectively coupled to the first set of photodetectors. In other embodiments, the at least one reference circuit may comprise a summer circuit configured to sum outputs of the second set of photodetectors.
The at least one reference circuit may comprise a second plurality of output terminals respectively coupled to outputs of the second set of photodetectors. The first set of photodetectors may be spaced apart from the second set of photodetectors. The at least one optical splitter may comprise a balanced optical splitter, for example. The at least one reference circuit may comprise a grating coupler coupled to an input of the at least one optical splitter.
The semiconductor device may also comprise a plurality of integrated circuits (ICs) carried by the semiconductor wafer, and a plurality of scribe lines therebetween. The at least one reference circuit may be carried within the plurality of scribe lines.
Another aspect is directed to a semiconductor wafer comprising a semiconductor wafer device, and at least one reference circuit carried by the semiconductor wafer device. The at least one reference circuit may include a plurality of a plurality of optical DUTs, a first set of photodetectors coupled to outputs of the plurality of optical DUTs, at least one optical splitter coupled to inputs of the plurality of optical DUTs, and a second set of photodetectors coupled to the at least one optical splitter. The at least one optical splitter may be coupled to an optical source and configured to transmit a reference optical signal to the first set of photodetectors via the plurality of optical DUTs and the second set of photodetectors.
Another aspect is directed to a method for testing a semiconductor device comprising at least one reference circuit. The at least one reference circuit may comprise a plurality of a plurality of optical DUTs, a first set of photodetectors coupled to outputs of the plurality of optical DUTs, at least one optical splitter coupled to inputs of the plurality of optical DUTs, and a second set of photodetectors coupled to the at least one optical splitter. The method may include coupling the at least one optical splitter to an optical source for transmitting a reference optical signal to the first set of photodetectors via the plurality of optical DUTs and the second set of photodetectors, and determining an optical loss of the plurality of optical DUTs based upon a difference in electrical output between the first and second sets of photodetectors.
Yet another aspect is directed to a method for making a semiconductor device comprising forming at least one reference circuit carried by a semiconductor wafer, and forming the at least one reference circuit. The at least one reference circuit may include a plurality of a plurality of optical DUTs, a first set of photodetectors coupled to outputs of the plurality of optical DUTs, at least one optical splitter coupled to inputs of the plurality of optical DUTs, and a second set of photodetectors coupled to the at least one optical splitter. The at least one optical splitter may be coupled to an optical source and configured to transmit a reference optical signal to the first set of photodetectors via the plurality of optical DUTs and the second set of photodetectors.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1-2 are schematic diagrams of portions of a reference circuit, according to the present disclosure.

FIG. 3 is a semiconductor wafer, according to the present disclosure.

FIGS. 4-5 are schematic diagrams of portions of another embodiment of the reference circuit, according to the present disclosure.

FIGS. 6-7 are schematic diagrams of portions of another embodiment of the reference circuit, according to the present disclosure.

FIG. 8 is a schematic diagram of portions of another embodiment of the reference circuit, according to the present disclosure.

FIG. 9 is a flowchart of a method, according to the present disclosure.

DETAILED DESCRIPTION

The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which several embodiments of the invention are shown. This present disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Like numbers refer to like elements throughout, and base 100 reference numerals are used to indicate similar elements in alternative embodiments.
Referring initially to FIGS. 1-3, a semiconductor device 32 according to the present disclosure is now described. The semiconductor device 32 illustratively includes a semiconductor wafer (e.g. a 300 mm silicon wafer or SOI wafer) 34, and a reference circuit (or testing circuit) 20 carried by the semiconductor wafer. The semiconductor device 32 illustratively includes a plurality of ICs 33 a-33 t carried by the semiconductor wafer 34, and a plurality of scribe lines therebetween. The reference circuit 20 is illustratively carried within the plurality of scribe lines. In this embodiment, the reference circuit 20 is removed/destroyed after singulation, but in other embodiments, the reference circuit may be located beyond the plurality of scribe lines, i.e. it may remain in the ICs 33 a-33 t after singulation. In some embodiments, the semiconductor wafer 34 can include one or more test ICs comprising the reference circuit 20.
In the illustrated embodiment, only one IC 33 a illustratively includes the reference circuit 20. Each IC 33 a-33 t includes other circuitry 35, which represents functional circuitry for use after singulation, i.e. non-test circuitry. But in some embodiments, each and every IC 33 a-33 t includes a reference circuit 20, i.e. the semiconductor device 32 would include a plurality of reference circuits. In other embodiments, each and every IC 33 a-33 t includes a plurality of reference circuits 20, for example, at two reference circuits at opposing sides of a respective IC.
The reference circuit 20 illustratively includes a grating coupler (or optical grating coupler) 22 to be coupled to an optical source (e.g. a laser optical source) 21. The reference circuit 20 illustratively includes a plurality of optical DUTs 24 a-24 n, 25 a-25 n, 26 a-26 n. Each optical DUT 24 a-24 n, 25 a-25 n, 26 a-26 n may comprise, for example, an optical waveguide, or an optical modulator component, such as meandering optical waveguides. The plurality of optical DUTs 24 a-24 n, 25 a-25 n, 26 a-26 n illustratively includes N parallel channels of DUTs, and each parallel channel may comprise a respective device type. In other words, in the illustrative embodiment, there are N optical devices being tested.
The reference circuit 20 illustratively includes a single optical splitter (e.g. a balanced optical splitter) 23 coupled between inputs of the plurality of optical DUTs 24 a-24 n, 25 a-25 n, 26 a-26 n and the grating coupler 22. In the illustrated embodiment, the single optical splitter 23 comprises a 1×2N splitter, with the combination of 1×N balanced splitter +1×2 balanced splitter on each output, for example. The reference circuit 20 illustratively includes a first set of photodetectors (e.g. photodiodes) 27 a-27 n coupled to outputs of the plurality of optical DUTs 24 a-24 n, 25 a-25 n, 26 a-26 n, and a second set of photodetectors (e.g. photodiodes) 29 a-29 n coupled to other outputs of the single optical splitter 23. Also, the reference circuit 20 illustratively includes a first plurality of output terminals 28 a-28 n respectively coupled to the first set of photodetectors 27 a-27 n, providing an individual output for each channel (or each type of DUT) of the plurality of optical DUTs 24 a-24 n, 25 a-25 n, 26 a-26 n. The reference circuit 20 illustratively includes a summer circuit 30 configured to sum outputs of the second set of photodetectors 29 a-29 n, and a second output terminal 31 coupled to an output of the summer circuit. The first and second output terminals 28 a-28 n, 31 comprise electrically conductive material, for example, copper, aluminum.
In some embodiments, the first set of photodetectors 27 a-27 n may be spaced apart from the second set of photodetectors 29 a-29 n. In other embodiments, the first set of photodetectors 27 a-27 n may be adjacent to the second set of photodetectors 29 a-29 n. Also, in this embodiment, the first and second sets of photodetectors 27 a-27 n, 29 a-29 n have matched responsivity values. The matching requirement is obtained either by appropriate design/layout/process of photodetectors and/or by adjacent hypothesis.
The single optical splitter 23 is to be coupled to the optical source 21 and is configured to transmit a reference optical signal to the first set of photodetectors 27 a-27 n via the plurality of optical DUTs 24 a-24 n, 25 a-25 n, 26 a-26 n and the second set of photodetectors 29 a-29 n. Since the second set of photodetectors 29 a-29 n receives the reference optical signal directly from the single optical splitter 23, the electrical output from the second output terminal 31 provides a lossless basis or combined reference current (outside of the intrinsic loss from the second set of photodetectors and the single optical splitter) for measuring the performance of the plurality of optical DUTs 24 a-24 n, 25 a-25 n, 26 a-26 n. Helpfully, the reference circuit 20 may be readily tested for determining optical loss by deriving a difference in a reference current 38 at the second output terminal 31 and a sum of the first plurality of output terminals 28 a-28 n.
The reference current 38 is governed by the following equation: I₀=N*R*P₀; where N is the number of the optical device; where R is the matched responsivity value, and where P₀is the balanced optical power level.
Another aspect is directed to a semiconductor wafer 32 comprising a semiconductor wafer device (e.g. an IC) 34, and at least one reference circuit 20 carried by the semiconductor wafer device. The at least one reference circuit 20 may include a plurality of a plurality of optical DUTs 24 a-24 n, 25 a-25 n, 26 a-26 n, a first set of photodetectors 27 a-27 n coupled to outputs of the plurality of optical DUTs, at least one optical splitter 23 coupled to inputs of the plurality of optical DUTs, and a second set of photodetectors 29 a-29 n coupled to the at least one optical splitter. The at least one optical splitter 23 may be coupled to an optical source 21 and configured to transmit a reference optical signal to the first set of photodetectors 27 a-27 n via the plurality of optical DUTs 24 a-24 n, 25 a-25 n, 26 a-26 n and the second set of photodetectors 29 a-29 n.
Referring now additionally to FIG. 10 and a flowchart 40 therein, another aspect is directed to a method for testing a semiconductor device (e.g. an individual IC or a semiconductor wafer comprising a plurality of ICs) 32. (Block 41). The semiconductor device 32 comprises at least one reference circuit 20. The at least one reference circuit 20 may comprise a plurality of a plurality of optical DUTs 24 a-24 n, 25 a-25 n, 26 a-26 n, a first set of photodetectors 27 a-27 n coupled to outputs of the plurality of optical DUTs, at least one optical splitter 23 coupled to inputs of the plurality of optical DUTs, and a second set of photodetectors 29 a-29 n coupled to the at least one optical splitter. The method may include coupling the at least one optical splitter 23 to an optical source 21 for transmitting an optical signal to the first set of photodetectors 27 a-27 n via the plurality of optical DUTs 24 a-24 n, 25 a-25 n, 26 a-26 n and the second set of photodetectors 29 a-29 n. (Block 43). The method may comprise determining an optical loss of the plurality of optical DUTs 24 a-24 n, 25 a-25 n, 26 a-26 n based upon a ratio in electrical output between the first and second sets of photodetectors 27 a-27 n, 29 a-29 n. (Blocks 45, 47).
Yet another aspect is directed to a method for making a semiconductor device 32 comprising forming at least one reference circuit 20 carried by a semiconductor wafer 34, and forming the at least one reference circuit. The at least one reference circuit 20 may include a plurality of a plurality of optical DUTs 24 a-24 n, 25 a-25 n, 26 a-26 n, a first set of photodetectors 27 a-27 n coupled to outputs of the plurality of optical DUTs, at least one optical splitter 23 coupled to inputs of the plurality of optical DUTs, and a second set of photodetectors 29 a-29 n coupled to the at least one optical splitter. The at least one optical splitter 23 may be coupled to an optical source 21 and configured to transmit a reference optical signal to the first set of photodetectors 27 a-27 n via the plurality of optical DUTs 24 a-24 n, 25 a-25 n, 26 a-26 n and the second set of photodetectors 29 a-29 n.
In the field of manufacturing optical devices, there is a desire to measure optical losses for finished devices for quality control purposes. In typical approaches, determining the optical loss for manufactured optical devices was difficult since individual loss was quite low (e.g. on the order of 0.015 dB per component). To address the issue, some approaches would cascade the optical devices together between an optical input and an optical output, i.e. defining a reference circuit.
The overall loss of the reference circuit was determined and divided by the number of test optical devices to determine average device loss. If the determined loss is outside the acceptable range, the wafer is considered defective and removed from the manufacturing process. A potential issue with this approach is that the optical input and output require precise alignment to avoid unintentional loss due to misalignment. This alignment issue is worsened when an optical fiber array needs to be aligned with multiple outputs (due to the intrinsic misalignment within the array). Since this testing is done at the wafer level before singulation, this laborious effort could grow geometrically if each wafer includes multiple reference circuits. Indeed, this task can be exhaustive when each IC within a wafer includes a reference circuit.
The reference circuit 20 disclosed herein provides an approach to this problem. Firstly, since the output terminals 28 a-28 n, 31 are electrical, the alignment of the output terminal reading is substantially easier and can use typical electrical probes. Also, there is only one or two optical inputs (i.e. the grating coupler 22), which reduces the amount of alignment effort needed to determine a loss percentage. Indeed, in the embodiments of FIGS. 1-3, there is only one grating coupler 22, 222, 322, which is used for both the reference signal and the loss signal. This also eliminates the need for aligning an optical fiber array. In particular, the loss is governed by the following equation: Loss=N*I_i/I₀in the case of one output terminal 31. A threshold condition at 3σ for example: N*I_i/I₀>Loss 3σ (Loss 3σ being the device tolerance versus the technology/platform specifications) can be used to do Optical Wafer Sorting (OWS).
Referring now additionally to FIGS. 4-5, another embodiment of the reference circuit 120 is now described. In this embodiment of the reference circuit 120 those elements already discussed above with respect to FIGS. 1-3 are incremented by 100 and most require no further discussion herein. This embodiment differs from the previous embodiment in that this reference circuit 120 illustratively includes first and second gratings couplers 122 a-122 b, and first and second optical splitters 123 a-123 b respectively coupled to the first and second gratings couplers. The first optical splitter 123 a is coupled between an output of the first grating coupler 122 a and the inputs of the plurality of optical DUTs 124 a-124 n, 125 a-125 n, 126 a-126 n. The second optical splitter 123 b is coupled between an output of the second grating coupler 122 b and the inputs of the second set of photodetectors 129 a-129 n. In this embodiment, the first and second optical splitters 123 a-123 b each comprises a balanced optical splitter, for example.
Referring now additionally to FIGS. 6-7, another embodiment of the reference circuit 220 is now described. In this embodiment of the reference circuit 220 those elements already discussed above with respect to FIGS. 1-3 are incremented by 200 and most require no further discussion herein. This embodiment differs from the previous embodiment in that no balanced optical power is required to drive the plurality of optical DUTs 124 a-124 n, 125 a-125 n, 126 a-126 n and the second set of photodetectors 129 a-129 n. Also, this embodiment differs from the previous embodiment in that this reference circuit 220 illustratively includes a second plurality of output terminals 231 a-231 n respectively coupled to outputs of the second set of photodetectors 229 a-229 n. In other words, the summer circuit 30, 130 of the above embodiments is omitted.
Referring now additionally to FIG. 8, another embodiment of the reference circuit 320 is now described. In this embodiment of the reference circuit 320 those elements already discussed above with respect to FIGS. 1-3 are incremented by 300 and most require no further discussion herein. This embodiment differs from the previous embodiment in that this reference circuit 320 illustratively includes first and second optical splitters 323 a-323 b coupled downstream from the optical source 321. The output P_inof the optical source 321 is split in half P_in/2 and fed into the inputs of the first and second optical splitters 323 a-323 b. The 1×2 balanced splitter is similar to the one described herein above.
This embodiment differs from the previous embodiment in that there is two set of photodetectors 327 a-327 n and 329 a-329 n (local matrix 350), which are close from layout point of view to solve the hypothesis of matched responsivity for the DUT channel and the reference one. Also, in this embodiment, the first and second optical splitters 323 a-323 b may either be balanced or unbalanced.
Many modifications and other embodiments of the present disclosure will come to the mind of one skilled in the art having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is understood that the present disclosure is not to be limited to the specific embodiments disclosed, and that modifications and embodiments are intended to be included within the scope of the appended claims.

Claims

1. A semiconductor device comprising:

a semiconductor layer; and

at least one reference circuit carried by said semiconductor layer, said at least one reference circuit comprising

a plurality of optical devices under tests (DUTs),

a first set of photodetectors coupled to outputs of said plurality of optical DUTs,

at least one optical splitter coupled to inputs of said plurality of optical DUTs, and

a second set of photodetectors coupled to said at least one optical splitter,

said at least one optical splitter to be coupled to an optical source and configured to transmit a reference optical signal to said first set of photodetectors via said plurality of optical DUTs and said second set of photodetectors.

2. The semiconductor device of claim 1 wherein said at least one optical splitter comprises first and second optical splitters; wherein said first optical splitter is coupled to the inputs of said plurality of optical DUTs; and wherein said second optical splitter is coupled to inputs of said second set of photodetectors.

3. The semiconductor device of claim 1 wherein said at least one optical splitter comprises a single optical splitter.

4. The semiconductor device of claim 1 wherein said at least one reference circuit comprises a first plurality of output terminals respectively coupled to said first set of photodetectors.

5. The semiconductor device of claim 1 wherein said at least one reference circuit comprises a summer circuit configured to sum outputs of said second set of photodetectors.

6. The semiconductor device of claim 1 wherein said at least one reference circuit comprises a second plurality of output terminals respectively coupled to outputs of said second set of photodetectors.

7. The semiconductor device of claim 1 wherein said first set of photodetectors is spaced apart from said second set of photodetectors.

8. The semiconductor device of claim 1 wherein said at least one optical splitter comprises a balanced optical splitter.

9. The semiconductor device of claim 1 wherein said at least one reference circuit comprises a grating coupler coupled to an input of said at least one optical splitter.

10. A semiconductor wafer comprising:

a semiconductor wafer device; and

at least one reference circuit carried by said semiconductor wafer device, said at least one reference circuit comprising

a plurality of optical devices under tests (DUTs),

a second set of photodetectors coupled to said at least one optical splitter,

11. The semiconductor wafer of claim 10 wherein said at least one optical splitter comprises first and second optical splitters; wherein said first optical splitter is coupled to the inputs of said plurality of optical DUTs; and wherein said second optical splitter is coupled to inputs of said second set of photodetectors.

12. The semiconductor wafer of claim 10 wherein said at least one optical splitter comprises a single optical splitter.

13. The semiconductor wafer of claim 10 wherein said at least one reference circuit comprises a first plurality of output terminals respectively coupled to said first set of photodetectors.

14. The semiconductor wafer of claim 10 wherein said at least one reference circuit comprises a summer circuit configured to sum outputs of said second set of photodetectors.

15. The semiconductor wafer of claim 10 wherein said at least one reference circuit comprises a second plurality of output terminals respectively coupled to outputs of said second set of photodetectors.

16. The semiconductor wafer of claim 10 wherein said semiconductor wafer device comprises a plurality of integrated circuits (ICs), and a plurality of scribe lines therebetween;

and wherein said at least one reference circuit is carried within said plurality of scribe lines.

17. A method for testing a semiconductor device comprising at least one reference circuit, the at least one reference circuit comprising a plurality of optical devices under tests (DUTs), a first set of photodetectors coupled to outputs of the plurality of optical DUTs, at least one optical splitter coupled to inputs of the plurality of optical DUTs, and a second set of photodetectors coupled to the at least one optical splitter, the method comprising:

coupling the at least one optical splitter to an optical source for transmitting a reference optical signal to the first set of photodetectors via the plurality of optical DUTs and the second set of photodetectors; and

determining an optical loss of the plurality of optical DUTs based upon a difference in electrical output between the first and second sets of photodetectors.

18. The method of claim 17 wherein the at least one optical splitter comprises first and second optical splitters; wherein the first optical splitter is coupled to the inputs of the plurality of optical DUTs; and wherein the second optical splitter is coupled to inputs of the second set of photodetectors.

19. The method of claim 17 wherein the at least one optical splitter comprises a single optical splitter.

20. The method of claim 17 wherein the at least one reference circuit comprises a first plurality of output terminals respectively coupled to the first set of photodetectors.

21. The method of claim 17 wherein the at least one reference circuit comprises a summer circuit configured to sum outputs of the second set of photodetectors.

22. The method of claim 17 wherein the at least one reference circuit comprises a second plurality of output terminals respectively coupled to outputs of the second set of photodetectors.

23. The method of claim 17 wherein the first set of photodetectors is spaced apart from the second set of photodetectors.

24. The method of claim 17 wherein the at least one optical splitter comprises a balanced optical splitter.

25. The method of claim 17 wherein the at least one reference circuit comprises a grating coupler coupled to an input of the at least one optical splitter.

26. A method for making a semiconductor device comprising:

forming at least one reference circuit carried by a semiconductor wafer; and

forming the at least one reference circuit to comprise

a plurality of optical devices under tests (DUTs),

a first set of photodetectors coupled to outputs of the plurality of optical DUTs,

at least one optical splitter coupled to inputs of the plurality of optical DUTs, and

a second set of photodetectors coupled to the at least one optical splitter,

the at least one optical splitter to be coupled to an optical source and configured to transmit a reference optical signal to the first set of photodetectors via the plurality of optical DUTs and the second set of photodetectors.

27. The method of claim 26 wherein the at least one optical splitter comprises first and second optical splitters; wherein the first optical splitter is coupled to the inputs of the plurality of optical DUTs; and wherein the second optical splitter is coupled to inputs of the second set of photodetectors.

28. The method of claim 26 wherein the at least one optical splitter comprises a single optical splitter.

29. The method of claim 26 wherein the at least one reference circuit comprises a first plurality of output terminals respectively coupled to the first set of photodetectors.

30. The method of claim 26 wherein the at least one reference circuit comprises a summer circuit configured to sum outputs of the second set of photodetectors.