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US20160148883A1 - Bond Pad Having Ruthenium Covering Passivation Sidewall - Google Patents

Bond Pad Having Ruthenium Covering Passivation Sidewall Download PDF

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Publication number
US20160148883A1
US20160148883A1 US15/010,022 US201615010022A US2016148883A1 US 20160148883 A1 US20160148883 A1 US 20160148883A1 US 201615010022 A US201615010022 A US 201615010022A US 2016148883 A1 US2016148883 A1 US 2016148883A1
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Prior art keywords
layer
bond pad
passivation
metal area
pad metal
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Abandoned
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US15/010,022
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Brian ZINN
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Texas Instruments Inc
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Texas Instruments Inc
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Publication date
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Priority to US15/010,022 priority Critical patent/US20160148883A1/en
Publication of US20160148883A1 publication Critical patent/US20160148883A1/en
Abandoned legal-status Critical Current

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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05676—Ruthenium [Ru] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01044—Ruthenium [Ru]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30101—Resistance

Definitions

  • Disclosed embodiments relate to bond pads for integrated circuits.
  • Integrated circuits (IC) devices are usually fabricated on a semiconductor wafer which has a plurality of IC device die each including a plurality of bond pads on its top surface that connect to various nodes in the device, such as for signal input, signal output and power supply nodes.
  • the bond pads are generally connected by a bond wire or other electrically conductive structure to permit utilization of the IC die.
  • Known methods for connecting an IC device to a lead frame or other support include wire bonding, Tape Automated Bonding (TAB), Controlled Collapse Chip Connection (C4) or bump bonding, and the use of electrically conductive adhesives.
  • some packaging technologies have used multi-layered bond pads having a top metal layer that is both electrically conductive and resistant to oxidation to provide high reliability (good corrosion performance) and high performance (low resistance), such as for wire bonding to the bond pads.
  • One such bond pad arrangement deposits a dielectric passivation layer(s) over an oxidizable uppermost metal interconnect layer such as copper or aluminum, and then forms a trench including dielectric sidewalls from the passivation layer.
  • a barrier layer comprising a refractory metal (e.g., Ta, TaN or Ti) is then deposited that lines the passivation sidewalls which provides good adhesion to the passivation material.
  • a multi-layer metal stack is formed on the barrier layer which can comprise palladium (Pd) as the final (top) layer on a nickel layer over the uppermost metal interconnect layer to provide a stable surface for wire bonding.
  • Pd being a platinum group metal has a low propensity for oxidation and is a good outer capping layer for the bond pad to prevent chemical attack of the oxidizable uppermost metal interconnect layer material thereunder.
  • Disclosed embodiments recognize although known multi-layer bond pad stacks for integrated circuits (IC) devices including palladium (Pd) on nickel (Ni) on an oxidizable uppermost metal interconnect layer material such as copper or aluminum generally provide high reliability (low corrosion susceptibility leading to good corrosion performance) and high performance (low resistance), Pd deposition and layer definition is generally an expensive process. Moreover, a barrier layer generally comprising a refractory metal is needed to line the sidewalls of the passivation trench to provide good adhesion for the Ni layer which does not directly adhere well to the passivation material(s).
  • ruthenium provides strong adhesion to conventional passivation dielectrics such as silicon oxide and/or silicon nitride, which enables bond pads for IC devices having Ru as the metal to be in direct contact with the passivation sidewalls of the trench and the bond pad areas of the uppermost metal interconnect layer.
  • This disclosed arrangement eliminates the need for a conventional refractory metal comprising barrier layer lining the passivation sidewalls of the bond pads.
  • Ru is recognized to have an electrically conductive oxide which reduces contact resistance to the Ru layer as compared to Pd when surface oxidized to PdO which has significantly less electrical conductivity.
  • Replacing Pd with Ru on the bond pads is recognized to provide other advantages too.
  • Pd can getter organics in the surrounding ambient so that airborne organics can attach thereon, which can result in adhesion problems to Pd, such as between bond wires and the top surface of the Pd layer.
  • Pd Chemical Mechanical Polishing/Planarizing (CMP) can also generally be difficult to achieve since Pd has a low corrosion susceptibility as compared to Ru, generally requiring a custom-made CMP polishing slurry with the limitation of relatively low Pd polishing rate as compared to more standard metal CMP processes, such as copper CMP.
  • Ru is also recognized to have a hardness 7 times ( ⁇ 700%) higher than Pd rendering it less susceptible to cracking, and such as during the bond wire attachment process. Moreover, Ru has about a 40% lower bulk electrical resistance as compared to Pd translating into improved electrical signal transmission and improved matching with copper or gold bond wires which are commonly used wire materials for connection to bond pads.
  • FIG. 1 is a flow chart that shows steps in an example method for forming bond pads having a metal bond pad area of oxidizable uppermost metal interconnect layer of an IC device including a Ru layer directly on the dielectric sidewalls of a passivation trench over the metal bond pad area, according to an example embodiment.
  • FIG. 2 is a cross sectional view of an example integrated circuit (IC) device including example bond pads having a Ru layer directly on the dielectric sidewalls of a passivation trench over the metal bond pad areas, according to an example embodiment.
  • IC integrated circuit
  • FIG. 3 is a cross sectional view of an example IC device including example bond pads having a Ru layer on a Ni layer on a refractory metal comprising barrier layer on the dielectric sidewalls of a passivation trench over the metal bond pad areas, according to an example embodiment.
  • Example embodiments are described with reference to the drawings, wherein like reference numerals are used to designate similar or equivalent elements. Illustrated ordering of acts or events should not be considered as limiting, as some acts or events may occur in different order and/or concurrently with other acts or events. Furthermore, some illustrated acts or events may not be required to implement a methodology in accordance with this disclosure.
  • FIG. 1 is a flow chart that shows steps in an example method 100 for forming bond pads having a Ru layer directly on the dielectric sidewalls of a trench over the metal bond pad area for an IC device, according to an example embodiment.
  • Step 101 comprise providing a substrate (e.g., a wafer) having least one IC device die formed thereon having an oxidizable uppermost metal interconnect layer which provides a plurality of bond pads coupled to circuit nodes on the IC device.
  • the plurality of bond pads includes a metal bond pad area, and at least one passivation layer thereon that provides a trench including dielectric sidewalls above the metal bond pad area.
  • the substrate can comprise silicon, silicon-germanium, or other semiconductor materials including III-V or II-VI materials.
  • the uppermost metal interconnect layer can comprise copper or aluminum, or alloys thereof.
  • Step 102 comprises depositing a Ru layer directly on the dielectric sidewalls of the trench and directly on the metal bond pad area.
  • the Ru layer being “directly on the metal bond pad area” includes the conventional contact arrangement where the uppermost metal interconnect layer has a native oxide layer formed at room temperature that is about 2 nm thick, such as primarily Cu 2 O in the case of copper.
  • the direct Ru attachment removes the need for a barrier layer lining the dielectric sidewalls of the trench.
  • the Ru layer can be sputter deposited using a Ru sputtering target for sputter coating on the substrate (e.g., wafer) surface. the Ru sputter can be performed at a relatively low temperature, such as 25° C. to 300° C.
  • the Ru layer may be a Ru alloy, such as including Zr or another transition metal from 1 ppm up to 10 wt. %, such as 0.5 wt. % to 5 wt. %.
  • the thickness of the Ru layer is generally 0.05 ⁇ m to 2 ⁇ m, such as from 0.2 ⁇ m to 2 ⁇ m.
  • Step 103 comprises patterning the Ru layer to provide a bond pad surface for the plurality of bond pads for bonding to the plurality of bond pads.
  • CMP can be used to remove overburden Ru above the top of the passivation layer(s) while preserving the Ru within the bond pad.
  • an aqueous slurry for polishing Ru can comprise about 0.5 wt. % to about 12 wt. % abrasive particles, such as comprising alumina, silica, cerium oxide or titania, at least one oxidizer in a concentration from 0.05 M to 1 M such as hydrogen peroxide, and a pH range from about 1 to 8.5.
  • FIG. 2 is a cross sectional view of an IC device 200 including example bond pads having a Ru layer 210 directly on the directly on the dielectric sidewalls of the trench and directly on the metal bond pad areas of the oxidizable uppermost metal interconnect layer, according to an example embodiment.
  • the metal stack is shown including three (3) layers of metal interconnect shown as M 1 , M 2 and M 3 damascened into ILD 1 , ILD 2 , and ILD 3 , respectively, on a dielectric layer over the top semiconductor surface that may be referred to as a pre-metal dielectric (PMD) 115 that is on another dielectric layer 116 , such as a thermally grown silicon oxide layer.
  • PMD pre-metal dielectric
  • An uppermost fourth metal interconnect layer shown as M 4 provides a plurality of bond pad metal areas shown as metal bond pad area 141 and metal bond pad area 142 .
  • a dielectric layer shown as 133 is on ILD 3 that provides an etch stop, such as comprising silicon nitride.
  • Plugs 121 are shown coupling M 3 to M 2 , plugs 122 coupling M 2 to Ml, and plugs 123 coupling M 1 to node 109 a shown as a diffusion (e.g., n+ or p+) and to 109 b shown as a gate electrode node (circuitry not shown, with 109 b being a contact to a metal oxide semiconductor (MOS) gate 112 on a gate dielectric 111 on the semiconductor surface of a substrate 108 , such as a silicon comprising surface in one embodiment.
  • the plugs 121 , 122 , 123 and 124 can all comprise tungsten, or other suitable electrically conductive plug material.
  • M 4 comprises an oxidizable metal material such as copper shown damascened into ILD 4 framed/lined by a refractory metal comprising barrier layer 127 .
  • the barrier layer 127 can comprise Ta, TaN, Ti or TiN.
  • M 4 can also comprise aluminum.
  • Metal bond pad areas 141 and 142 are shown coupled by plug 124 though dielectric layer 133 and ILD 3 to M 3 , and from M 3 all the way to features on the semiconductor surface, such as from metal bond pad area 141 to node 109 b.
  • IC device 200 includes at least one passivation layer(s) which defines a trench over the metal bond pad areas 141 and 142 , with the passivation shown in FIG. 2 being a first dielectric layer 147 (e.g., silicon nitride or silicon oxynitride) on a second dielectric layer 146 (e.g., silicon oxide or silicon oxynitride) on an etch stop layer 145 (e.g., silicon nitride).
  • a Ru layer 210 directly contacts the dielectric sidewalls of the trench and is directly connected to the top surface of the metal bond pad areas 141 and 142 , so that there is no conventional intervening barrier layer, typically being a refractive metal comprising barrier layer.
  • Ru provides strong adhesion to dielectric layers such as silicon oxide and silicon nitride, which enables direct connection of the Ru layer and thus elimination of conventional barrier layer processing needed for proper adhesion to dielectric layers such as silicon oxide and silicon nitride, such as needed by conventional metals including Ni.
  • a layer of an electrically conductive material may be positioned on the Ru layer.
  • IC devices having disclosed bond pads including a layer of Ru directly on the dielectric sidewalls of the trench and directly on the metal bond pad area of the uppermost metal interconnect layer will generally achieve the similar or better performance and reliability as known Pd on Ni.
  • Ru is recognized to be a platinum group metal with low oxidation potential. Ru has about a 40% lower bulk resistivity compared to Pd. Utilizing a Ru layer in place of a Pd layer on Ni layer on a barrier layer reduces back end of the line (BEOL) processing cost and cycle time.
  • Ru is expected to provide better bond adhesion as compared to Pd due to a reduced tendency to getter organics from the surrounding ambient, resulting in an improvement in bond strength and a resulting reliability improvement.
  • FIG. 3 is a cross sectional view of an example IC device 300 including example bond pads having a Ru layer 210 on a Ni layer 215 on a refractory metal comprising barrier layer 218 on the dielectric sidewalls of a passivation trench over the metal bond pad areas, according to an example embodiment.
  • a trench is over the metal bond pad areas 141 and 142 , with the passivation shown in FIG. 3 being the same as in FIG. 2 comprising a first dielectric layer 147 (e.g., silicon nitride or silicon oxynitride) on a second dielectric layer 146 .
  • the barrier layer 218 can comprise Ta, TaN, Ti or TiN, and can be 45 nm to 180 nm thick.
  • the Ni layer 215 can be from 0.1 ⁇ m to 1 ⁇ m thick, and the Ru layer can be 0.05 ⁇ m to 2 ⁇ m thick.
  • Disclosed embodiments can be integrated into a variety of assembly flows to form a variety of different semiconductor integrated circuit (IC) devices and related products.
  • the assembly can comprise single semiconductor die or multiple semiconductor die, such as PoP configurations comprising a plurality of stacked semiconductor die.
  • a variety of package substrates may be used.
  • the semiconductor die may include various elements therein and/or layers thereon, including barrier layers, dielectric layers, device structures, active elements and passive elements including source regions, drain regions, bit lines, bases, emitters, collectors, conductive lines, conductive vias, etc.
  • the semiconductor die can be formed from a variety of processes including bipolar, insulated-gate bipolar transistor (IGBT), CMOS, BiCMOS and MEMS.
  • IGBT insulated-gate bipolar transistor

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Abstract

A method of forming bond pads includes providing a substrate including an integrated circuit (IC) device formed thereon having an oxidizable uppermost metal interconnect layer which provides a plurality of bond pads that are coupled to circuit nodes on the IC device. The plurality of bond pads include a metal bond pad area. At least one passivation layer provides a trench including dielectric sidewalls above the metal bond pad area. A ruthenium (Ru) layer is deposited directly on the dielectric sidewalls and directly on the metal bond pad area, which removes the need for a barrier layer lining the dielectric sidewalls of the trench. The Ru layer is patterned to provide a bond pad surface for the plurality of bond pads.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • Under 35 U.S.C. §120, this continuation application claims priority to and benefits of U.S. patent application Ser. No. 14/278,613, filed on May 15, 2014, the entirety of which is incorporated herein by reference.
    • FIELD
  • Disclosed embodiments relate to bond pads for integrated circuits.
    • BACKGROUND
  • Integrated circuits (IC) devices are usually fabricated on a semiconductor wafer which has a plurality of IC device die each including a plurality of bond pads on its top surface that connect to various nodes in the device, such as for signal input, signal output and power supply nodes. The bond pads are generally connected by a bond wire or other electrically conductive structure to permit utilization of the IC die. Known methods for connecting an IC device to a lead frame or other support include wire bonding, Tape Automated Bonding (TAB), Controlled Collapse Chip Connection (C4) or bump bonding, and the use of electrically conductive adhesives.
  • To provide a reliable and low resistance attachment to the bond pad surface, such as by bond wires, some packaging technologies have used multi-layered bond pads having a top metal layer that is both electrically conductive and resistant to oxidation to provide high reliability (good corrosion performance) and high performance (low resistance), such as for wire bonding to the bond pads. One such bond pad arrangement deposits a dielectric passivation layer(s) over an oxidizable uppermost metal interconnect layer such as copper or aluminum, and then forms a trench including dielectric sidewalls from the passivation layer. A barrier layer comprising a refractory metal (e.g., Ta, TaN or Ti) is then deposited that lines the passivation sidewalls which provides good adhesion to the passivation material. A multi-layer metal stack is formed on the barrier layer which can comprise palladium (Pd) as the final (top) layer on a nickel layer over the uppermost metal interconnect layer to provide a stable surface for wire bonding. Pd being a platinum group metal has a low propensity for oxidation and is a good outer capping layer for the bond pad to prevent chemical attack of the oxidizable uppermost metal interconnect layer material thereunder.
    • SUMMARY
  • This Summary is provided to introduce a brief selection of disclosed concepts in a simplified form that are further described below in the Detailed Description including the drawings provided. This Summary is not intended to limit the claimed subject matter's scope.
  • Disclosed embodiments recognize although known multi-layer bond pad stacks for integrated circuits (IC) devices including palladium (Pd) on nickel (Ni) on an oxidizable uppermost metal interconnect layer material such as copper or aluminum generally provide high reliability (low corrosion susceptibility leading to good corrosion performance) and high performance (low resistance), Pd deposition and layer definition is generally an expensive process. Moreover, a barrier layer generally comprising a refractory metal is needed to line the sidewalls of the passivation trench to provide good adhesion for the Ni layer which does not directly adhere well to the passivation material(s).
  • Disclosed embodiments recognize ruthenium (Ru) provides strong adhesion to conventional passivation dielectrics such as silicon oxide and/or silicon nitride, which enables bond pads for IC devices having Ru as the metal to be in direct contact with the passivation sidewalls of the trench and the bond pad areas of the uppermost metal interconnect layer. This disclosed arrangement eliminates the need for a conventional refractory metal comprising barrier layer lining the passivation sidewalls of the bond pads. Moreover, Ru is recognized to have an electrically conductive oxide which reduces contact resistance to the Ru layer as compared to Pd when surface oxidized to PdO which has significantly less electrical conductivity.
  • Replacing Pd with Ru on the bond pads is recognized to provide other advantages too. Disclosed embodiments recognize Pd can getter organics in the surrounding ambient so that airborne organics can attach thereon, which can result in adhesion problems to Pd, such as between bond wires and the top surface of the Pd layer. Pd Chemical Mechanical Polishing/Planarizing (CMP) can also generally be difficult to achieve since Pd has a low corrosion susceptibility as compared to Ru, generally requiring a custom-made CMP polishing slurry with the limitation of relatively low Pd polishing rate as compared to more standard metal CMP processes, such as copper CMP.
  • Ru is also recognized to have a hardness 7 times (˜700%) higher than Pd rendering it less susceptible to cracking, and such as during the bond wire attachment process. Moreover, Ru has about a 40% lower bulk electrical resistance as compared to Pd translating into improved electrical signal transmission and improved matching with copper or gold bond wires which are commonly used wire materials for connection to bond pads.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • Reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, wherein:
  • FIG. 1 is a flow chart that shows steps in an example method for forming bond pads having a metal bond pad area of oxidizable uppermost metal interconnect layer of an IC device including a Ru layer directly on the dielectric sidewalls of a passivation trench over the metal bond pad area, according to an example embodiment.
  • FIG. 2 is a cross sectional view of an example integrated circuit (IC) device including example bond pads having a Ru layer directly on the dielectric sidewalls of a passivation trench over the metal bond pad areas, according to an example embodiment.
  • FIG. 3 is a cross sectional view of an example IC device including example bond pads having a Ru layer on a Ni layer on a refractory metal comprising barrier layer on the dielectric sidewalls of a passivation trench over the metal bond pad areas, according to an example embodiment.
    •  DETAILED DESCRIPTION
  • Example embodiments are described with reference to the drawings, wherein like reference numerals are used to designate similar or equivalent elements. Illustrated ordering of acts or events should not be considered as limiting, as some acts or events may occur in different order and/or concurrently with other acts or events. Furthermore, some illustrated acts or events may not be required to implement a methodology in accordance with this disclosure.
  • FIG. 1 is a flow chart that shows steps in an example method 100 for forming bond pads having a Ru layer directly on the dielectric sidewalls of a trench over the metal bond pad area for an IC device, according to an example embodiment. Step 101 comprise providing a substrate (e.g., a wafer) having least one IC device die formed thereon having an oxidizable uppermost metal interconnect layer which provides a plurality of bond pads coupled to circuit nodes on the IC device. The plurality of bond pads includes a metal bond pad area, and at least one passivation layer thereon that provides a trench including dielectric sidewalls above the metal bond pad area.
  • The substrate can comprise silicon, silicon-germanium, or other semiconductor materials including III-V or II-VI materials. The uppermost metal interconnect layer can comprise copper or aluminum, or alloys thereof.
  • Step 102 comprises depositing a Ru layer directly on the dielectric sidewalls of the trench and directly on the metal bond pad area. As used herein, the Ru layer being “directly on the metal bond pad area” includes the conventional contact arrangement where the uppermost metal interconnect layer has a native oxide layer formed at room temperature that is about 2 nm thick, such as primarily Cu2O in the case of copper. The direct Ru attachment removes the need for a barrier layer lining the dielectric sidewalls of the trench. The Ru layer can be sputter deposited using a Ru sputtering target for sputter coating on the substrate (e.g., wafer) surface. the Ru sputter can be performed at a relatively low temperature, such as 25° C. to 300° C. Due to the about 10× lower cost of Ru as compared to Pd, Ru targets are about 35% to 55% lower cost for when compared to Pd targets. The Ru layer may be a Ru alloy, such as including Zr or another transition metal from 1 ppm up to 10 wt. %, such as 0.5 wt. % to 5 wt. %. The thickness of the Ru layer is generally 0.05 μm to 2 μm, such as from 0.2 μm to 2 μm.
  • Step 103 comprises patterning the Ru layer to provide a bond pad surface for the plurality of bond pads for bonding to the plurality of bond pads. CMP can be used to remove overburden Ru above the top of the passivation layer(s) while preserving the Ru within the bond pad. For example, an aqueous slurry for polishing Ru can comprise about 0.5 wt. % to about 12 wt. % abrasive particles, such as comprising alumina, silica, cerium oxide or titania, at least one oxidizer in a concentration from 0.05 M to 1 M such as hydrogen peroxide, and a pH range from about 1 to 8.5.
  • FIG. 2 is a cross sectional view of an IC device 200 including example bond pads having a Ru layer 210 directly on the directly on the dielectric sidewalls of the trench and directly on the metal bond pad areas of the oxidizable uppermost metal interconnect layer, according to an example embodiment. The metal stack is shown including three (3) layers of metal interconnect shown as M1, M2 and M3 damascened into ILD1, ILD2, and ILD3, respectively, on a dielectric layer over the top semiconductor surface that may be referred to as a pre-metal dielectric (PMD) 115 that is on another dielectric layer 116, such as a thermally grown silicon oxide layer. An uppermost fourth metal interconnect layer shown as M4 provides a plurality of bond pad metal areas shown as metal bond pad area 141 and metal bond pad area 142. A dielectric layer shown as 133 is on ILD3 that provides an etch stop, such as comprising silicon nitride.
  • Plugs 121 are shown coupling M3 to M2, plugs 122 coupling M2 to Ml, and plugs 123 coupling M1 to node 109 a shown as a diffusion (e.g., n+ or p+) and to 109 b shown as a gate electrode node (circuitry not shown, with 109 b being a contact to a metal oxide semiconductor (MOS) gate 112 on a gate dielectric 111 on the semiconductor surface of a substrate 108, such as a silicon comprising surface in one embodiment. The plugs 121, 122, 123 and 124 can all comprise tungsten, or other suitable electrically conductive plug material.
  • M4 comprises an oxidizable metal material such as copper shown damascened into ILD4 framed/lined by a refractory metal comprising barrier layer 127. For example, the barrier layer 127 can comprise Ta, TaN, Ti or TiN. M4 can also comprise aluminum. Metal bond pad areas 141 and 142 are shown coupled by plug 124 though dielectric layer 133 and ILD3 to M3, and from M3 all the way to features on the semiconductor surface, such as from metal bond pad area 141 to node 109 b.
  • IC device 200 includes at least one passivation layer(s) which defines a trench over the metal bond pad areas 141 and 142, with the passivation shown in FIG. 2 being a first dielectric layer 147 (e.g., silicon nitride or silicon oxynitride) on a second dielectric layer 146 (e.g., silicon oxide or silicon oxynitride) on an etch stop layer 145 (e.g., silicon nitride). A Ru layer 210 directly contacts the dielectric sidewalls of the trench and is directly connected to the top surface of the metal bond pad areas 141 and 142, so that there is no conventional intervening barrier layer, typically being a refractive metal comprising barrier layer. As noted above disclosed embodiments recognize Ru provides strong adhesion to dielectric layers such as silicon oxide and silicon nitride, which enables direct connection of the Ru layer and thus elimination of conventional barrier layer processing needed for proper adhesion to dielectric layers such as silicon oxide and silicon nitride, such as needed by conventional metals including Ni. Optionally, a layer of an electrically conductive material may be positioned on the Ru layer.
  • IC devices having disclosed bond pads including a layer of Ru directly on the dielectric sidewalls of the trench and directly on the metal bond pad area of the uppermost metal interconnect layer will generally achieve the similar or better performance and reliability as known Pd on Ni. Like Pd, Ru is recognized to be a platinum group metal with low oxidation potential. Ru has about a 40% lower bulk resistivity compared to Pd. Utilizing a Ru layer in place of a Pd layer on Ni layer on a barrier layer reduces back end of the line (BEOL) processing cost and cycle time. Moreover, as noted above, Ru is expected to provide better bond adhesion as compared to Pd due to a reduced tendency to getter organics from the surrounding ambient, resulting in an improvement in bond strength and a resulting reliability improvement.
  • FIG. 3 is a cross sectional view of an example IC device 300 including example bond pads having a Ru layer 210 on a Ni layer 215 on a refractory metal comprising barrier layer 218 on the dielectric sidewalls of a passivation trench over the metal bond pad areas, according to an example embodiment. A trench is over the metal bond pad areas 141 and 142, with the passivation shown in FIG. 3 being the same as in FIG. 2 comprising a first dielectric layer 147 (e.g., silicon nitride or silicon oxynitride) on a second dielectric layer 146. The barrier layer 218 can comprise Ta, TaN, Ti or TiN, and can be 45 nm to 180 nm thick. The Ni layer 215 can be from 0.1 μm to 1 μm thick, and the Ru layer can be 0.05 μm to 2 μm thick.
  • Disclosed embodiments can be integrated into a variety of assembly flows to form a variety of different semiconductor integrated circuit (IC) devices and related products. The assembly can comprise single semiconductor die or multiple semiconductor die, such as PoP configurations comprising a plurality of stacked semiconductor die. A variety of package substrates may be used. The semiconductor die may include various elements therein and/or layers thereon, including barrier layers, dielectric layers, device structures, active elements and passive elements including source regions, drain regions, bit lines, bases, emitters, collectors, conductive lines, conductive vias, etc. Moreover, the semiconductor die can be formed from a variety of processes including bipolar, insulated-gate bipolar transistor (IGBT), CMOS, BiCMOS and MEMS.
  • Those skilled in the art to which this disclosure relates will appreciate that many other embodiments and variations of embodiments are possible within the scope of the claimed invention, and further additions, deletions, substitutions and modifications may be made to the described embodiments without departing from the scope of this disclosure.

Claims (20)

What is claimed is:
1. A device, comprising:
a semiconductor substrate;
a metal layer formed above the semiconductor substrate;
a bond pad metal area formed above the metal layer and coupled to the metal layer using a via plug;
a passivation layer patterned with an opening exposing the bond pad metal area, the passivation layer forming a trench with the bond pad metal area, the trench having passivation sidewalls; and
a ruthenium (Ru) layer covering the passivation sidewalls and the bond pad metal area.
2. The device of claim 1, wherein the Ru layer is formed directly on the passivation sidewalls and the bond pad metal area.
3. The device of claim 1, further comprising:
a barrier layer formed directly on the passivation sidewalls and the bond pad metal area, the barrier layer directly interfacing the bond pad metal area with the Ru layer.
4. The device of claim 1, further comprising:
a barrier layer formed directly on the passivation sidewalls and the bond pad metal area;
a nickel layer formed directly on the barrier layer and within the trench, wherein the Ru layer is positioned directly on the nickel layer.
5. The device of claim 1, further comprising:
a barrier layer formed directly on the passivation sidewalls and the bond pad metal area, the barrier layer interfacing the bond pad metal area with the Ru layer, the barrier layer includes a material selected from a group consisting of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), and combinations thereof.
6. The device of claim 1, further comprising:
a first transistor formed in the semiconductor substrate;
a second transistor formed in the semiconductor substrate, wherein the metal layer couples the first transistor to the second transistor.
7. The device of claim 1, wherein the bond pad metal area and the Ru layer form a bond pad sized to receive a bond wire.
8. The device of claim 1, wherein the Ru layer has a thickness greater than 0.2 um.
9. The device of claim 1, wherein the passivation layer has a top surface above the trench and free of contact from the Ru layer.
10. An integrated circuit, comprising:
a substrate;
transistors formed on the substrate;
a metal layer formed above the substrate and interconnecting the transistors;
an bond pad metal area formed above the metal layer and coupled to the metal layer using a via plug;
a passivation layer patterned with an opening exposing the bond pad metal area, the passivation layer forming a trench with the bond pad metal area, the trench having passivation sidewalls; and
a ruthenium (Ru) layer covering the passivation sidewalls and the bond pad metal area.
11. The integrated circuit of claim 10, wherein the Ru layer is formed directly on the passivation sidewalls and the bond pad metal area.
12. The integrated circuit of claim 10, further comprising:
a barrier layer formed directly on the passivation sidewalls and the bond pad metal area, the barrier layer directly interfacing the bond pad metal area with the Ru layer.
13. The integrated circuit of claim 10, further comprising:
a barrier layer formed directly on the passivation sidewalls and the bond pad metal area;
a nickel layer formed directly on the barrier layer and within the trench, wherein the Ru layer is positioned directly on the nickel layer.
14. The integrated circuit of claim 10, wherein the bond pad metal area and the Ru layer form a bond pad sized to receive a bond wire.
15. The integrated circuit of claim 10, the Ru layer has a thickness greater than 0.2 um.
16. The integrated circuit of claim 10, wherein the passivation layer has a top surface above the trench and free of contact from the Ru layer.
17. A method, comprising:
patterning a passivation layer to define an opening exposing a bond pad metal area on a semiconductor wafer and to form a trench having passivation sidewalls surrounding the opening; and
forming a ruthenium (Ru) layer to cover the passivation sidewalls and the bond pad metal area of the trench.
18. The method of claim 17, further comprising:
removing the Ru layer on a top surface of the passivation layer while preserving the Ru layer covering the trench.
19. The method of claim 17, wherein the forming the Ru layer includes:
depositing a Ru material directly onto the passivation sidewalls and the bond pad metal area.
20. The method of claim 17, further comprising:
forming a barrier layer directly on the passivation sidewalls and the bond pad metal area, the barrier layer including a material selected from a group consisting of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), and combinations thereof,
wherein the forming the Ru layer includes depositing a Ru material directly onto the barrier layer.
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