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US20160141386A1 - Method for forming semiconductor device with low sealing loss - Google Patents

Method for forming semiconductor device with low sealing loss Download PDF

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Publication number
US20160141386A1
US20160141386A1 US14/542,685 US201414542685A US2016141386A1 US 20160141386 A1 US20160141386 A1 US 20160141386A1 US 201414542685 A US201414542685 A US 201414542685A US 2016141386 A1 US2016141386 A1 US 2016141386A1
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layer
seal layer
seal
forming
substrate
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US9362382B1 (en
Inventor
Yu-Hsiang Hung
Yen-Liang Wu
Ssu-I Fu
Chih-Kai Hsu
Jyh-Shyang Jenq
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United Microelectronics Corp
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United Microelectronics Corp
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Assigned to UNITED MICROELECTRONICS CORPORATION reassignment UNITED MICROELECTRONICS CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: FU, SSU-I, HSU, CHIH-KAI, HUNG, YU-HSIANG, JENQ, JYH-SHYANG, WU, YEN-LIANG
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    • H01L29/66492—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/022—Manufacture or treatment of FETs having insulated gates [IGFET] having lightly-doped source or drain extensions selectively formed at the sides of the gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02167—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0335—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H01L29/66795—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]

Definitions

  • the invention relates to a manufacture process of a semiconductor device with dopant implanting structure, and more particularly to a Field Effect Transistor (FinFET) manufacturing process.
  • FinFET Field Effect Transistor
  • a nitride seal such as a silicon nitride (SiN) layer, serves as a diffusion barrier to oxygen and prevents contamination during subsequent processing.
  • SiN silicon nitride
  • the thickness of the SiN layer may become thinner than desired during a LDD wet cleaning process. It would worsen the performance of the semiconductor device and causes a serious dopant-loss problem, and might cause bump issues after an epitaxial (EPI) forming process.
  • EPI epitaxial
  • An object of the invention is to solve the seal loss issues of a dopant implanting structure as mentioned above.
  • a method for forming a semiconductor device includes steps of providing a substrate; forming a first seal layer over the substrate; forming a second seal layer atop the first seal layer; forming a patterned photoresist layer on the second seal layer; implanting a dopant into the substrate by using the patterned photoresist layer as a mask; executing a first removing process to remove the patterned photoresist layer, wherein the first seal layer has a higher etch rate than that of the second seal layer in the first removing process; and removing the second seal layer after removing the patterned photoresist layer.
  • the etch selectivity of the first seal layer to the second seal layer is greater than 7:1.
  • the total thickness of the first seal layer and the second seal layer is ranged between 20 A to 50 A.
  • the first seal layer may be made of SiN, SiON, SiCN, or other similar materials.
  • the second seal layer is a silicon oxide layer, or other layers having high etch selectivity to the first seal layer.
  • the substrate has a gate structure formed thereon.
  • the first seal layer covers the gate structure.
  • the step of forming the patterned photoresist layer includes forming a photoresist layer and patterning the photoresist layer by a lithographic process.
  • the first removing process is a wet etching process, or a dry etching process followed by a wet etching process.
  • the method further includes steps of forming a patterned hard mask layer on the first seal layer after the second seal layer being removed; forming a recess in the substrate by using the patterned hard mask as a mask; and forming an epitaxial layer into the recess.
  • the semiconductor device is a FinFET.
  • FIG. 1 is a cross-sectional view showing a gate structure formed for a process for forming a FinFET according to an embodiment of the invention.
  • FIGS. 2A and 2B are cross-sectional views showing a first and second seal layers deposited atop of a gate structure according to the embodiment of the invention.
  • FIG. 3 is a cross-sectional view showing a LDD structure formed according to the embodiment of the invention.
  • FIGS. 4A and 4B are cross-sectional views of the process for forming the FinFET according to the embodiment of the invention.
  • FIG. 5 is a cross-sectional view showing remaining steps for forming the FinFET according to the embodiment of the invention.
  • a gate patterning process is executed or performed on a substrate 1 having an isolation structure 11 , so that a gate structure 2 is formed. Then, as shown in FIGS. 2A and 2B , a first seal layer 3 is deposited atop the substrate 1 and covers the gate structure 2 , and a second seal layer 4 is deposited atop the first seal layer 3 .
  • the first seal layer 3 and the second seal layer 4 are LDD seal layers.
  • a patterned photoresist layer 5 is formed on the second seal layer 4 , and then a dopant is implanted into the substrate 1 by using the patterned photoresist layer 5 as a mask.
  • a first removing process is then executed to remove the patterned photoresist layer 5 .
  • the first removing process might be a dry etching process followed by a wet etching process, or just a wet etching process.
  • the first seal layer 3 has a higher etch rate than that of the second seal layer 4 .
  • the etch selectivity of the first seal layer 3 to the second seal layer 4 is greater than 7:1.
  • the first seal layer 3 may be a nitride layer made of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), or other similar materials.
  • the second seal layer 4 may be an oxide layer, such as, e.g. a silicon oxide layer, or other layers having higher etch selectivities to the first seal layer 3 .
  • the steps of forming the patterned photoresist layer, implanting dopant into the substrate and removing the patterned photoresist layer are repeated for multiple times, so as to form LDD structures in several predetermined regions in the substrate.
  • the second seal layer 4 is then removed after removing the patterned photoresist layer 5 .
  • the first seal layer 3 serves as an etch stop layer.
  • the second seal layer 4 is completely removed and the first seal layer 3 is remained.
  • FIG. 5 illustrates the remaining steps for forming FinFETs according to the embodiment of the invention.
  • a patterned hard mask layer 6 is formed atop the first seal layer 3 .
  • the patterned hard mask 6 might be constructed by two or more deposition processes.
  • the patterned hard mask 6 may be a nitride layer made of SiN, SiON, SiCN, or other similar materials.
  • the patterned hard mask 6 and the first seal layer 3 have the same material.
  • the total thickness of the first seal layer 3 and the second seal layer 4 is ranged between 20 angstrom ( ⁇ ) to 50 angstrom ( ⁇ ). While modifying a conventional FinFET manufacturing process by using or adopting the techniques and method of the embodiment of the invention, it is noticeable that to maintain or sustain the performance of the FinFET device, the total thickness of the first seal layer 3 and the patterned hard mask 6 must be kept constant.
  • the first seal layer 3 might have a thickness of 30 ⁇ in a conventional process, while the patterned hard mask 6 is constructed by two deposition processes, and each deposition process provide 60 ⁇ for the thickness of the patterned hard mask 6 . Accordingly, the total thickness of the first seal layer 3 and the patterned hard mask 6 is 150 ⁇ .
  • the thicknesses of the first seal layer 3 , the second seal layer 4 , the first and second deposited layers for the patterned hard mask 6 might be 15 ⁇ , 15 ⁇ , 75 ⁇ , and 60 ⁇ , respectively. Since the second seal layer 4 will be removed before the formation of the patterned hard mask 6 , the total thickness of the first seal layer 3 and the patterned hard mask 6 is still remained as 150 ⁇ .
  • a recess (not shown) is then formed in the substrate 1 by using the patterned hard mask 6 as a mask and an epitaxial layer (not shown) is formed into the recess.
  • formation of elements including additional spacers, source/drain region, epitaxial layer, silicides, and contact etch stop layer and replacement metal gate (RMG) process could be conducted thereafter to complete the fabrication of a metal gate transistor (not shown), and as these processes are well known to those skilled in the art, the details of which are not explained in for the sake of brevity. This completes the fabrication of a semiconductor device according to a preferred embodiment of the present invention.
  • an extra seal layer e.g. an oxide layer
  • the original seal layer e.g. a nitride layer

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Abstract

A method for forming a semiconductor device, includes steps of: providing a substrate; forming a first seal layer over the substrate; forming a second seal layer atop the first seal layer; forming a patterned photoresist layer on the second seal layer; implanting a dopant into the substrate by using the patterned photoresist layer as a mask; executing a first removing process to remove the patterned photoresist layer, wherein the first seal layer has a higher etch rate than that of the second seal layer in the first removing process; and removing the second seal layer after removing the patterned photoresist layer.

Description

    FIELD OF THE INVENTION
  • The invention relates to a manufacture process of a semiconductor device with dopant implanting structure, and more particularly to a Field Effect Transistor (FinFET) manufacturing process.
    • BACKGROUND OF THE INVENTION
  • While manufacturing semiconductor devices such as FinFETs having Lightly Doped Drain (LDD) structures, a nitride seal, such as a silicon nitride (SiN) layer, serves as a diffusion barrier to oxygen and prevents contamination during subsequent processing. However, the thickness of the SiN layer may become thinner than desired during a LDD wet cleaning process. It would worsen the performance of the semiconductor device and causes a serious dopant-loss problem, and might cause bump issues after an epitaxial (EPI) forming process.
    • SUMMARY OF THE INVENTION
  • An object of the invention is to solve the seal loss issues of a dopant implanting structure as mentioned above.
  • The present invention will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of preferred embodiments of this invention are presented herein for purpose of illustration and description only. It is not intended to be exhaustive or to be limited to the precise form disclosed.
  • According an embodiment of the invention, a method for forming a semiconductor device includes steps of providing a substrate; forming a first seal layer over the substrate; forming a second seal layer atop the first seal layer; forming a patterned photoresist layer on the second seal layer; implanting a dopant into the substrate by using the patterned photoresist layer as a mask; executing a first removing process to remove the patterned photoresist layer, wherein the first seal layer has a higher etch rate than that of the second seal layer in the first removing process; and removing the second seal layer after removing the patterned photoresist layer.
  • The etch selectivity of the first seal layer to the second seal layer is greater than 7:1.
  • The total thickness of the first seal layer and the second seal layer is ranged between 20 A to 50 A.
  • The first seal layer may be made of SiN, SiON, SiCN, or other similar materials.
  • The second seal layer is a silicon oxide layer, or other layers having high etch selectivity to the first seal layer.
  • The substrate has a gate structure formed thereon. The first seal layer covers the gate structure.
  • The step of forming the patterned photoresist layer includes forming a photoresist layer and patterning the photoresist layer by a lithographic process.
  • The first removing process is a wet etching process, or a dry etching process followed by a wet etching process.
  • The method further includes steps of forming a patterned hard mask layer on the first seal layer after the second seal layer being removed; forming a recess in the substrate by using the patterned hard mask as a mask; and forming an epitaxial layer into the recess.
  • According to an embodiment of the invention, the semiconductor device is a FinFET.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which:
  • FIG. 1 is a cross-sectional view showing a gate structure formed for a process for forming a FinFET according to an embodiment of the invention.
  • FIGS. 2A and 2B are cross-sectional views showing a first and second seal layers deposited atop of a gate structure according to the embodiment of the invention.
  • FIG. 3 is a cross-sectional view showing a LDD structure formed according to the embodiment of the invention.
  • FIGS. 4A and 4B are cross-sectional views of the process for forming the FinFET according to the embodiment of the invention.
  • FIG. 5 is a cross-sectional view showing remaining steps for forming the FinFET according to the embodiment of the invention.
    •  DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
  • Please refer to FIG. 1, a gate patterning process is executed or performed on a substrate 1 having an isolation structure 11, so that a gate structure 2 is formed. Then, as shown in FIGS. 2A and 2B, a first seal layer 3 is deposited atop the substrate 1 and covers the gate structure 2, and a second seal layer 4 is deposited atop the first seal layer 3. In this embodiment, the first seal layer 3 and the second seal layer 4 are LDD seal layers. To form the LDD structure as shown in FIG. 3, a patterned photoresist layer 5 is formed on the second seal layer 4, and then a dopant is implanted into the substrate 1 by using the patterned photoresist layer 5 as a mask.
  • A first removing process is then executed to remove the patterned photoresist layer 5. Referring to FIG. 4A, the first removing process might be a dry etching process followed by a wet etching process, or just a wet etching process. In the first removing process, the first seal layer 3 has a higher etch rate than that of the second seal layer 4. In general, the etch selectivity of the first seal layer 3 to the second seal layer 4 is greater than 7:1. The first seal layer 3 may be a nitride layer made of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), or other similar materials. The second seal layer 4 may be an oxide layer, such as, e.g. a silicon oxide layer, or other layers having higher etch selectivities to the first seal layer 3.
  • In general, the steps of forming the patterned photoresist layer, implanting dopant into the substrate and removing the patterned photoresist layer are repeated for multiple times, so as to form LDD structures in several predetermined regions in the substrate. During the multiple wet cleaning processes, if the seal layer loss happens, the gate structure and the substrate might be damaged.
  • Once the formation of LDD structures in several predetermined regions in the substrate is completed, as shown in FIG. 4B, the second seal layer 4 is then removed after removing the patterned photoresist layer 5. Please note that during removing of the second seal layer 4, another wet etching process is executed for the second seal layer 4, and the first seal layer 3 serves as an etch stop layer. In a preferred embodiment, the second seal layer 4 is completely removed and the first seal layer 3 is remained.
  • FIG. 5 illustrates the remaining steps for forming FinFETs according to the embodiment of the invention. After removing the second seal layer 4, a patterned hard mask layer 6 is formed atop the first seal layer 3. For certain purpose, the patterned hard mask 6 might be constructed by two or more deposition processes. The patterned hard mask 6 may be a nitride layer made of SiN, SiON, SiCN, or other similar materials. In a preferred embodiment, the patterned hard mask 6 and the first seal layer 3 have the same material.
  • The total thickness of the first seal layer 3 and the second seal layer 4 is ranged between 20 angstrom (Å) to 50 angstrom (Å). While modifying a conventional FinFET manufacturing process by using or adopting the techniques and method of the embodiment of the invention, it is noticeable that to maintain or sustain the performance of the FinFET device, the total thickness of the first seal layer 3 and the patterned hard mask 6 must be kept constant. For example, the first seal layer 3 might have a thickness of 30 Å in a conventional process, while the patterned hard mask 6 is constructed by two deposition processes, and each deposition process provide 60 Å for the thickness of the patterned hard mask 6. Accordingly, the total thickness of the first seal layer 3 and the patterned hard mask 6 is 150 Å. When modifying the conventional process into the method of the invention, the thicknesses of the first seal layer 3, the second seal layer 4, the first and second deposited layers for the patterned hard mask 6 might be 15 Å, 15 Å, 75 Å, and 60 Å, respectively. Since the second seal layer 4 will be removed before the formation of the patterned hard mask 6, the total thickness of the first seal layer 3 and the patterned hard mask 6 is still remained as 150 Å.
  • A recess (not shown) is then formed in the substrate 1 by using the patterned hard mask 6 as a mask and an epitaxial layer (not shown) is formed into the recess. Depending on the demand of the process, formation of elements (not shown) including additional spacers, source/drain region, epitaxial layer, silicides, and contact etch stop layer and replacement metal gate (RMG) process could be conducted thereafter to complete the fabrication of a metal gate transistor (not shown), and as these processes are well known to those skilled in the art, the details of which are not explained in for the sake of brevity. This completes the fabrication of a semiconductor device according to a preferred embodiment of the present invention.
  • To sum up, during the formation process of a dopant-implanting structure of a semiconductor device such a FinFET, an extra seal layer, e.g. an oxide layer, is added atop of the original seal layer, e.g. a nitride layer. According to the lower etching rate for the extra seal layer to the original seal layer during the wet clean process, the later (original seal layer) will be protected, and thus solve the LDD seal layer loss issue.
  • While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.

Claims (17)

1. A method for forming a semiconductor device, comprising steps of:
providing a substrate;
forming a first seal layer over the substrate;
forming a second seal layer atop the first seal layer;
forming a patterned photoresist layer on the second seal layer;
implanting a dopant into the substrate by using the patterned photoresist layer as a mask;
executing a first removing process to remove the patterned photoresist layer, wherein the first seal layer has a higher etch rate than that of the second seal layer in the first removing process; and
removing the second seal layer after removing the patterned photoresist layer.
2. The method according to claim 1, wherein the substrate has a gate structure formed thereon.
3. The method according to claim 2, wherein the first seal layer covers the gate structure.
4. The method according to claim 1, wherein the step of forming the patterned photoresist layer includes forming a photoresist layer and patterning the photoresist layer by a lithographic process.
5. The method according to claim 1, wherein the first removing process is a wet etching process.
6. The method according to claim 1, wherein the first removing process is a dry etching process followed by a wet etching process.
7. (canceled)
8. The method according to claim 1, wherein the etch selectivity of the first seal layer to the second seal layer is greater than 7:1.
9. The method according to claim 1, wherein the total thickness of the first seal layer and the second seal layer is ranged between 20 angstrom (Å) to 50 angstrom (Å).
10. The method according to claim 1, wherein the first seal layer is a nitride layer.
11. The method according to claim 10, wherein the nitride layer is a SiN layer.
12. The method according to claim 10, wherein the nitride layer is a SiON layer.
13. The method according to claim 10, wherein the nitride layer is a SiCN layer.
14. The method according to claim 1, wherein the second seal layer is an oxide layer.
15. The method according to claim 14, wherein the oxide layer is a silicon oxide layer.
16. The method according to claim 1, wherein the semiconductor device is a FinFET.
17. The method according to claim 1, wherein the first seal layer is a first LDD seal layer, and the second seal layer is a second LDD seal layer.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108231778A (en) * 2016-12-09 2018-06-29 联华电子股份有限公司 Semiconductor element and manufacturing method thereof
US11411009B2 (en) 2018-04-12 2022-08-09 United Microelectronics Corp. Semiconductor device and method for fabricating the same

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3993972B2 (en) * 2000-08-25 2007-10-17 富士通株式会社 Semiconductor device manufacturing method and semiconductor device
US6479339B2 (en) * 2000-10-10 2002-11-12 Texas Instruments Incorporated Use of a thin nitride spacer in a split gate embedded analog process
US7335945B2 (en) * 2003-12-26 2008-02-26 Electronics And Telecommunications Research Institute Multi-gate MOS transistor and method of manufacturing the same
US7652332B2 (en) 2007-08-10 2010-01-26 International Business Machines Corporation Extremely-thin silicon-on-insulator transistor with raised source/drain
US8772118B2 (en) * 2011-07-08 2014-07-08 Texas Instruments Incorporated Offset screen for shallow source/drain extension implants, and processes and integrated circuits
JP5913869B2 (en) * 2011-08-31 2016-04-27 林純薬工業株式会社 Etching solution composition and etching method
CN102655081B (en) 2012-04-16 2015-08-19 上海华力微电子有限公司 A kind of shallow junction of amorphous carbon sacrificial gate electrode structure and the preparation method of side wall
US9054163B2 (en) * 2013-11-06 2015-06-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method for via plating with seed layer
US9337258B2 (en) * 2013-12-20 2016-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making a FinFET device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108231778A (en) * 2016-12-09 2018-06-29 联华电子股份有限公司 Semiconductor element and manufacturing method thereof
US11411009B2 (en) 2018-04-12 2022-08-09 United Microelectronics Corp. Semiconductor device and method for fabricating the same

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