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US20160093536A1 - Integrated circuit having plural transistors with work function metal gate structures - Google Patents

Integrated circuit having plural transistors with work function metal gate structures Download PDF

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Publication number
US20160093536A1
US20160093536A1 US14/520,342 US201414520342A US2016093536A1 US 20160093536 A1 US20160093536 A1 US 20160093536A1 US 201414520342 A US201414520342 A US 201414520342A US 2016093536 A1 US2016093536 A1 US 2016093536A1
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layer
barrier layer
bottom barrier
trench
transistor
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US9318389B1 (en
Inventor
Chih-Wei Yang
Yu-Feng Liu
Jian-Cun KE
Chia-Fu Hsu
Yu-Ru Yang
En-Chiuan Liou
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Marlin Semiconductor Ltd
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United Microelectronics Corp
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Priority to US15/060,572 priority Critical patent/US9754841B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0135—Manufacturing their gate conductors
    • H10D84/014—Manufacturing their gate conductors the gate conductors having different materials or different implants
    • H01L21/82345—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • H01L27/088—
    • H01L29/42372—
    • H01L29/4966—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H10D84/0177—Manufacturing their gate conductors the gate conductors having different materials or different implants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 

Definitions

  • the present invention is related to an integrated circuit and a method of forming the same, and more particularly, to an integrated circuit having a plurality of transistors with different threshold voltages, and the method of forming the same.
  • Poly-silicon is conventionally used as a gate electrode in semiconductor devices, such as metal-oxide-semiconductors (MOS).
  • MOS metal-oxide-semiconductors
  • the conventional poly-silicon gate faces problems like low performances due to boron penetration, and unavoidable depletion effect that increases the equivalent thickness of the gate dielectric layer, reduces the gate capacitance, and worsens a driving force of the devices. Therefore, work function metals are used to replace the conventional poly-silicon gates as control electrodes that are suitable as high-K gate dielectric layers.
  • CMOS complementary metal-oxide semiconductor
  • one of the dual work function metal gates is used in an NMOS device and the other one is alternatively used in a PMOS device.
  • the conventional dual metal gate methods are categorized into gate first processes and gate last processes.
  • the annealing process for forming the source/drain ultra-shallow junction and the silicide process are performed after forming the metal gate.
  • a sacrificial gate or a replacement gate is provided in a first step, followed by performing processes used to construct a normal MOS transistor. Then, the sacrificial/replacement gate is removed to form a gate trench. Consequently, the gate trench is filled with metals according to the different electrical requirements.
  • the manufacturers are devoted to simplifying the manufacturing process.
  • the metal gate of the PMOS or the NMOS may include a plurality of metal layers.
  • the materials of the metal layers always affect the work function of the NMOS or the PMOS, and consequently affect the performances of the product. Thus, the manufacturers are searching for new manufacturing method to obtain a MOS with better work function performances.
  • the present invention therefore provides an integrated circuit having a plurality of transistors with different threshold voltages.
  • the present invention provides an integrated circuit including a substrate, a first transistor, a second transistor and a third transistor.
  • the first transistor has a first metal gate including a first bottom barrier layer, a first work function metal layer and a first metal layer.
  • the second transistor has a second metal gate including a second bottom barrier layer, a second work function metal layer and a second metal layer.
  • the third transistor has a third metal gate including a third bottom barrier layer, a third work function metal layer and a third metal layer.
  • the first transistor, the second transistor and the third transistor has the same conductive type.
  • a method of forming an integrated circuit is provided.
  • a dielectric layer having a first trench, a second trench and a third trench are provided.
  • a bottom barrier layer is formed on the dielectric layer, wherein the bottom barrier layer comprises a first bottom barrier layer in the first trench, a second bottom barrier layer in the second trench and a third bottom barrier layer in the third trench, wherein a nitrogen concentration of the first bottom barrier layer>a nitrogen concentration of the second bottom barrier layer>a nitrogen concentration of the third bottom barrier layer.
  • WFM work function metal
  • the present invention provides an integrated circuit structure having plural transistors and the method of forming the same. It is featured that the formed transistors have bottom barrier layers with different thickness and/or compositions, thereby tuning the electrical performance of the transistors and enable them different threshold voltages.
  • FIG. 1 to FIG. 10 are schematic diagrams of the method of forming the integrated circuit according to one embodiment of the present invention.
  • FIG. 1 to FIG. 10 are schematic diagrams of the method of forming an integrated circuit according to one embodiment of the present invention.
  • a substrate 300 is provided, such as a silicon substrate, a silicon-containing substrate or a silicon-on-insulator (SOI) substrate, but is not limited thereto.
  • a plurality of shallow trench isolations (STI) 302 are disposed on the substrate 300 . According to the areas encompassed by the STI 302 , a first active region 400 , a second active region 500 and a third active region 600 , which are insulated from each other, are defined on the substrate 300 .
  • STI shallow trench isolations
  • a first transistor 402 , a second transistor 502 and a third transistor 602 are formed on the substrate 300 in the first active region 400 , the second active region 500 and the third active region 600 respectively.
  • the first transistor 402 , the second transistor 502 and the third transistor 602 have the same conductive type. Preferably, they are N conductive transistors.
  • the first transistor 402 includes a first interface layer 404 , a first high-k dielectric layer 405 , a first etch stop layer 407 , a first sacrificial gate 406 , a first cap layer 408 , a first spacer 410 , a first lightly doped drain (LDD) 412 and a first source/drain 414 .
  • the first interface layer 404 can be a SiO 2 layer.
  • the first high-k dielectric layer 405 has a dielectric constant greater than 4 , and the material thereof includes rare earth metal oxides or lanthanide oxides, such as hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO 4 ), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), lanthanum aluminum oxide (LaAlO), tantalum oxide (Ta 2 O 5 ), zirconium oxide (ZrO 2 ), zirconium silicon oxide (ZrSiO 4 ), hafnium zirconium oxide (HfZrO), yttrium oxide (Yb 2 O 3 ), yttrium silicon oxide (YbSiO), zirconium aluminate (ZrAlO), hafnium aluminate (HfAlO), aluminum nitride (AlN), titanium oxide (TiO 2
  • the first etch stop layer 407 includes metal or metal/metal nitride, such as TiN.
  • the first sacrificial gate 406 is a poly-silicon gate. In another embodiment, the first sacrificial gate 406 is a multi-layered gate including a poly-silicon layer, an amorphous silicon layer or a germanium layer.
  • the first cap layer 408 is a SiN layer for example.
  • the first spacer 410 can be a multi-layered structure including high temperature oxide (HTO), SiN, SiO or SiN formed by hexachlorodisilane (Si 2 Cl 6 ) (HCD-SiN).
  • the first LDD 412 and the first source/drain 414 are formed by appropriate dopants implantation.
  • the first interface layer 404 and the first etch stop layer 407 can be omitted.
  • the second transistor 502 includes a second interface layer 504 , a second high-k dielectric layer 505 , a second etch stop layer 507 , a second sacrificial gate 506 , a second cap layer 508 , a second spacer 510 , a second LDD 512 and a second source/drain 514 .
  • the components in the second transistor 502 of this embodiment are similar to those of the first transistor 402 and are therefore not described repeatedly.
  • the third transistor 602 includes a third interface layer 604 , a third high-k dielectric layer 605 , a third sacrificial gate 606 , a third cap layer 608 , a third spacer 610 , a third LDD 612 and a third source/drain 614 .
  • the components in the third transistor 602 of this embodiment are similar to those of the first transistor 402 and are therefore not described repeatedly. It is noted that since the first transistor 402 , the second transistor 502 and the third transistor 602 have different threshold voltages, some components of these transistors may be different.
  • the first source/drain 414 , the second source/drain 514 and the third source/drain 614 have the same conductive type dopant, however, the concentrations thereof can be different.
  • the first high-k dielectric layer 405 , the second high-k dielectric layer 505 and the third high-k dielectric layer 606 may have different thickness.
  • the first transistor 402 , the second transistor 502 and the third transistor 602 can further include other semiconductor structures that are not explicitly shown in FIG. 1 , such as a silicide layer, a source/drain having an hexagon (also called sigma E) or an octagon shaped cross-section which is formed by selective epitaxial growth (SEG), or other protective films.
  • a contact etch stop layer (CESL) 306 and an inter-layer dielectric (ILD) layer 308 are formed on the substrate 300 to cover the first transistor 402 , the second transistor 502 and the third transistor 602 .
  • the CESL 306 can generate different degrees of stress in the first active region 400 , the second active region 500 and the third active region 600 to form a selective strain scheme (SSS) for the first transistor 402 , the second transistor 502 and the third transistor 602 , respectively.
  • SSS selective strain scheme
  • a planarization process such as a chemical mechanical polish (CMP) process or an etching-back process or combination thereof is performed to remove a part of the ILD layer 308 , a part of the CESL 306 , a part of the first spacer 410 , a part of the second spacer 510 , apart of the third spacer 610 and completely remove the first cap layer 408 , the second cap layer 508 and the third cap layer 608 , until the top surfaces of the first sacrificial gate 406 , the second sacrificial gate 506 and the third sacrificial gate 606 are exposed.
  • CMP chemical mechanical polish
  • a wet etching process and/or a dry etching process is performed to remove the first sacrificial gate 406 , the second sacrificial gate 506 and the third sacrificial gate 606 until exposing the first etch stop layer 407 , the second etch stop layer 507 and the third etch stop layer 607 .
  • a first trench 416 is formed in the first transistor 402
  • a second trench 516 is formed in the second transistor 502
  • a third trench 616 is formed in the third transistor 602 .
  • the first etch stop layer 407 , the second etch stop layer 507 and the third etch stop layer 607 can be removed.
  • an adjust layer 318 is formed comprehensively on the substrate 300 and is formed conformally along the surface of the first trench 416 , the second trench 516 and the third trench 616 .
  • the adjust layer 318 will become a part of the bottom barrier metal (BBM) layer in the subsequent steps and the material thereof is metal.
  • the adjust layer 318 is, for example, titanium (Ti). As shown in FIG.
  • the adjust layer 318 has a first adjust layer 318 a in the first trench 416 , which has a thinnest thickness, a second adjust layer 318 b in the second trench 516 , which has a middle thickness, and a third adjust layer 318 c , which has a thickest thickness.
  • the thickness of the first adjust layer 318 can be approximately zero.
  • the method for forming the adjust layer 318 with different thicknesses starts by forming an initial adjust layer (not shown) with uniform thickness in the first trench 416 , the second trench 516 and the third trench 616 .
  • a mask (not shown) is formed to cover the third trench 616 , and an etching back process is carried out to remove a part of the initial adjust layer (not shown) in the second trench 516 and the third trench 616 .
  • another mask (not shown) is formed to further cover the second trench 516 , followed by another etching process to further remove a part of the initial adjust layer (not shown) in the first trench 416 .
  • the initial adjust layer (not shown) in the first trench 416 can be completely removed.
  • the initial adjust layer (not shown) in the first trench 416 still remains a predetermined thickness. Lastly, all the masks are removed away.
  • the adjust layer 318 having the first adjust layer 318 a , the second adjust layer 318 b and the third adjust layer 318 c with different thicknesses respectively in the first trench 416 , the second trench 516 and the third trench 616 can be formed.
  • the method for forming the adjust layer 318 with different thicknesses can include forming an initial adjust layer (not shown) with uniform thickness in the first trench 416 , the second trench 516 and the third trench 616 .
  • a mask (not shown) is formed to cover the first trench 416 and a deposition process is performed to thicken the initial adjust layer (not shown) in the second trench 516 and the third trench 616 not covered by the mask.
  • Another mask (not shown) is formed to further cover the second trench 516 , and another deposition process is performed to thicken the initial adjust layer (not shown) in the third trench 616 .
  • a planarization process and/or an etching process is performed to remove the mask layer and the above initial adjust layer, thereby forming the adjust layer 318 with different thicknesses.
  • the method can start by directly forming a mask covering the first trench 416 , and a deposition process is performed to form the initial adjust layer (not shown) in the second trench 516 and the third trench 616 .
  • another mask (not shown) is formed for further covering the second trench 516 , and a deposition to thicken the initial adjust layer in the third trench 616 is carried out.
  • the adjust layer 318 can also be formed by other methods and should not be limited to the above methods.
  • an assisting layer 320 with uniform thickness is formed on the substrate 300 , covering the adjust layer 318 in the first trench 416 , the second trench 516 and the third trench 616 .
  • the assisting layer 320 includes metal, preferably a nitride material of the adjust layer 318 .
  • the assisting layer 320 can be TiN.
  • the following context shows the embodiment of the adjust layer 318 containing Ti and the assisting layer 320 containing TiN.
  • the bottom barrier layer 322 has a first bottom barrier layer 322 a , a second bottom barrier layer 322 b and a third bottom barrier layer 322 c .
  • the first bottom barrier layer 322 a disposed in the first trench 416 is formed by “the thinnest first adjust layer 318 a ” and “uniform assisting layer 320 ”.
  • the second bottom barrier layer 322 b disposed in the second trench 516 is formed by “the middle second adjust layer 318 b ” and “uniform assisting layer 320 ”.
  • the third bottom barrier layer 322 c disposed in the third trench 616 is formed by “the thickest third adjust layer 318 c ” and “uniform assisting layer 320 ”.
  • first bottom barrier layer 322 a , the second bottom barrier layer 322 b and the third bottom barrier layer 322 c have different properties.
  • the first bottom barrier layer 322 a is thinnest
  • the second bottom barrier layer 322 b is middle
  • the third barrier layer 322 c is thickest.
  • the thickness of the first adjust layer 318 a is approximately zero
  • the final thickness of the first bottom barrier layer 322 a is equal to that of the assisting layer 320 .
  • a concentration of the material of the adjust layer 320 (Ti) is smallest with respect to the first bottom barrier layer 322 a , the ratio is middle in the second bottom barrier layer 322 b and the ratio is largest in the third bottom barrier layer 322 c .
  • a concentration of the material of the assisting layer 322 (TiN) is largest with respect to the first bottom barrier layer 322 a , the ratio is middle in the second bottom barrier layer 322 b and the ratio is smallest in the third bottom barrier layer 322 c .
  • the first bottom barrier layer 322 a is therefore “N rich”, and the third bottom barrier layer 322 c is “Ti rich.”
  • the first transistor 402 , the second transistor 502 and the third transistor 602 can have different electrical performance.
  • the above embodiment shows forming the adjust layer 318 and then forming the assisting layer 320 , so the formed bottom barrier layer 322 has a Ti concentration increasing from bottom to top (from a side of the substrate 300 to the opposite side) and a N concentration decreasing from bottom to top.
  • the bottom barrier layer 322 when first forming the uniform assisting layer 320 and then forming the adjust layer 318 with different thickness, has a Ti concentration decreasing from bottom to top and a N concentration increasing from bottom to top.
  • the adjust layer 318 can have uniform thickness while the assisting layer 320 can have different thickness.
  • the assisting layer 320 has a thickest portion in the first trench 416 , a middle portion in the second trench 516 and a thinnest portion in the third trench 616 .
  • one or more than one nitrogen treatment can be incorporated into the above steps, thereby forming the bottom barrier layer 322 with different nitrogen concentrations.
  • an upper bottom barrier layer 324 is formed comprehensively on the substrate 300 .
  • the upper bottom barrier layer 324 is formed along the surface of the first bottom barrier layer 322 a in the first trench 416 , the second bottom barrier layer 322 b in the second trench 516 and the third bottom barrier layer 322 c in the third trench 616 , but these trenches 416 , 516 , 616 are not completely filled with the upper bottom barrier layer 324 .
  • the upper bottom barrier 324 can include TaN or Ta/TaN. In one embodiment, it is a uniform layer.
  • the upper bottom barrier layer 324 can have different thicknesses. As shown in FIG. 8 , the upper bottom barrier layer 324 has a first upper bottom barrier layer 324 a in the first trench 416 , which is thinnest, a second upper bottom barrier layer 324 b in the second trench 516 , which is middle, and a third upper bottom barrier layer 324 c , which is thickest.
  • the forming method thereof is similar to that for forming adjust layer 320 ; when the upper bottom barrier layer 324 comprises Ta/TaN, the forming method thereof is similar to the method for forming the bottom barrier layer 322 .
  • a work function metal (WFM) layer 326 , a top barrier layer 326 and a metal layer 330 are sequentially formed on the substrate 300 to completely fill the first trench 416 , the second trench 516 and the third trench 616 .
  • the WFM layer 326 can include titanium aluminides (TiAl), aluminum zirconium (ZrAl), aluminum tungsten (WAl), aluminum tantalum (TaAl) or aluminum hafnium (HfAl), but should not be limited thereto.
  • the WFM layer 326 can include Ni, Pd, Pt, Be, Ir, Te, Re, Ru, Rh, W, Mo, or WN, RuN, MoN, TiN, TaN, or WC, TaC, TiC, or TiAlN, TaAlN, but should not be limited thereto.
  • the top barrier layer 328 can include TiN, TiAlC, TiAlN, TaN, TaAlC, TaAlN, TiCuC, TiCuN, TaCuC or TaCuN, but is not limited thereto. In one embodiment, the top barrier layer 328 can be omitted.
  • the metal layer 330 includes Al, Ti, Ta, W, Nb, Mo, TiN, TiC, TaN, Ti/W or Ti/TiN, but is not limited thereto.
  • a planarization process is performed to simultaneously remove the metal layer 330 , the top barrier layer 328 , the WFM layer 326 , the upper bottom barrier layer 324 and the bottom barrier layer 322 outside of the first trench 416 , the second trench 516 and the third trench 616 .
  • the first etch stop layer 407 , the first bottom barrier layer 322 a , the upper bottom barrier layer (or the first bottom barrier layer 324 a ), the WFM layer 326 (the first WFM layer 326 a herein), the top barrier layer 328 (the first top barrier layer 328 a herein) and the metal layer 330 (the first metal layer 330 a herein) together form a first metal gate 418 of the first transistor 402 .
  • the third etch stop layer 607 , the third bottom barrier layer 322 c , the upper bottom barrier layer 324 (or the third bottom barrier layer 324 c ), the WFM layer 326 (the third WFM layer 326 c herein), the top barrier layer 328 (the third top barrier layer 328 c herein) and the metal layer 330 (the third metal layer 330 c herein) together form a third metal gate 618 in the third transistor 602 .
  • the first transistor 402 , the second transistor 502 and the third transistor 602 have the bottom barrier layer 322 with different thickness and different compositions, they can exhibit different electrical performance.
  • the first transistor 402 has the largest threshold voltage
  • the second transistor 502 has the middle one
  • the third transistor 602 has the smallest one.
  • the threshold voltage of the first transistor 402 is about 0.3V to 0.6V
  • the threshold voltage of the second transistor 502 is about 0.2V to 0.3V
  • the threshold voltage of the third transistor 602 is about 0.1V to 0.2V.
  • the above method shown in a gate-last process can also be applied in a gate-first process.
  • the above method shows forming the high-k gate dielectric layer before removing the sacrificial gate (namely, the high-k first process).
  • the material of the dielectric layer formed under the sacrificial gate is not limited to high-k material but can also include another dielectric material such as SiO 2 .
  • the first transistor 402 , the second transistor 502 and the third transistor 602 can be non-planar transistors such as Fin-FET and is not limited to the planar transistor shown above.
  • the present invention provides a structure having plural transistors and the forming method. It is featured that the formed transistors have bottom barrier layers with different thickness and/or composition, thereby tuning the electrical performance of the transistors and providing them with different threshold voltages.

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Abstract

The present invention provides an integrated circuit including a substrate, a first transistor, a second transistor and a third transistor. The first transistor has a first metal gate including a first bottom barrier layer, a first work function metal layer and a first metal layer. The second transistor has a second metal gate including a second bottom barrier layer, a second work function metal layer and a second metal layer. The third transistor has a third metal gate including a third bottom barrier layer, a third work function metal layer and a third metal layer. The first transistor, the second transistor and the third transistor has the same conductive type. A nitrogen concentration of the first bottom barrier layer>a nitrogen concentration of the second bottom barrier layer>a nitrogen concentration of the third bottom barrier layer.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention is related to an integrated circuit and a method of forming the same, and more particularly, to an integrated circuit having a plurality of transistors with different threshold voltages, and the method of forming the same.
  • 2. Description of the Prior Art
  • Poly-silicon is conventionally used as a gate electrode in semiconductor devices, such as metal-oxide-semiconductors (MOS). However, with a trend toward scaling down the size of semiconductor devices, the conventional poly-silicon gate faces problems like low performances due to boron penetration, and unavoidable depletion effect that increases the equivalent thickness of the gate dielectric layer, reduces the gate capacitance, and worsens a driving force of the devices. Therefore, work function metals are used to replace the conventional poly-silicon gates as control electrodes that are suitable as high-K gate dielectric layers.
  • In a complementary metal-oxide semiconductor (CMOS) device, one of the dual work function metal gates is used in an NMOS device and the other one is alternatively used in a PMOS device. It is well-known that the compatibility and the process controls of the dual metal gates are more complicated, whereas the thickness and the composition controls of the materials used in the dual metal gate method are more precise. The conventional dual metal gate methods are categorized into gate first processes and gate last processes. In a conventional dual metal gate method applied with the gate first process, the annealing process for forming the source/drain ultra-shallow junction and the silicide process are performed after forming the metal gate. In the conventional gate last process, a sacrificial gate or a replacement gate is provided in a first step, followed by performing processes used to construct a normal MOS transistor. Then, the sacrificial/replacement gate is removed to form a gate trench. Consequently, the gate trench is filled with metals according to the different electrical requirements. However, because of the complicated steps of the gate last processes, the manufacturers are devoted to simplifying the manufacturing process.
  • In the gate first process or the gate last process, the metal gate of the PMOS or the NMOS may include a plurality of metal layers. The materials of the metal layers always affect the work function of the NMOS or the PMOS, and consequently affect the performances of the product. Thus, the manufacturers are searching for new manufacturing method to obtain a MOS with better work function performances.
    • SUMMARY OF THE INVENTION
  • The present invention therefore provides an integrated circuit having a plurality of transistors with different threshold voltages.
  • According one embodiment of the present invention, the present invention provides an integrated circuit including a substrate, a first transistor, a second transistor and a third transistor. The first transistor has a first metal gate including a first bottom barrier layer, a first work function metal layer and a first metal layer. The second transistor has a second metal gate including a second bottom barrier layer, a second work function metal layer and a second metal layer. The third transistor has a third metal gate including a third bottom barrier layer, a third work function metal layer and a third metal layer. The first transistor, the second transistor and the third transistor has the same conductive type. A nitrogen concentration of the first bottom barrier layer>a nitrogen concentration of the second bottom barrier layer>a nitrogen concentration of the third bottom barrier layer.
  • According to another embodiment of the present invention, a method of forming an integrated circuit is provided. A dielectric layer having a first trench, a second trench and a third trench are provided. Next, a bottom barrier layer is formed on the dielectric layer, wherein the bottom barrier layer comprises a first bottom barrier layer in the first trench, a second bottom barrier layer in the second trench and a third bottom barrier layer in the third trench, wherein a nitrogen concentration of the first bottom barrier layer>a nitrogen concentration of the second bottom barrier layer>a nitrogen concentration of the third bottom barrier layer. Then, a work function metal (WFM) layer is formed on the bottom barrier layer in the first trench, the second trench and the third trench. Subsequently, a metal layer is formed on the WFM layer, wherein the first trench, the second trench and the third trench are completely filled with the metal layer.
  • The present invention provides an integrated circuit structure having plural transistors and the method of forming the same. It is featured that the formed transistors have bottom barrier layers with different thickness and/or compositions, thereby tuning the electrical performance of the transistors and enable them different threshold voltages.
  • These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 to FIG. 10 are schematic diagrams of the method of forming the integrated circuit according to one embodiment of the present invention.
    •  DETAILED DESCRIPTION
  • To provide a better understanding of the present invention, preferred embodiments will be described in detail. The preferred embodiments of the present invention are illustrated in the accompanying drawings with numbered elements.
  • Please refer to FIG. 1 to FIG. 10. FIG. 1 to FIG. 10 are schematic diagrams of the method of forming an integrated circuit according to one embodiment of the present invention. First, a substrate 300 is provided, such as a silicon substrate, a silicon-containing substrate or a silicon-on-insulator (SOI) substrate, but is not limited thereto. A plurality of shallow trench isolations (STI) 302 are disposed on the substrate 300. According to the areas encompassed by the STI 302, a first active region 400, a second active region 500 and a third active region 600, which are insulated from each other, are defined on the substrate 300. Then, a first transistor 402, a second transistor 502 and a third transistor 602 are formed on the substrate 300 in the first active region 400, the second active region 500 and the third active region 600 respectively. In one preferred embodiment of the present invention, the first transistor 402, the second transistor 502 and the third transistor 602 have the same conductive type. Preferably, they are N conductive transistors.
  • In one embodiment shown in FIG. 1, the first transistor 402 includes a first interface layer 404, a first high-k dielectric layer 405, a first etch stop layer 407, a first sacrificial gate 406, a first cap layer 408, a first spacer 410, a first lightly doped drain (LDD) 412 and a first source/drain 414. In one preferred embodiment of the present invention, the first interface layer 404 can be a SiO2 layer. The first high-k dielectric layer 405 has a dielectric constant greater than 4, and the material thereof includes rare earth metal oxides or lanthanide oxides, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO), tantalum oxide (Ta2O5), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO), yttrium oxide (Yb2O3), yttrium silicon oxide (YbSiO), zirconium aluminate (ZrAlO), hafnium aluminate (HfAlO), aluminum nitride (AlN), titanium oxide (TiO2), zirconium oxynitride (ZrON), hafnium oxynitride (HfON), zirconium silicon oxynitride (ZrSiON), hafnium silicon oxynitride (HfSiON), strontium bismuth tantalite (SrBi2Ta2O9, SBT), lead zirconate titanate (PbZrxTi1-xO3, PZT) or barium strontium titanate (BaxSr1-xTiO3, BST), but is not limited thereto. The first etch stop layer 407 includes metal or metal/metal nitride, such as TiN. The first sacrificial gate 406 is a poly-silicon gate. In another embodiment, the first sacrificial gate 406 is a multi-layered gate including a poly-silicon layer, an amorphous silicon layer or a germanium layer. The first cap layer 408 is a SiN layer for example. The first spacer 410 can be a multi-layered structure including high temperature oxide (HTO), SiN, SiO or SiN formed by hexachlorodisilane (Si2Cl6) (HCD-SiN). The first LDD 412 and the first source/drain 414 are formed by appropriate dopants implantation. In one embodiment, the first interface layer 404 and the first etch stop layer 407 can be omitted.
  • The second transistor 502 includes a second interface layer 504, a second high-k dielectric layer 505, a second etch stop layer 507, a second sacrificial gate 506, a second cap layer 508, a second spacer 510, a second LDD 512 and a second source/drain 514. The components in the second transistor 502 of this embodiment are similar to those of the first transistor 402 and are therefore not described repeatedly. The third transistor 602 includes a third interface layer 604, a third high-k dielectric layer 605, a third sacrificial gate 606, a third cap layer 608, a third spacer 610, a third LDD 612 and a third source/drain 614. The components in the third transistor 602 of this embodiment are similar to those of the first transistor 402 and are therefore not described repeatedly. It is noted that since the first transistor 402, the second transistor 502 and the third transistor 602 have different threshold voltages, some components of these transistors may be different. For instance, the first source/drain 414, the second source/drain 514 and the third source/drain 614 have the same conductive type dopant, however, the concentrations thereof can be different. In another embodiment, the first high-k dielectric layer 405, the second high-k dielectric layer 505 and the third high-k dielectric layer 606 may have different thickness. In addition, the first transistor 402, the second transistor 502 and the third transistor 602 can further include other semiconductor structures that are not explicitly shown in FIG. 1, such as a silicide layer, a source/drain having an hexagon (also called sigma E) or an octagon shaped cross-section which is formed by selective epitaxial growth (SEG), or other protective films.
  • After forming the first transistor 402, the second transistor 502 and the third transistor 602, a contact etch stop layer (CESL) 306 and an inter-layer dielectric (ILD) layer 308 are formed on the substrate 300 to cover the first transistor 402, the second transistor 502 and the third transistor 602. In one embodiment, the CESL 306 can generate different degrees of stress in the first active region 400, the second active region 500 and the third active region 600 to form a selective strain scheme (SSS) for the first transistor 402, the second transistor 502 and the third transistor 602, respectively.
  • As shown in FIG. 2, a planarization process, such as a chemical mechanical polish (CMP) process or an etching-back process or combination thereof is performed to remove a part of the ILD layer 308, a part of the CESL 306, a part of the first spacer 410, a part of the second spacer 510, apart of the third spacer 610 and completely remove the first cap layer 408, the second cap layer 508 and the third cap layer 608, until the top surfaces of the first sacrificial gate 406, the second sacrificial gate 506 and the third sacrificial gate 606 are exposed.
  • As shown in FIG. 3, a wet etching process and/or a dry etching process is performed to remove the first sacrificial gate 406, the second sacrificial gate 506 and the third sacrificial gate 606 until exposing the first etch stop layer 407, the second etch stop layer 507 and the third etch stop layer 607. A first trench 416 is formed in the first transistor 402, a second trench 516 is formed in the second transistor 502 and a third trench 616 is formed in the third transistor 602. In one embodiment, after forming the first trench 416, the second trench 516 and the third trench 616, the first etch stop layer 407, the second etch stop layer 507 and the third etch stop layer 607 can be removed.
  • As shown in FIG. 4, an adjust layer 318 is formed comprehensively on the substrate 300 and is formed conformally along the surface of the first trench 416, the second trench 516 and the third trench 616. In one embodiment of the invention, the adjust layer 318 will become a part of the bottom barrier metal (BBM) layer in the subsequent steps and the material thereof is metal. In one embodiment, when the first transistor 416, the second transistor 516, and the third transistor 616 are N type transistors, the adjust layer 318 is, for example, titanium (Ti). As shown in FIG. 4, it is characterized in the present embodiment that the adjust layer 318 has a first adjust layer 318 a in the first trench 416, which has a thinnest thickness, a second adjust layer 318 b in the second trench 516, which has a middle thickness, and a third adjust layer 318 c, which has a thickest thickness. In one preferred embodiment, the thickness of the first adjust layer 318 can be approximately zero.
  • The method for forming the adjust layer 318 with different thicknesses, for example, starts by forming an initial adjust layer (not shown) with uniform thickness in the first trench 416, the second trench 516 and the third trench 616. Next, a mask (not shown) is formed to cover the third trench 616, and an etching back process is carried out to remove a part of the initial adjust layer (not shown) in the second trench 516 and the third trench 616. Subsequently, another mask (not shown) is formed to further cover the second trench 516, followed by another etching process to further remove a part of the initial adjust layer (not shown) in the first trench 416. In one embodiment, the initial adjust layer (not shown) in the first trench 416 can be completely removed. In anther embodiment, the initial adjust layer (not shown) in the first trench 416 still remains a predetermined thickness. Lastly, all the masks are removed away. The adjust layer 318 having the first adjust layer 318 a, the second adjust layer 318 b and the third adjust layer 318 c with different thicknesses respectively in the first trench 416, the second trench 516 and the third trench 616 can be formed.
  • In another embodiment, the method for forming the adjust layer 318 with different thicknesses can include forming an initial adjust layer (not shown) with uniform thickness in the first trench 416, the second trench 516 and the third trench 616. Next, a mask (not shown) is formed to cover the first trench 416 and a deposition process is performed to thicken the initial adjust layer (not shown) in the second trench 516 and the third trench 616 not covered by the mask. Another mask (not shown) is formed to further cover the second trench 516, and another deposition process is performed to thicken the initial adjust layer (not shown) in the third trench 616. A planarization process and/or an etching process is performed to remove the mask layer and the above initial adjust layer, thereby forming the adjust layer 318 with different thicknesses. In another embodiment, when the first adjust layer 318 a has a zero of thickness, the method can start by directly forming a mask covering the first trench 416, and a deposition process is performed to form the initial adjust layer (not shown) in the second trench 516 and the third trench 616. Next, another mask (not shown) is formed for further covering the second trench 516, and a deposition to thicken the initial adjust layer in the third trench 616 is carried out. It is worth noting that the adjust layer 318 can also be formed by other methods and should not be limited to the above methods.
  • As shown in FIG. 5, an assisting layer 320 with uniform thickness is formed on the substrate 300, covering the adjust layer 318 in the first trench 416, the second trench 516 and the third trench 616. In one embodiment, the assisting layer 320 includes metal, preferably a nitride material of the adjust layer 318. For instance, when the adjust layer 318 is Ti, the assisting layer 320 can be TiN. The following context shows the embodiment of the adjust layer 318 containing Ti and the assisting layer 320 containing TiN.
  • As shown in FIG. 6, an annealing process is performed to inter-diffuse the adjust layer 318 and the assisting layer 320 to form a bottom barrier layer 322. The bottom barrier layer 322 has a first bottom barrier layer 322 a, a second bottom barrier layer 322 b and a third bottom barrier layer 322 c. The first bottom barrier layer 322 a disposed in the first trench 416 is formed by “the thinnest first adjust layer 318 a” and “uniform assisting layer 320”. The second bottom barrier layer 322 b disposed in the second trench 516 is formed by “the middle second adjust layer 318 b” and “uniform assisting layer 320”. The third bottom barrier layer 322 c disposed in the third trench 616 is formed by “the thickest third adjust layer 318 c” and “uniform assisting layer 320”.
  • It is understood that the first bottom barrier layer 322 a, the second bottom barrier layer 322 b and the third bottom barrier layer 322 c have different properties. In the view of thickness, the first bottom barrier layer 322 a is thinnest, the second bottom barrier layer 322 b is middle and the third barrier layer 322 c is thickest. In one embodiment, when the thickness of the first adjust layer 318 a is approximately zero, the final thickness of the first bottom barrier layer 322 a is equal to that of the assisting layer 320. In the view of the material compositions, a concentration of the material of the adjust layer 320 (Ti) is smallest with respect to the first bottom barrier layer 322 a, the ratio is middle in the second bottom barrier layer 322 b and the ratio is largest in the third bottom barrier layer 322 c. On the contrary, a concentration of the material of the assisting layer 322 (TiN) is largest with respect to the first bottom barrier layer 322 a, the ratio is middle in the second bottom barrier layer 322 b and the ratio is smallest in the third bottom barrier layer 322 c. In other words, a nitrogen concentration in the first bottom barrier layer 322 a>a nitrogen concentration in the second bottom barrier layer 322 b>a nitrogen concentration in the third bottom barrier layer 322 c; a titanium concentration in the first bottom barrier layer 322 a<a titanium concentration in the second bottom barrier layer 322 b<a titanium concentration in the third bottom barrier layer 322 c. The first bottom barrier layer 322 a is therefore “N rich”, and the third bottom barrier layer 322 c is “Ti rich.” As such, the first transistor 402, the second transistor 502 and the third transistor 602 can have different electrical performance.
  • The above embodiment shows forming the adjust layer 318 and then forming the assisting layer 320, so the formed bottom barrier layer 322 has a Ti concentration increasing from bottom to top (from a side of the substrate 300 to the opposite side) and a N concentration decreasing from bottom to top. In another embodiment, when first forming the uniform assisting layer 320 and then forming the adjust layer 318 with different thickness, the bottom barrier layer 322 has a Ti concentration decreasing from bottom to top and a N concentration increasing from bottom to top. In another embodiment, the adjust layer 318 can have uniform thickness while the assisting layer 320 can have different thickness. For example, the assisting layer 320 has a thickest portion in the first trench 416, a middle portion in the second trench 516 and a thinnest portion in the third trench 616. In another embodiment, one or more than one nitrogen treatment can be incorporated into the above steps, thereby forming the bottom barrier layer 322 with different nitrogen concentrations.
  • As shown in FIG. 7, an upper bottom barrier layer 324 is formed comprehensively on the substrate 300. In one embodiment, the upper bottom barrier layer 324 is formed along the surface of the first bottom barrier layer 322 a in the first trench 416, the second bottom barrier layer 322 b in the second trench 516 and the third bottom barrier layer 322 c in the third trench 616, but these trenches 416, 516, 616 are not completely filled with the upper bottom barrier layer 324. The upper bottom barrier 324 can include TaN or Ta/TaN. In one embodiment, it is a uniform layer.
  • In another embodiment, the upper bottom barrier layer 324 can have different thicknesses. As shown in FIG. 8, the upper bottom barrier layer 324 has a first upper bottom barrier layer 324 a in the first trench 416, which is thinnest, a second upper bottom barrier layer 324 b in the second trench 516, which is middle, and a third upper bottom barrier layer 324 c, which is thickest. In the method of forming the upper bottom layer 324 with different thickness, when the upper bottom barrier layer 324 includes TaN, the forming method thereof is similar to that for forming adjust layer 320; when the upper bottom barrier layer 324 comprises Ta/TaN, the forming method thereof is similar to the method for forming the bottom barrier layer 322. In one embodiment, a nitrogen concentration in the first upper bottom barrier layer 324 a>a nitrogen concentration in the second upper bottom barrier layer 324 b>a nitrogen concentration in the third upper bottom barrier layer 324 c. Alternatively, a tantalum concentration in the first upper bottom barrier layer 324 a<a tantalum concentration in the second upper bottom barrier layer 324 b>a tantalum concentration in the third upper bottom barrier layer 324 c.
  • As shown in FIG. 9, a work function metal (WFM) layer 326, a top barrier layer 326 and a metal layer 330 are sequentially formed on the substrate 300 to completely fill the first trench 416, the second trench 516 and the third trench 616. In one embodiment, when the first transistor 402, the second transistor 502 and the third transistor 602 are N type transistors, the WFM layer 326 can include titanium aluminides (TiAl), aluminum zirconium (ZrAl), aluminum tungsten (WAl), aluminum tantalum (TaAl) or aluminum hafnium (HfAl), but should not be limited thereto. When the first transistor 402, the second transistor 502 and the third transistor 602 are P type transistors, the WFM layer 326 can include Ni, Pd, Pt, Be, Ir, Te, Re, Ru, Rh, W, Mo, or WN, RuN, MoN, TiN, TaN, or WC, TaC, TiC, or TiAlN, TaAlN, but should not be limited thereto. The top barrier layer 328 can include TiN, TiAlC, TiAlN, TaN, TaAlC, TaAlN, TiCuC, TiCuN, TaCuC or TaCuN, but is not limited thereto. In one embodiment, the top barrier layer 328 can be omitted. The metal layer 330 includes Al, Ti, Ta, W, Nb, Mo, TiN, TiC, TaN, Ti/W or Ti/TiN, but is not limited thereto.
  • As shown in FIG. 10, a planarization process is performed to simultaneously remove the metal layer 330, the top barrier layer 328, the WFM layer 326, the upper bottom barrier layer 324 and the bottom barrier layer 322 outside of the first trench 416, the second trench 516 and the third trench 616. Thus, the first etch stop layer 407, the first bottom barrier layer 322 a, the upper bottom barrier layer (or the first bottom barrier layer 324 a), the WFM layer 326 (the first WFM layer 326 a herein), the top barrier layer 328 (the first top barrier layer 328 a herein) and the metal layer 330 (the first metal layer 330 a herein) together form a first metal gate 418 of the first transistor 402. The second etch stop layer 507, the second bottom barrier layer 322 b, the upper bottom barrier layer 324 (or the second bottom barrier layer 324 b), the WFM layer 326 (the second WFM layer 326 b herein), the top barrier layer 328 (the second top barrier layer 328 b herein) and the metal layer 330 (the second metal layer 330 b herein) together forma second metal gate 518 of the second transistor 502. The third etch stop layer 607, the third bottom barrier layer 322 c, the upper bottom barrier layer 324 (or the third bottom barrier layer 324 c), the WFM layer 326 (the third WFM layer 326 c herein), the top barrier layer 328 (the third top barrier layer 328 c herein) and the metal layer 330 (the third metal layer 330 c herein) together form a third metal gate 618 in the third transistor 602.
  • Since the first transistor 402, the second transistor 502 and the third transistor 602 have the bottom barrier layer 322 with different thickness and different compositions, they can exhibit different electrical performance. In detail, the first transistor 402 has the largest threshold voltage, the second transistor 502 has the middle one and the third transistor 602 has the smallest one. In one embodiment, the threshold voltage of the first transistor 402 is about 0.3V to 0.6V; the threshold voltage of the second transistor 502 is about 0.2V to 0.3V; the threshold voltage of the third transistor 602 is about 0.1V to 0.2V.
  • It should be noted that the above method shown in a gate-last process can also be applied in a gate-first process. Besides, the above method shows forming the high-k gate dielectric layer before removing the sacrificial gate (namely, the high-k first process). However, those skilled in the art can realize that, in the present invention, it is also possible to form the high-k layer after removing the sacrificial gate (namely, the high-k last process). In addition, when the invention is performed in the high-k last process, the material of the dielectric layer formed under the sacrificial gate is not limited to high-k material but can also include another dielectric material such as SiO2. In another embodiment, the first transistor 402, the second transistor 502 and the third transistor 602 can be non-planar transistors such as Fin-FET and is not limited to the planar transistor shown above.
  • In summary, the present invention provides a structure having plural transistors and the forming method. It is featured that the formed transistors have bottom barrier layers with different thickness and/or composition, thereby tuning the electrical performance of the transistors and providing them with different threshold voltages.
  • Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims (20)

1. An integrated circuit having plural transistors with different threshold voltages, comprising:
a substrate;
a first transistor with a first metal gate disposed on the substrate, wherein the first metal gate comprises a first bottom barrier layer, a first work function metal (WFM) layer and a first metal layer;
a second transistor with a second metal gate disposed on the substrate, wherein the second metal gate comprises a second bottom barrier layer, a second WFM layer and a second metal layer; and
a third transistor with a third metal gate disposed on the substrate, wherein the third metal gate comprises a third bottom barrier layer, a third WFM layer and a third metal layer, wherein the first transistor, the second transistor and the third transistor have the same conductive type, and a nitrogen concentration of the first bottom barrier layer>a nitrogen concentration of the second bottom barrier layer>a nitrogen concentration of the third bottom barrier layer.
2. The integrated circuit according to claim 1, wherein a titanium concentration of the first bottom barrier layer<a titanium concentration of the second bottom barrier layer<a titanium concentration of the third bottom barrier layer.
3. The integrated circuit according to claim 1, wherein a thickness of the first bottom barrier layer<a thickness of the second bottom barrier layer<a thickness of the third bottom barrier layer.
4. The integrated circuit according to claim 1, wherein a threshold voltage of the first transistor>a threshold voltage of the second transistor>a threshold voltage of the third transistor.
5. The integrated circuit according to claim 1, wherein the nitrogen concentration in the first bottom barrier layer, the nitrogen concentration in the second bottom barrier layer, and the nitrogen concentration in the third bottom barrier layer increase from a side near the substrate toward a side far from the substrate.
6. The integrated circuit according to claim 1, wherein the nitrogen concentration of the first bottom barrier layer, the nitrogen concentration of the second bottom barrier layer, and the nitrogen concentration of the third bottom barrier layer decrease from a side near the substrate toward a side far from the substrate.
7. The integrated circuit according to claim 1, wherein the first transistor, the second transistor and the third transistor are N type transistors.
8. The integrated circuit according to claim 1, wherein,
the first transistor further comprises a first upper bottom barrier layer disposed between the first bottom barrier layer and the first WFM layer;
the second transistor further comprises a second upper bottom barrier layer disposed between the second bottom barrier layer and the second WFM layer; and
the third transistor further comprises a third upper bottom barrier layer disposed between the third bottom barrier layer and the third WFM layer, wherein a nitrogen concentration of the first upper bottom barrier layer>a nitrogen concentration of the second upper bottom barrier layer>a nitrogen concentration of the third upper bottom barrier layer.
9. The integrated circuit according to claim 8, wherein a tantalum concentration of the first upper bottom barrier layer<a tantalum concentration of the second upper bottom barrier layer>a tantalum concentration of the third upper bottom barrier layer.
10. A method of forming an integrated circuit which has plural transistors with different threshold voltages, comprising:
providing a dielectric layer having a first trench, a second trench and a third trench;
forming a bottom barrier layer on the dielectric layer, wherein the bottom barrier layer comprises a first bottom barrier layer in the first trench, a second bottom barrier layer in the second trench and a third bottom barrier layer of the third trench, wherein a nitrogen concentration of the first bottom barrier layer>a nitrogen concentration of the second bottom barrier layer>a nitrogen concentration of the third bottom barrier layer;
forming a work function metal (WFM) layer on the bottom barrier layer in the first trench, the second trench and the third trench; and
forming a metal layer on the WFM layer, wherein the first trench, the second trench and the third trench are completely filled with the metal layer.
11. The method of forming an integrated circuit according to claim 10, wherein the step of forming the bottom barrier layer comprises:
forming an adjust layer on the dielectric layer, wherein the adjust layer comprises a first adjust layer in the first trench, a second adjust layer in the second trench and a third adjust layer in the third trench, wherein a thickness of the first adjust layer<a thickness of the second adjust layer<a thickness of the third adjust layer;
forming an assisting layer in the first trench, the second trench and the third trench; and
performing an annealing process.
12. The method of forming an integrated circuit according to claim 11, wherein forming the adjust layer, then forming the assisting layer.
13. The method of forming an integrated circuit according to claim 11, wherein forming the assisting layer, then forming the adjust layer.
14. The method of forming an integrated circuit according to claim 11, wherein the assisting layer in the first trench, the second trench and the third trench has the same thickness.
15. The method of forming an integrated circuit according to claim 11, wherein the assisting layer in the first trench, the second trench and the third trench has different thicknesses.
16. The method of forming an integrated circuit according to claim 11, wherein a thickness of the first bottom barrier layer is substantially zero.
17. The method of forming an integrated circuit according to claim 10, wherein after forming the bottom barrier layer and before forming the WFM layer, further comprising:
forming an upper bottom barrier layer on the bottom barrier layer, wherein the upper bottom barrier layer comprises a first upper bottom barrier layer in the first trench, a second upper bottom barrier layer in the second trench and a third upper barrier layer in the third trench.
18. The method of forming an integrated circuit according to claim 17, wherein a nitrogen concentration of the first upper bottom barrier layer>a nitrogen concentration of the second upper bottom barrier layer>a nitrogen concentration of the third upper bottom barrier layer.
19. The method of forming an integrated circuit according to claim 17, wherein a tantalum concentration of the first upper bottom barrier layer<a tantalum concentration of the second upper bottom barrier layer>a tantalum concentration of the third upper bottom barrier layer.
20. The method of forming an integrated circuit according to claim 10, wherein the WFM layer comprises N type WFM layer.
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