+

US20150255576A1 - Semiconductor device and method for fabricating the same - Google Patents

Semiconductor device and method for fabricating the same Download PDF

Info

Publication number
US20150255576A1
US20150255576A1 US14/201,373 US201414201373A US2015255576A1 US 20150255576 A1 US20150255576 A1 US 20150255576A1 US 201414201373 A US201414201373 A US 201414201373A US 2015255576 A1 US2015255576 A1 US 2015255576A1
Authority
US
United States
Prior art keywords
spacer
shovel
fin structure
sidewall
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US14/201,373
Other versions
US9123744B1 (en
Inventor
Chin-I Liao
Sheng-Hsu Liu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
United Microelectronics Corp
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to US14/201,373 priority Critical patent/US9123744B1/en
Assigned to UNITED MICROELECTRONICS CORP. reassignment UNITED MICROELECTRONICS CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LIAO, CHIN-I, LIU, SHENG-HSU
Application granted granted Critical
Publication of US9123744B1 publication Critical patent/US9123744B1/en
Publication of US20150255576A1 publication Critical patent/US20150255576A1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H01L29/66553—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H01L29/16—
    • H01L29/161—
    • H01L29/24—
    • H01L29/6653—
    • H01L29/66795—
    • H01L29/7851—
    • H01L29/7853—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain

Definitions

  • This invention relates to a semiconductor process and a product thereof, and particularly relates to a method for fabricating a semiconductor device, and to a semiconductor device and a structure of a semiconductor layer made by the method.
  • a FinFET typically includes a semiconductor fin, a gate crossing over the fin to form a tri-gate structure, and a source and a drain beside the portion of the fin under the gate.
  • the portions of the fin not under the gate are recessed after the gate is formed, and a semiconductor compound having a lattice parameter different from that of the material of the fin is grown based on the recessed portions of the fin to serve as a source and a drain.
  • the top of the recessed fin is near the isolation layer, so the semiconductor compound layer easily touches the isolation layer and becomes asymmetric.
  • the semiconductor compound layer includes silicon-phosphorus (SiP) and SiP is deposited in the epitaxy process, many dislocations in ⁇ 111> direction occur due to competition of phosphorus and chlorine in the epitaxy process. Hence, there is concern on issues of device degradation, drain-induced barrier lowering (DIBL), self-aligned contact (SAC) and so on.
  • DIBL drain-induced barrier lowering
  • SAC self-aligned contact
  • this invention provides a method for fabricating a semiconductor device, which is capable of preventing the above problems.
  • This invention also provides a semiconductor device fabricated by the method.
  • This invention also provides a structure of a semiconductor layer formed by the method.
  • a spacer is formed on a sidewall of a fin structure.
  • a portion of the fin structure is removed to form a cavity exposing at least a portion of the inner sidewall of the spacer.
  • An epitaxy process is performed based on the remaining fin structure to form thereon a semiconductor layer that has a shovel-shaped cross section including: a stem portion in the cavity, and a shovel plane portion contiguous with the stem portion.
  • the reaction gas introduced in the epitaxy process contains a silicon source gas for Si epitaxy.
  • the reaction gas may further contain a phosphorus source gas or a germanium source gas for SiP epitaxy or SiGe epitaxy.
  • the semiconductor device of this invention includes a fin structure, a spacer and a semiconductor layer.
  • the spacer is at both sides of the fin structure, and defines a cavity together with the fin structure.
  • the semiconductor layer is on the fin structure, and has a shovel-shaped cross section including: a stem portion in the cavity and connected with the fin, and a shovel plane portion contiguous with the stem portion.
  • the shovel plane portion covers a portion of the sidewall of the spacer.
  • the structure of a semiconductor layer of this invention has a shovel-shaped cross section including: a stem portion, and a shovel plane portion being contiguous with the stem portion and defining a spade shape together with the stem portion.
  • the semiconductor layer does not easily touch the isolation layer and hence becomes more symmetric.
  • the semiconductor layer includes SiP and SiP is deposited in the epitaxy process, the growth of (110) and (111) surfaces of silicon are blocked by the spacer at an initial stage of the epitaxy, so that a dislocation in ⁇ 111> direction does not easily occur. As a result, the concern on issues of device degradation, DIBL, SAC and so on can be reduced.
  • FIGS. 1 , 2 , 3 and 4 A/ 4 B schematically illustrate, in a perspective view ( FIGS. 1 and 2 ) or an A-A′ cross-sectional view (FIGS. 3 and 4 A/ 4 B), a method for fabricating a semiconductor device according to an embodiment of this invention, wherein FIG. 4A or 4 B illustrates the resulting semiconductor device in a case where the shovel plane portion of the semiconductor layer covers or does not cover a portion of a sidewall of the spacer.
  • FIG. 5 is a locally magnified view of the structure in FIG. 4 A/B.
  • the semiconductor fin structure is connected to a semiconductor substrate below the isolation layer
  • the fin structure may not be connected to a semiconductor substrate below the isolation layer in other embodiments, e.g., an embodiment where the fin is defined from a SOI substrate.
  • FIGS. 1 , 2 , 3 and 4 A/ 4 B schematically illustrate, in a perspective view ( FIGS. 1 and 2 ) or an A-A′ cross-sectional view (FIGS. 3 and 4 A/ 4 B), a method for fabricating a semiconductor device according to an embodiment of this invention, wherein FIG. 4 A/ 4 B also illustrates the resulting semiconductor device.
  • a semiconductor substrate 10 such as a single-crystal silicon substrate or an epitaxial silicon substrate, is provided, and a fin structure 10 a is defined from a surface part of the substrate 10 .
  • An isolation layer 12 such as a shallow trench isolation (STI) layer, is then fowled on the recessed substrate 10 sandwiching a lower portion of the fin structure 10 a.
  • a gate dielectric 14 which may include silicon oxide, is formed on the surface of fin structure 10 a, and then a gate conductor 16 is formed crossing over the fin structure 10 a with the gate dielectric 14 therebetween.
  • a cap layer 18 which is defined by the same mask layer for defining the gate conductor 16 , is usually disposed on the gate conductor 16 .
  • the gate conductor 16 may include poly-Si.
  • the cap layer 18 may include silicon nitride (SiN).
  • the spacer material layer 20 may include SiN.
  • anisotropic etching is performed to the spacer material layer 20 to form a first spacer 20 a on the sidewall of the gate conductor 16 and a second spacer 20 b on the sidewall of the fin structure 10 a.
  • a portion of the sidewall of the fin structure 10 a may be exposed outside of the spacer 20 b in consideration of the desired height of the fin structure 10 a above the isolation layer 12 and the desired height of the spacer 20 b.
  • the height of the spacer 20 b substantially determines the position of the shovel plane portion of the shovel-shaped cross section of the semiconductor layer formed in the epitaxy process later, and is preferably larger than 80 ⁇ .
  • a portion of the fin structure 10 a is removed to form a cavity 21 exposing a portion of an inner sidewall of the spacer 20 b. That is, the cavity 21 is defined by the remaining fin structure 10 b and the spacer 20 b.
  • the removal may utilize anisotropic etching or wet etching.
  • an epitaxy process is performed based on the remaining fin structure 10 b to form a semiconductor layer 22 .
  • the reaction gas introduced in the epitaxy process may contains a Si source gas for Si epitaxy, and may further contain a phosphorus source gas for SiP epitaxy, or a germanium source gas for SiGe epitaxy.
  • the silicon source gas may be selected from the group consisting of dichlorosilane (DCS) and SiH 4 .
  • the phosphorus source gas may be PH 3 .
  • the germanium source gas may be GeH 4 .
  • the semiconductor layer 22 may include Si, SiP or SiGe.
  • the temperature of the epitaxy process is usually higher than 500° C., preferably in the range of 675 to 725° C.
  • the pressure of the epitaxy process is usually higher than 10 torr, preferably in the range of 275 to 325 torr.
  • DCS is used as the silicon source gas
  • the flow rate of DCS is preferably in the range of 100 to 200 sccm.
  • the flow rate of PH 3 is preferably in the range of 300 to 500 sccm.
  • a carrier gas such as H 2
  • An etching gas such as HCl
  • the flow rate of HCl is preferably in the range of 50 to 90 sccm.
  • the cross section of the semiconductor layer 22 has a shovel shape, and includes a stem portion 22 b in the cavity 21 and connected with the fin structure 10 b, and a shovel plane portion 22 a on and contiguous with the stem portion 22 b.
  • the shovel plane portion 22 a may extend to cover a portion of the sidewall of the spacer 20 b and define a spade shape together with the stem portion, as shown in FIG. 4A .
  • the shovel plane portion 22 a does not cover a portion of the sidewall of the spacer 20 b and has a nearly rhombus shape, as shown in FIG. 4B .
  • the height of the entire semiconductor layer 22 may be within the range of 250 to 450 ⁇ . More details of the structure of the semiconductor layer 22 are described below, in reference of FIG. 5 as a locally magnified view of the structure in FIG. 4 A/ 4 B.
  • the shovel plane portion 22 a has an upper sidewall 221 facing up, and a lower sidewall 222 facing down and connected with the upper sidewall 221 .
  • the ratio of the length D 2 of the lower sidewall 222 to the length D 1 of the upper sidewall 221 is larger than 0.3:1, for example.
  • the ratio of the height D 4 of the stem portion 22 b to the height D 3 of the shovel plane portion 22 a may be within the range of 0.1 to 1.
  • the shovel plane portion 22 a has a turning region around the top of the spacer 20 b and near the spacer 20 b, and the turning region has a turning angle ⁇ within the range of 25 to 120 degrees.
  • the semiconductor layer does not easily touch the isolation layer and hence becomes more symmetric.
  • the semiconductor layer includes SiP and SiP is deposited in the epitaxy process, the growth of (110) and (111) surfaces of silicon are blocked by the spacer at an initial stage of the epitaxy, so that a dislocation in ⁇ 111> direction does not easily occur.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

A method for fabricating a semiconductor device is described. A spacer is formed on a sidewall of a fin structure. A portion of the fin structure is removed to form a cavity exposing at least a portion of the inner sidewall of the spacer. An epitaxy process is performed based on the remaining fin structure to form a semiconductor layer that has a shovel-shaped cross section including: a stem portion in the cavity, and a shovel plane portion contiguous with the stem portion. A semiconductor device is also described, which includes the spacer, the remaining fin structure and the semiconductor layer that are mentioned above.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of Invention
  • This invention relates to a semiconductor process and a product thereof, and particularly relates to a method for fabricating a semiconductor device, and to a semiconductor device and a structure of a semiconductor layer made by the method.
  • 2. Description of Related Art
  • A FinFET typically includes a semiconductor fin, a gate crossing over the fin to form a tri-gate structure, and a source and a drain beside the portion of the fin under the gate. In a strained silicon process applied to FinFET, the portions of the fin not under the gate are recessed after the gate is formed, and a semiconductor compound having a lattice parameter different from that of the material of the fin is grown based on the recessed portions of the fin to serve as a source and a drain.
  • Because the fin structure usually protrudes from the isolation layer, the top of the recessed fin is near the isolation layer, so the semiconductor compound layer easily touches the isolation layer and becomes asymmetric.
  • Moreover, when the semiconductor compound layer includes silicon-phosphorus (SiP) and SiP is deposited in the epitaxy process, many dislocations in <111> direction occur due to competition of phosphorus and chlorine in the epitaxy process. Hence, there is concern on issues of device degradation, drain-induced barrier lowering (DIBL), self-aligned contact (SAC) and so on.
    • SUMMARY OF THE INVENTION
  • Accordingly, this invention provides a method for fabricating a semiconductor device, which is capable of preventing the above problems.
  • This invention also provides a semiconductor device fabricated by the method.
  • This invention also provides a structure of a semiconductor layer formed by the method.
  • The method for fabricating a semiconductor device of this invention is described below. A spacer is formed on a sidewall of a fin structure. A portion of the fin structure is removed to form a cavity exposing at least a portion of the inner sidewall of the spacer. An epitaxy process is performed based on the remaining fin structure to form thereon a semiconductor layer that has a shovel-shaped cross section including: a stem portion in the cavity, and a shovel plane portion contiguous with the stem portion.
  • In an embodiment, the reaction gas introduced in the epitaxy process contains a silicon source gas for Si epitaxy. The reaction gas may further contain a phosphorus source gas or a germanium source gas for SiP epitaxy or SiGe epitaxy.
  • The semiconductor device of this invention includes a fin structure, a spacer and a semiconductor layer. The spacer is at both sides of the fin structure, and defines a cavity together with the fin structure. The semiconductor layer is on the fin structure, and has a shovel-shaped cross section including: a stem portion in the cavity and connected with the fin, and a shovel plane portion contiguous with the stem portion.
  • In some embodiments, the shovel plane portion covers a portion of the sidewall of the spacer.
  • The structure of a semiconductor layer of this invention has a shovel-shaped cross section including: a stem portion, and a shovel plane portion being contiguous with the stem portion and defining a spade shape together with the stem portion.
  • Because the fin structure and the epitaxial growth of the semiconductor layer can be spaced from the isolation layer by the spacer in the method for fabricating a semiconductor device of this invention, the semiconductor layer does not easily touch the isolation layer and hence becomes more symmetric.
  • Moreover, when the semiconductor layer includes SiP and SiP is deposited in the epitaxy process, the growth of (110) and (111) surfaces of silicon are blocked by the spacer at an initial stage of the epitaxy, so that a dislocation in <111> direction does not easily occur. As a result, the concern on issues of device degradation, DIBL, SAC and so on can be reduced.
  • In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, a preferred embodiment accompanied with figures is described in detail below.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGS. 1, 2, 3 and 4A/4B schematically illustrate, in a perspective view (FIGS. 1 and 2) or an A-A′ cross-sectional view (FIGS. 3 and 4A/4B), a method for fabricating a semiconductor device according to an embodiment of this invention, wherein FIG. 4A or 4B illustrates the resulting semiconductor device in a case where the shovel plane portion of the semiconductor layer covers or does not cover a portion of a sidewall of the spacer.
  • FIG. 5 is a locally magnified view of the structure in FIG. 4A/B.
    •  DESCRIPTION OF EMBODIMENTS
  • This invention will be further explained with the following embodiment and the accompanying drawings, which are not intended to restrict the scope of this invention. For example, although in the following embodiment the semiconductor fin structure is connected to a semiconductor substrate below the isolation layer, the fin structure may not be connected to a semiconductor substrate below the isolation layer in other embodiments, e.g., an embodiment where the fin is defined from a SOI substrate.
  • FIGS. 1, 2, 3 and 4A/4B schematically illustrate, in a perspective view (FIGS. 1 and 2) or an A-A′ cross-sectional view (FIGS. 3 and 4A/4B), a method for fabricating a semiconductor device according to an embodiment of this invention, wherein FIG. 4A/4B also illustrates the resulting semiconductor device.
  • Referring to FIG. 1, a semiconductor substrate 10, such as a single-crystal silicon substrate or an epitaxial silicon substrate, is provided, and a fin structure 10 a is defined from a surface part of the substrate 10. An isolation layer 12, such as a shallow trench isolation (STI) layer, is then fowled on the recessed substrate 10 sandwiching a lower portion of the fin structure 10 a. A gate dielectric 14, which may include silicon oxide, is formed on the surface of fin structure 10 a, and then a gate conductor 16 is formed crossing over the fin structure 10 a with the gate dielectric 14 therebetween. A cap layer 18, which is defined by the same mask layer for defining the gate conductor 16, is usually disposed on the gate conductor 16. The gate conductor 16 may include poly-Si. The cap layer 18 may include silicon nitride (SiN).
  • Thereafter, a substantially conformal spacer material layer 20 is formed over the resulting structure. The spacer material layer 20 may include SiN.
  • Referring to FIG. 2, anisotropic etching is performed to the spacer material layer 20 to form a first spacer 20 a on the sidewall of the gate conductor 16 and a second spacer 20 b on the sidewall of the fin structure 10 a. A portion of the sidewall of the fin structure 10 a may be exposed outside of the spacer 20 b in consideration of the desired height of the fin structure 10 a above the isolation layer 12 and the desired height of the spacer 20 b. The height of the spacer 20 b substantially determines the position of the shovel plane portion of the shovel-shaped cross section of the semiconductor layer formed in the epitaxy process later, and is preferably larger than 80 Å.
  • Referring to FIG. 3 in the A-A′ cross-sectional view of FIG. 2, a portion of the fin structure 10 a is removed to form a cavity 21 exposing a portion of an inner sidewall of the spacer 20 b. That is, the cavity 21 is defined by the remaining fin structure 10 b and the spacer 20 b. The removal may utilize anisotropic etching or wet etching.
  • Referring to FIG. 4A/B, an epitaxy process is performed based on the remaining fin structure 10 b to form a semiconductor layer 22. The reaction gas introduced in the epitaxy process may contains a Si source gas for Si epitaxy, and may further contain a phosphorus source gas for SiP epitaxy, or a germanium source gas for SiGe epitaxy.
  • The silicon source gas may be selected from the group consisting of dichlorosilane (DCS) and SiH4. The phosphorus source gas may be PH3. The germanium source gas may be GeH4. Accordingly, the semiconductor layer 22 may include Si, SiP or SiGe. The temperature of the epitaxy process is usually higher than 500° C., preferably in the range of 675 to 725° C. The pressure of the epitaxy process is usually higher than 10 torr, preferably in the range of 275 to 325 torr. When DCS is used as the silicon source gas, the flow rate of DCS is preferably in the range of 100 to 200 sccm. When PH3 is used as the phosphorus source gas, the flow rate of PH3 is preferably in the range of 300 to 500 sccm.
  • In addition, a carrier gas, such as H2, may also be introduced in the epitaxy process. An etching gas, such as HCl, may also be introduced in the epitaxy process to improve the selectivity of the epitaxy process. When HCl is used as the etching gas, the flow rate of HCl is preferably in the range of 50 to 90 sccm.
  • Referring to FIG. 4A/4B again, the cross section of the semiconductor layer 22 has a shovel shape, and includes a stem portion 22 b in the cavity 21 and connected with the fin structure 10 b, and a shovel plane portion 22 a on and contiguous with the stem portion 22 b. The shovel plane portion 22 a may extend to cover a portion of the sidewall of the spacer 20 b and define a spade shape together with the stem portion, as shown in FIG. 4A. Alternatively, the shovel plane portion 22 a does not cover a portion of the sidewall of the spacer 20 b and has a nearly rhombus shape, as shown in FIG. 4B. The height of the entire semiconductor layer 22 may be within the range of 250 to 450 Å. More details of the structure of the semiconductor layer 22 are described below, in reference of FIG. 5 as a locally magnified view of the structure in FIG. 4A/4B.
  • Referring to FIG. 5, the shovel plane portion 22 a has an upper sidewall 221 facing up, and a lower sidewall 222 facing down and connected with the upper sidewall 221. The ratio of the length D2 of the lower sidewall 222 to the length D1 of the upper sidewall 221 is larger than 0.3:1, for example.
  • In addition, the ratio of the height D4 of the stem portion 22 b to the height D3 of the shovel plane portion 22 a may be within the range of 0.1 to 1. The shovel plane portion 22 a has a turning region around the top of the spacer 20 b and near the spacer 20 b, and the turning region has a turning angle θ within the range of 25 to 120 degrees.
  • Because the fin structure and the epitaxial growth of the semiconductor layer is spaced from the isolation layer by the spacer in this invention, the semiconductor layer does not easily touch the isolation layer and hence becomes more symmetric.
  • Moreover, when the semiconductor layer includes SiP and SiP is deposited in the epitaxy process, the growth of (110) and (111) surfaces of silicon are blocked by the spacer at an initial stage of the epitaxy, so that a dislocation in <111> direction does not easily occur.
  • This invention has been disclosed above in the preferred embodiments, but is not limited to those. It is known to persons skilled in the art that some modifications and innovations may be made without departing from the spirit and scope of this invention. Hence, the scope of this invention should be defined by the following claims.

Claims (21)

1. A method for fabricating a semiconductor device, comprising:
forming an isolation layer at both sides of a fin structure;
forming a spacer on a sidewall of the fin structure and on a top of the isolation layer, wherein the spacer covers only a portion of a top surface of the isolation layer;
removing a portion of the fin structure to form a cavity exposing at least a portion of an inner sidewall of the spacer; and
performing an epitaxy process based on the remaining fin structure to form thereon a semiconductor layer that has a shovel-shaped cross section including: a stem portion in the cavity, and a shovel plane portion contiguous with the stem portion.
2. The method of claim 1, wherein a reaction gas introduced in the epitaxy process comprises a silicon source gas.
3. The method of claim 2, wherein the reaction gas further comprises a phosphorus source gas or a germanium source gas.
4. The method of claim 2, wherein a temperature of the epitaxy process is higher than 500° C.
5. The method of claim 2, wherein a pressure of the epitaxy process is higher than 10 torr.
6. The method of claim 1, wherein a height of the spacer is larger than 80 Å.
7. The method of claim 1, wherein the semiconductor layer comprises Si, SiP or SiGe.
8. The method of claim 1, wherein the spacer comprises SiN.
9. A semiconductor device, comprising:
a fin structure;
an isolation layer at both sides of the fin structure;
a spacer at both sides of the fin structure and on a top of the isolation layer, defining a cavity together with the fin structure, wherein the spacer covers only a portion of a top surface of the isolation layer; and
a semiconductor layer on the fin structure, having a shovel-shaped cross section including:
a stem portion in the cavity and connected with the fin structure, and
a shovel plane portion contiguous with the stem portion.
10. The semiconductor device of claim 9, wherein a height of the semiconductor layer is within a range of 250 to 450 Å.
11. The semiconductor device of claim 9, wherein a height ratio of the stem portion to the shovel plane portion is within a range of 0.1 to 1.
12. The semiconductor device of claim 9, wherein the shovel plane portion has an upper sidewall facing up, and a lower sidewall facing down and connected with the upper sidewall, and a length ratio of the lower sidewall to the upper sidewall is larger than 0.3:1.
13. The semiconductor device of claim 9, wherein the shovel plane portion has, around a top of the spacer, a turning angle within a range of 25 to 120 degrees.
14. The semiconductor device of claim 13, wherein the shovel plane portion covers a portion of a sidewall of the spacer.
15. The semiconductor device of claim 9, wherein the semiconductor layer comprises Si, SiP or SiGe.
16. A structure of a semiconductor layer, having a shovel-shaped cross section including:
a stem portion, and
a shovel plane portion contiguous with the stem portion, defining a spade shape together with the stem portion,
wherein the shovel plane portion covers a portion of a sidewall of a spacer, wherein the spacer is on a sidewall of the stem portion and on a top of an isolation layer, and the spacer covers only a portion of a top surface of the isolation layer.
17. The structure of claim 16, wherein a height of the semiconductor layer is within a range of 250 to 450 Å.
18. The structure of claim 16, wherein a height ratio of the stem portion to the shovel plane portion is within a range of 0.1 to 1.
19. The structure of claim 16, wherein the shovel plane portion has an upper sidewall facing up, and a lower sidewall facing down and connected with the upper sidewall, and a length ratio of the lower sidewall to the upper sidewall is larger than 0.3:1.
20. The structure of claim 16, wherein the shovel plane portion has a turning region near the stem portion, and the turning region has a turning angle within a range of 25 to 120 degrees.
21. The structure of claim 16, wherein the semiconductor layer comprises Si, SiP or SiGe.
US14/201,373 2014-03-07 2014-03-07 Semiconductor device and method for fabricating the same Active US9123744B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/201,373 US9123744B1 (en) 2014-03-07 2014-03-07 Semiconductor device and method for fabricating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14/201,373 US9123744B1 (en) 2014-03-07 2014-03-07 Semiconductor device and method for fabricating the same

Publications (2)

Publication Number Publication Date
US9123744B1 US9123744B1 (en) 2015-09-01
US20150255576A1 true US20150255576A1 (en) 2015-09-10

Family

ID=53938971

Family Applications (1)

Application Number Title Priority Date Filing Date
US14/201,373 Active US9123744B1 (en) 2014-03-07 2014-03-07 Semiconductor device and method for fabricating the same

Country Status (1)

Country Link
US (1) US9123744B1 (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9443769B2 (en) 2014-04-21 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Wrap-around contact
US9502507B1 (en) * 2016-02-01 2016-11-22 Globalfoundries Inc. Methods of forming strained channel regions on FinFET devices
US9508848B1 (en) 2016-02-01 2016-11-29 Globalfoundries Inc. Methods of forming strained channel regions on FinFET devices by performing a heating process on a heat-expandable material
US9653605B2 (en) * 2014-10-17 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Fin field effect transistor (FinFET) device and method for forming the same
US20170243868A1 (en) * 2016-02-23 2017-08-24 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and Method for Semiconductor Device
US20170309624A1 (en) * 2016-04-25 2017-10-26 Taiwan Semiconductor Manufacturing Company, Ltd. Finfets and methods of forming finfets
US9853154B2 (en) * 2014-01-24 2017-12-26 Taiwan Semiconductor Manufacturing Company Ltd. Embedded source or drain region of transistor with downward tapered region under facet region
US9865495B2 (en) 2015-11-05 2018-01-09 Samsung Electronics Co., Ltd. Semiconductor device and method for fabricating the same

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150372107A1 (en) * 2014-06-18 2015-12-24 Stmicroelectronics, Inc. Semiconductor devices having fins, and methods of forming semiconductor devices having fins
US9391200B2 (en) * 2014-06-18 2016-07-12 Stmicroelectronics, Inc. FinFETs having strained channels, and methods of fabricating finFETs having strained channels
US20160005868A1 (en) * 2014-07-01 2016-01-07 Globalfoundries Inc. Finfet with confined epitaxy
US9472470B2 (en) * 2014-12-09 2016-10-18 GlobalFoundries, Inc. Methods of forming FinFET with wide unmerged source drain EPI
US9406752B2 (en) * 2014-12-29 2016-08-02 Globalfoundries Inc. FinFET conformal junction and high EPI surface dopant concentration method and device
US9397162B1 (en) * 2014-12-29 2016-07-19 Globalfoundries Inc. FinFET conformal junction and abrupt junction with reduced damage method and device
KR102336787B1 (en) * 2015-08-11 2021-12-07 삼성전자주식회사 Semiconductor device
US9620644B2 (en) * 2015-09-02 2017-04-11 International Business Machines Corporation Composite spacer enabling uniform doping in recessed fin devices
US9780218B1 (en) 2016-05-02 2017-10-03 United Microelectronics Corp. Bottom-up epitaxy growth on air-gap buffer
CN107546127B (en) * 2016-06-28 2022-06-21 联华电子股份有限公司 Semiconductor device and method of making the same
US10290738B2 (en) 2017-04-10 2019-05-14 Globalfoundries Inc. Methods of forming epi semiconductor material on a recessed fin in the source/drain regions of a FinFET device
US10121868B1 (en) 2017-05-03 2018-11-06 Globalfoundries Inc. Methods of forming epi semiconductor material on a thinned fin in the source/drain regions of a FinFET device
US9887094B1 (en) * 2017-05-03 2018-02-06 Globalfoundries Inc. Methods of forming EPI semiconductor material on the source/drain regions of a FinFET device
US10243079B2 (en) 2017-06-30 2019-03-26 International Business Machines Corporation Utilizing multilayer gate spacer to reduce erosion of semiconductor fin during spacer patterning
US10269932B1 (en) 2018-01-18 2019-04-23 Globalfoundries Inc. Asymmetric formation of epi semiconductor material in source/drain regions of FinFET devices
KR102422241B1 (en) 2018-02-06 2022-07-18 삼성전자주식회사 Semiconductor devices having source/drain regions

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150048453A1 (en) * 2013-07-03 2015-02-19 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs and Methods for Forming the Same

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080003755A1 (en) 2006-06-30 2008-01-03 Uday Shah Sacrificial oxide layer which enables spacer over-etch in tri-gate architectures
US8962433B2 (en) 2012-06-12 2015-02-24 United Microelectronics Corp. MOS transistor process

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150048453A1 (en) * 2013-07-03 2015-02-19 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs and Methods for Forming the Same

Cited By (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9853154B2 (en) * 2014-01-24 2017-12-26 Taiwan Semiconductor Manufacturing Company Ltd. Embedded source or drain region of transistor with downward tapered region under facet region
US9941367B2 (en) 2014-04-21 2018-04-10 Taiwan Semiconductor Manufacturing Company, Ltd. Wrap-around contact on FinFET
US11854898B2 (en) 2014-04-21 2023-12-26 Taiwan Semiconductor Manufacturing Co., Ltd. Wrap-around contact on FinFET
US11362000B2 (en) 2014-04-21 2022-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Wrap-around contact on FinFET
US11251086B2 (en) 2014-04-21 2022-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices, FinFET devices, and manufacturing methods thereof
US10651091B2 (en) 2014-04-21 2020-05-12 Taiwan Semiconductor Manufacturing Company, Ltd. Wrap-around contact on FinFET
US10269649B2 (en) 2014-04-21 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Wrap-around contact on FinFET
US9443769B2 (en) 2014-04-21 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Wrap-around contact
US10049938B2 (en) * 2014-04-21 2018-08-14 Taiwan Semiconductor Manufacturing Company Semiconductor devices, FinFET devices, and manufacturing methods thereof
US10164109B2 (en) 2014-10-17 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (FinFET) device and method for forming the same
US10964819B2 (en) 2014-10-17 2021-03-30 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (FinFET) device and method for forming the same
US10164108B2 (en) 2014-10-17 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (FinFET) device and method for forming the same
US11721762B2 (en) 2014-10-17 2023-08-08 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (FinFET) device and method for forming the same
US9653605B2 (en) * 2014-10-17 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Fin field effect transistor (FinFET) device and method for forming the same
US10546956B2 (en) 2014-10-17 2020-01-28 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (FinFET) device and method for forming the same
US11158744B2 (en) 2014-10-17 2021-10-26 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (FinFET) device and method for forming the same
US10686077B2 (en) 2014-10-17 2020-06-16 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (FinFET) device and method for forming the same
US10840378B2 (en) 2014-10-17 2020-11-17 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (FinFET) device and method for forming the same
US9865495B2 (en) 2015-11-05 2018-01-09 Samsung Electronics Co., Ltd. Semiconductor device and method for fabricating the same
US9502507B1 (en) * 2016-02-01 2016-11-22 Globalfoundries Inc. Methods of forming strained channel regions on FinFET devices
US9508848B1 (en) 2016-02-01 2016-11-29 Globalfoundries Inc. Methods of forming strained channel regions on FinFET devices by performing a heating process on a heat-expandable material
TWI624948B (en) * 2016-02-01 2018-05-21 格羅方德半導體公司 Method of forming a strain channel region on a FINFET device
US10727229B2 (en) 2016-02-23 2020-07-28 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and method for semiconductor device
US11031398B2 (en) 2016-02-23 2021-06-08 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and method for semiconductor device
US20170243868A1 (en) * 2016-02-23 2017-08-24 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and Method for Semiconductor Device
US9825036B2 (en) * 2016-02-23 2017-11-21 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and method for semiconductor device
US10868005B2 (en) 2016-04-25 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs and methods of forming finFETs
US10515958B2 (en) 2016-04-25 2019-12-24 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs and methods of forming FinFETs
US20170309624A1 (en) * 2016-04-25 2017-10-26 Taiwan Semiconductor Manufacturing Company, Ltd. Finfets and methods of forming finfets
US10163898B2 (en) * 2016-04-25 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs and methods of forming FinFETs

Also Published As

Publication number Publication date
US9123744B1 (en) 2015-09-01

Similar Documents

Publication Publication Date Title
US9123744B1 (en) Semiconductor device and method for fabricating the same
US8709897B2 (en) High performance strained source-drain structure and method of fabricating the same
US20140264444A1 (en) Stress-enhancing selective epitaxial deposition of embedded source and drain regions
US9287399B2 (en) Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels
US9406790B2 (en) Suspended ring-shaped nanowire structure
US9991258B2 (en) FinFETs with non-merged epitaxial S/D extensions having a SiGe seed layer on insulator
US9362170B2 (en) Dielectric liner for a self-aligned contact via structure
US9245974B2 (en) Performance boost by silicon epitaxy
US9520484B2 (en) Method for forming semiconductor nanowire transistors
US9209094B2 (en) Fin field effect transistor with dielectric isolation and anchored stressor elements
US9502562B2 (en) Fin field effect transistor including self-aligned raised active regions
US9601621B1 (en) Semiconductor device including dual spacer and uniform epitaxial buffer interface of embedded SiGe source/drain
CN105679824A (en) Fin field effect transistor and fabrication method thereof
US10734382B2 (en) Method for manufacturing a semiconductor structure including a very narrow aspect ratio trapping trench structure
US9099309B2 (en) Method providing an epitaxial growth having a reduction in defects and resulting structure
US20160149003A1 (en) Methods of Manufacturing Semiconductor Devices
CN104900525A (en) Semiconductor element, manufacturing method thereof and structure of semiconductor layer
US10147602B2 (en) Double aspect ratio trapping
CN106558495B (en) Fin formula field effect transistor and forming method thereof
US8901654B1 (en) Semiconductor-on-insulator (SOI) field effect transistor with buried epitaxial active regions
CN103578987A (en) Semiconductor device and method for manufacturing the same

Legal Events

Date Code Title Description
AS Assignment

Owner name: UNITED MICROELECTRONICS CORP., TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LIAO, CHIN-I;LIU, SHENG-HSU;SIGNING DATES FROM 20140220 TO 20140303;REEL/FRAME:032382/0295

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 8

点击 这是indexloc提供的php浏览器服务，不要输入任何密码和下载