US20150169445A1 - Virtual grouping of memory - Google Patents
Virtual grouping of memory Download PDFInfo
- Publication number
- US20150169445A1 US20150169445A1 US14/104,438 US201314104438A US2015169445A1 US 20150169445 A1 US20150169445 A1 US 20150169445A1 US 201314104438 A US201314104438 A US 201314104438A US 2015169445 A1 US2015169445 A1 US 2015169445A1
- Authority
- US
- United States
- Prior art keywords
- memory
- modules
- channel
- virtual
- segment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000000034 method Methods 0.000 claims description 23
- 239000000872 buffer Substances 0.000 claims description 16
- 238000010586 diagram Methods 0.000 description 16
- 230000004075 alteration Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 101001051799 Aedes aegypti Molybdenum cofactor sulfurase 3 Proteins 0.000 description 1
- 101710116852 Molybdenum cofactor sulfurase 1 Proteins 0.000 description 1
- 101710116850 Molybdenum cofactor sulfurase 2 Proteins 0.000 description 1
- 230000003466 anti-cipated effect Effects 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000007726 management method Methods 0.000 description 1
- 230000008520 organization Effects 0.000 description 1
- 238000011112 process operation Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
- G06F3/0617—Improving the reliability of storage systems in relation to availability
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0615—Address space extension
- G06F12/0623—Address space extension for memory modules
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0646—Configuration or reconfiguration
- G06F12/0653—Configuration or reconfiguration with centralised address assignment
- G06F12/0661—Configuration or reconfiguration with centralised address assignment and decentralised selection
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0646—Configuration or reconfiguration
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0629—Configuration or reconfiguration of storage systems
- G06F3/0631—Configuration or reconfiguration of storage systems by allocating resources to storage systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0662—Virtualisation aspects
- G06F3/0664—Virtualisation aspects at device level, e.g. emulation of a storage device or system
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0683—Plurality of storage devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1016—Performance improvement
- G06F2212/1024—Latency reduction
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/15—Use in a specific computing environment
- G06F2212/152—Virtualized environment, e.g. logically partitioned system
Definitions
- This disclosure relates to virtual memory grouping. In particular, it relates to virtual memory grouping across memory channels.
- Main memory in a system can be setup in various physical configurations to optimize power consumption and performance.
- Memory may be mirrored for redundancy to mitigate DIMM failures. Fully mirrored memory, while being fully redundant, would cut the capacity of the memory in half vs. non-mirrored memory.
- memory may be selectively mirrored so that a portion of the memory is mirrored, such as that containing information critical to program operation, and the remainder of the memory is non-mirrored.
- the present disclosure includes a method, comprising: identifying, in a memory system, a capacity for each of a plurality of memory modules for a first memory channel having a first amount of memory and a second memory channel having a second amount of memory; determining a memory segment size from the capacities of the memory modules; identifying a first memory segment of the memory segment size for the first memory channel and a second memory segment of the memory segment size for the second memory channel; and creating a virtual group that includes the first memory segment and the second memory segment and that uses less than the entire first amount of memory from the first memory channel.
- the present disclosure further includes a method, comprising identifying a capacity for each of a plurality of memory modules for a first memory channel and a second memory channel in a memory system; determining a first portion of memory modules and a second portion of memory modules from the capacities of the memory modules for each of the first and second memory channels; creating a first virtual group that includes the first portion of the memory modules from the first memory channel and the first portion of memory modules from the second memory channel; and creating a second virtual group that includes the second portion of the memory modules from the first memory channel and the second portion of memory modules from the second memory channel.
- the present disclosure further includes a computer system, comprising service processor firmware configured to identify a capacity for each of a plurality of memory modules for a first memory channel having a first amount of memory and a second memory channel having a second amount of memory; determine a memory segment size from the capacities of the memory modules; identify a first memory segment of the memory segment size for the first memory channel and a second memory segment of the memory segment size for the second memory channel; and create a virtual group that includes first memory segment and the second memory segment and that uses less than the entire first amount of memory from the first memory channel.
- FIG. 1 is a flowchart of a method for creating virtual groups of memory, according to embodiments of the disclosure.
- FIG. 2A is a diagram of a memory system, according to embodiments of the disclosure.
- FIG. 2B is a diagram of memory allocation in a memory system, according to embodiments of the disclosure.
- FIG. 3 is an example diagram of a memory system, according to embodiments of the disclosure.
- FIG. 4 is an example diagram of grouping of memory segments for the system of FIG. 3 , according to embodiments of the disclosure.
- FIG. 5A is a diagram of memory from memory controller segments in physical groups for physical grouping, according to embodiments of the disclosure.
- FIG. 5B is a diagram of memory from memory controller segments in virtual groups for virtual grouping 1 , according to embodiments of the disclosure.
- FIG. 5C is a diagram of memory from memory controller segments in virtual groups for virtual grouping 2 , according to embodiments of the disclosure.
- Memory modules in a memory system may be organized into groups along memory channels behind memory controllers and memory buffers to match the internal throughput of the system bus of a computer system.
- a memory controller may have multiple memory buffers, each memory buffer having multiple memory channels leading to one or more DIMMs.
- Memory modules may be populated into memory channels in groups of similar sizes of memory to enable memory minoring and memory interleaving, while unequal sizes of memory may be populated to form different groups.
- An operating system or hypervisor may allocate memory for an application as a physical group across multiple memory modules so that those memory modules may be accessed at the same time. The memory map for a particular physical group will likely be a single contiguous space.
- Accessing memory according to the physical organization of the memory behind the memory controller may compromise memory throughput and affinity. Access to the memory groups may be limited by the physical characteristics of the memory, as the grouping is performed along physical boundaries. Mirrored data may be allocated to physical memory groups of equal sizes behind a memory buffer, which may reduce the memory flexibility and utilization of the system. Memory grouped according to a particular bandwidth may not be optimized for the way in which the memory is actually utilized by applications.
- memory may be virtually grouped and accessed to improve memory throughput and affinity.
- Memory segments of an identified memory size may be grouped virtually according to considerations such as the minimum memory module capacity, application priority, criticality, or memory access characteristics, and performance data for various memory module configurations.
- Virtual groups accessed by multiple memory controllers may scale the throughput high, as a greater number of memory modules may be accessed in parallel.
- Virtual groups of equal memory segments may be created from the same physical memory group or from physical memory groups of different sizes and behind multiple memory controllers.
- Memory presented as and allocated through virtual groups may be accessed symmetrically and diffusely through operations such as memory interleaving.
- Performance and configuration information collected from memory in the virtual groups may be utilized by systems and users to improve physical memory access and application performance.
- the performance of memory in various virtual configurations may be used to create improved physical groupings of the memory modules through memory configuration and population rules.
- Data may be allocated to a particular memory group based on the priority of the application's data or the memory access characteristics of the application.
- Virtual groups may also support selective memory mirroring by identifying data to be mirrored and configuring virtual memory groups accordingly.
- FIG. 1 is a flowchart of a method for creating virtual groups of memory, according to embodiments of the disclosure.
- the memory capacities of one or more memory modules in the memory system may be determined, as in 100 .
- Memory from the memory modules may be grouped into virtual groups, as in 110 .
- Once the virtual groups are created, memory from the virtual groups may be allocated to applications, as in 120 .
- the memory modules having memory in a virtual memory group may be monitored for performance, power consumption, and other usage statistics, as in 130 .
- the system may perform an initial program load, as in 101 .
- vital product data for the memory modules may be collected, as in 102 .
- Vital product data may include hardware information, such as serial number and capacity.
- the vital product data may be determined for the system or collected from a vital product data storage location on the system.
- the collection of vital product data may be performed by a system such as the host system of the memory system, a remote system, or a field replaceable unit.
- Memory from the memory modules may be grouped into virtual memory groups, as in 110 .
- the capacities of the memory modules may be scanned and evaluated from the vital product data of the memory modules, as in 111 .
- a memory segment size (or portion) may be determined from the scanned memory module capacities, as in 112 , according to the memory access characteristics of the memory module.
- the memory segment size may be the smallest independently operated memory unit for one or more physical memory groups, such as the smallest memory module size or a rank size in a memory module.
- the memory segment size may be evaluated for memory modules across two or more memory channels.
- the memory segment size may be the smallest memory module size in common between the two memory channels.
- 1 GB may be the memory segment size; alternately, 2 GB may be the memory segment size, as both groups have at least two 1 GB DIMMs.
- Memory segments of the memory segment size may be identified for memory modules in the memory system, as in 113 , and used to create a virtual memory group, as in 114 .
- the two 1 GB DIMMs from the first channel and two 1 GB DIMMs from the second channel may be grouped into a first group. If a third memory channel has two 1 GB DIMMs, the remaining two 1 GB DIMMs from the second memory channel may be grouped with the two 1 GB DIMMs from the third memory channel.
- the virtual groups may contain memory from memory channels that is less than the total memory capacity of the memory channels.
- a memory buffer or controller having two memory channels may have memory grouped into two or more virtual groups, each group containing memory from both memory channels.
- a virtual group may have memory from memory channels of different memory capacity connected to two different controllers.
- a virtual group may have memory from memory channels having different memory capacities.
- Creation of virtual groups may be informed by performance information of the memory modules, as in 131 . For example, if an executing processor in a distributed shared memory system has greater processor affinity to a certain group of DIMMs, those DIMMs may be used for the virtual group assigned to an application executed on that processor.
- memory from the virtual groups may be allocated to applications, as in 120 .
- the application's priority, criticality, or memory access characteristics may inform the operating system or hypervisor as to which virtual group may be allocated to the application, as in 121 .
- a virtual group providing deeper memory access or limited to fewer memory modules may be used, so that memory for applications with more diffuse memory access or requiring greater fault tolerance may use virtual groups having a greater usage of memory modules.
- the virtual group may be targeted by or allocated to the application, as in 122 .
- the application's performance may be monitored to determine the appropriateness of the virtual group for that application.
- the memory modules in a virtual group may be monitored for performance and power consumption, as in 130 .
- Information of the memory modules, such as performance and power consumption, may be collected, as in 131 .
- the information may be used as feedback to determine memory module configuration options, as in 132 .
- These memory module configuration options may be used to physically configure or populate the memory modules so as to be improve memory access, such as by increasing memory affinity or optimizing throughput.
- These configuration options may be used as DIMM plug rules when the DIMMs are off-line.
- FIG. 2A is a diagram of a memory system, according to embodiments of the disclosure.
- a processor 201 may be connected to one or more memory controllers 202 .
- the memory controller 202 may be part of the processor itself, as shown in FIG. 2 , or on a separate chip.
- the processor contains a memory controller A 202 A and a memory controller B 202 B.
- Each memory controller may support one or more memory buffers 203 .
- the memory buffer 203 may be part of the memory controller 202 or on a separate chip. Shown here, memory controller A 202 A is connected to memory buffer A 203 A, and memory controller B 202 B is connected to memory buffer B 203 B. Each memory controller 202 or memory buffer 203 may be connected to one or more memory modules 204 through one or more memory channels 209 . Shown here, memory buffer A 203 A is connected to memory module A 204 A and memory module C 204 C through memory channel A 209 A, and memory buffer B 203 B is connected to DIMM B 204 B through memory channel B. The performance of the memory modules 204 and the processor 201 may be monitored by performance monitor logic 207 .
- the memory system may contain a service processor 205 .
- the service processor 205 may be a hardware or firmware unit configured for virtual memory management.
- the service processor 205 may be configured to create virtual groups 206 of memory from the memory modules 204 of different memory channels 209 .
- the service processor 205 may receive feedback from the performance monitor logic 207 as to performance of memory modules 204 in the virtual groups 206 and applications assigned to certain virtual groups 206 . This performance information may be used by a hypervisor 208 to assign applications to virtual groups 206 or to provide configuration options for physical configuration of the DIMMs 204 .
- FIG. 2B is a diagram of memory allocation in a memory system, according to embodiments of the disclosure.
- Service processor firmware 214 may create virtual memory groups from memory 215 .
- the memory 215 may include memory modules from across a memory system, including memory modules from different physical groups behind different processors, memory controllers, and memory buffers.
- An operating system 212 , hypervisor 213 , or application 211 may allocate memory 215 from the memory groups to the application 211 .
- the service processor firmware 214 may present the memory 215 to the hypervisor 213 or operating system 212 as virtual groups.
- FIG. 3 is an example diagram of a memory system for use in the examples diagrams of FIGS. 4 , 5 A, 5 B, and 5 C, according to embodiments of the disclosure.
- a processor 300 has eight memory controllers, each connected to multiple DIMMs through one or more memory channels (and optionally one or more memory buffers, not shown).
- the memory contained behind each memory controller may be referred to as the memory controller segment (MCS) for the memory controller.
- MCS memory controller segment
- Memory controller 1 301 controls DIMM 1A 311 A and DIMM 1B 311 B as MCS 1; memory controller 2 302 controls DIMM 2A 312 A and DIMM 2B 312 B as MCS 2; memory controller 3 303 controls DIMM 3A 313 A and DIMM 3B 313 B as MCS 3; memory controller 4 304 controls DIMM 4A 314 A and DIMM 4B 314 B as MCS 4; memory controller 5 305 controls DIMM 5A 315 A, DIMM 5B 315 B, DIMM 5D 315 C, and DIMM 5D 315 D as MCS 5; memory controller 6 306 controls DIMM 6A 316 A, DIMM 6B 316 B, DIMM 6C 316 C, and DIMM 6D 316 D as MCS 6; memory controller 7 307 controls DIMM 7A 317 A, DIMM 7B 317 B, DIMM 7C 317 C, DIMM 7D 317 D, DIMM 7E 317 E, DIMM 7F 317 F, DIMM 7G 317 G, and DI
- FIG. 4 is an example diagram of physical and virtual groupings of memory segments for the system of FIG. 3 , according to embodiments of the disclosure.
- memory from a memory controller segment MCS
- MCS memory controller segment
- three physical groups may be formed.
- Group 1 may contain 8 GB of total memory, comprising the 2 GB of memory behind each of the four memory controllers 1-4.
- Group 2 may contain 8 GB of total memory, comprising the 4 GB of memory behind memory controllers 5 and 6.
- Group 3 may contain 16 GB of total memory behind memory controllers 7 and 8.
- memory access may not be constrained to physical memory groups or memory controller segments, and a greater number of memory access configurations may be created.
- a greater number of memory buffers and controllers may access memory at a time, reducing access time to the memory.
- virtual groups having the same size as the physical groups discussed above may be formed, but with different memory access configurations.
- 2 GB of memory from each memory controller 1-8 may be grouped as memory segments into group 3 to form a 16 GB group; 2 GB of memory from each memory controller 5-8 may be grouped into group 2 to form an 8 GB group; and 4 GB of memory from each memory controller 7 and 8 may be grouped into group 1 to form an 8 GB group.
- 2 GB of DIMMs from each memory controller 1-4 may be grouped as memory segments into group 1 to form an 8 GB group; 4 GB of memory from each memory controller 7 and 8 may be grouped into group 2 to form an 8 GB group; and 4 GB of memory from each memory controller 5-8 may be grouped into group 3 to form a 16 GB group.
- FIG. 5A , FIG. 5B , and FIG. 5C are diagrams of the physical and virtual groupings of memory from FIG. 4 , according to embodiments of the disclosure.
- FIG. 5A is a diagram of memory from memory controller segments in physical groups for the physical grouping, according to embodiments of the disclosure. As discussed above, each physical group contains memory from memory controller segments of the same size and configuration.
- FIG. 5B is a diagram of memory from memory controller segments in virtual groups for the virtual grouping 1, according to embodiments of the disclosure.
- Memory access to group 3 is spread across 8 memory controllers, which may allow for greater throughput.
- Processor operations that require accessing multiple segments of information simultaneously, such as parallel processing, or containing critical data may best utilize the memory access characteristics of virtual group 3.
- Critical process operations requiring similar fast access or high availability but for a smaller 8 GB capacity may best utilize the memory access characteristics of virtual group 2.
- Non-critical applications or application that may better utilize access to the same DIMM for information, such as deep or linear computing operations, may utilize virtual group 1.
- the memory segments from each memory controller segment are similarly sized, and may be used for symmetrical processes such as memory mirroring and interleaving.
- FIG. 5C is a diagram of memory from memory controller segments in virtual groups for the virtual grouping 2, according to embodiments of the disclosure.
- Applications utilizing faster memory access for parallel processes or performing more critical operations may be assigned group 1.
- Applications involving non-critical storage may be assigned group 2.
- Operations involving linear memory access or minoring, such as database storage, may be assigned group 3, as access is spread across memory controllers.
- the 16 GB group capacity of group 3 is divided among four memory controllers for redundancy, two of which may contain original data and two of which may contain copy data.
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Memory System (AREA)
Abstract
The present disclosure includes identifying, in a memory system, a capacity for each of a plurality of memory modules for a first memory channel having a first amount of memory and a second memory channel having a second amount of memory; determining a memory segment size from the capacities of the memory modules; identifying a first memory segment of the memory segment size for the first memory channel and a second memory segment of the memory segment size for the second memory channel; and creating a virtual group that includes the first memory segment and the second memory segment and that uses less than the entire first amount of memory from the first memory channel.
Description
- This disclosure relates to virtual memory grouping. In particular, it relates to virtual memory grouping across memory channels.
- Main memory in a system can be setup in various physical configurations to optimize power consumption and performance. Memory may be mirrored for redundancy to mitigate DIMM failures. Fully mirrored memory, while being fully redundant, would cut the capacity of the memory in half vs. non-mirrored memory. However, memory may be selectively mirrored so that a portion of the memory is mirrored, such as that containing information critical to program operation, and the remainder of the memory is non-mirrored.
- The present disclosure includes a method, comprising: identifying, in a memory system, a capacity for each of a plurality of memory modules for a first memory channel having a first amount of memory and a second memory channel having a second amount of memory; determining a memory segment size from the capacities of the memory modules; identifying a first memory segment of the memory segment size for the first memory channel and a second memory segment of the memory segment size for the second memory channel; and creating a virtual group that includes the first memory segment and the second memory segment and that uses less than the entire first amount of memory from the first memory channel.
- The present disclosure further includes a method, comprising identifying a capacity for each of a plurality of memory modules for a first memory channel and a second memory channel in a memory system; determining a first portion of memory modules and a second portion of memory modules from the capacities of the memory modules for each of the first and second memory channels; creating a first virtual group that includes the first portion of the memory modules from the first memory channel and the first portion of memory modules from the second memory channel; and creating a second virtual group that includes the second portion of the memory modules from the first memory channel and the second portion of memory modules from the second memory channel.
- The present disclosure further includes a computer system, comprising service processor firmware configured to identify a capacity for each of a plurality of memory modules for a first memory channel having a first amount of memory and a second memory channel having a second amount of memory; determine a memory segment size from the capacities of the memory modules; identify a first memory segment of the memory segment size for the first memory channel and a second memory segment of the memory segment size for the second memory channel; and create a virtual group that includes first memory segment and the second memory segment and that uses less than the entire first amount of memory from the first memory channel.
- The drawings included in the present application are incorporated into, and form part of, the specification. They illustrate embodiments of the present invention and, along with the description, serve to explain the principles of the invention. The drawings are only illustrative of typical embodiments of the invention and do not limit the invention.
-
FIG. 1 is a flowchart of a method for creating virtual groups of memory, according to embodiments of the disclosure. -
FIG. 2A is a diagram of a memory system, according to embodiments of the disclosure. -
FIG. 2B is a diagram of memory allocation in a memory system, according to embodiments of the disclosure. -
FIG. 3 is an example diagram of a memory system, according to embodiments of the disclosure. -
FIG. 4 is an example diagram of grouping of memory segments for the system ofFIG. 3 , according to embodiments of the disclosure. -
FIG. 5A is a diagram of memory from memory controller segments in physical groups for physical grouping, according to embodiments of the disclosure. -
FIG. 5B is a diagram of memory from memory controller segments in virtual groups forvirtual grouping 1, according to embodiments of the disclosure. -
FIG. 5C is a diagram of memory from memory controller segments in virtual groups forvirtual grouping 2, according to embodiments of the disclosure. - Memory modules in a memory system may be organized into groups along memory channels behind memory controllers and memory buffers to match the internal throughput of the system bus of a computer system. For example, a memory controller may have multiple memory buffers, each memory buffer having multiple memory channels leading to one or more DIMMs. Memory modules may be populated into memory channels in groups of similar sizes of memory to enable memory minoring and memory interleaving, while unequal sizes of memory may be populated to form different groups. An operating system or hypervisor may allocate memory for an application as a physical group across multiple memory modules so that those memory modules may be accessed at the same time. The memory map for a particular physical group will likely be a single contiguous space.
- Accessing memory according to the physical organization of the memory behind the memory controller may compromise memory throughput and affinity. Access to the memory groups may be limited by the physical characteristics of the memory, as the grouping is performed along physical boundaries. Mirrored data may be allocated to physical memory groups of equal sizes behind a memory buffer, which may reduce the memory flexibility and utilization of the system. Memory grouped according to a particular bandwidth may not be optimized for the way in which the memory is actually utilized by applications.
- According to embodiments of the disclosure, memory may be virtually grouped and accessed to improve memory throughput and affinity. Memory segments of an identified memory size may be grouped virtually according to considerations such as the minimum memory module capacity, application priority, criticality, or memory access characteristics, and performance data for various memory module configurations. Virtual groups accessed by multiple memory controllers may scale the throughput high, as a greater number of memory modules may be accessed in parallel. Virtual groups of equal memory segments may be created from the same physical memory group or from physical memory groups of different sizes and behind multiple memory controllers. Memory presented as and allocated through virtual groups may be accessed symmetrically and diffusely through operations such as memory interleaving.
- Performance and configuration information collected from memory in the virtual groups may be utilized by systems and users to improve physical memory access and application performance. The performance of memory in various virtual configurations may be used to create improved physical groupings of the memory modules through memory configuration and population rules. Data may be allocated to a particular memory group based on the priority of the application's data or the memory access characteristics of the application. Virtual groups may also support selective memory mirroring by identifying data to be mirrored and configuring virtual memory groups accordingly.
-
FIG. 1 is a flowchart of a method for creating virtual groups of memory, according to embodiments of the disclosure. The memory capacities of one or more memory modules in the memory system may be determined, as in 100. Memory from the memory modules may be grouped into virtual groups, as in 110. Once the virtual groups are created, memory from the virtual groups may be allocated to applications, as in 120. The memory modules having memory in a virtual memory group may be monitored for performance, power consumption, and other usage statistics, as in 130. - To determine memory capacities of the memory modules, as in 100, the system may perform an initial program load, as in 101. Once the system has been initialized, vital product data for the memory modules may be collected, as in 102. Vital product data may include hardware information, such as serial number and capacity. The vital product data may be determined for the system or collected from a vital product data storage location on the system. The collection of vital product data may be performed by a system such as the host system of the memory system, a remote system, or a field replaceable unit.
- Memory from the memory modules may be grouped into virtual memory groups, as in 110. The capacities of the memory modules may be scanned and evaluated from the vital product data of the memory modules, as in 111. A memory segment size (or portion) may be determined from the scanned memory module capacities, as in 112, according to the memory access characteristics of the memory module. In certain embodiments, the memory segment size may be the smallest independently operated memory unit for one or more physical memory groups, such as the smallest memory module size or a rank size in a memory module. The memory segment size may be evaluated for memory modules across two or more memory channels. For example, if a first memory channel has two 1 GB DIMMs, a second memory channel has four 1 GB DIMMs, the memory segment size may be the smallest memory module size in common between the two memory channels. In this example, 1 GB may be the memory segment size; alternately, 2 GB may be the memory segment size, as both groups have at least two 1 GB DIMMs.
- Memory segments of the memory segment size may be identified for memory modules in the memory system, as in 113, and used to create a virtual memory group, as in 114. In the example above, the two 1 GB DIMMs from the first channel and two 1 GB DIMMs from the second channel may be grouped into a first group. If a third memory channel has two 1 GB DIMMs, the remaining two 1 GB DIMMs from the second memory channel may be grouped with the two 1 GB DIMMs from the third memory channel.
- The virtual groups may contain memory from memory channels that is less than the total memory capacity of the memory channels. In some embodiments, a memory buffer or controller having two memory channels may have memory grouped into two or more virtual groups, each group containing memory from both memory channels. In other embodiments, a virtual group may have memory from memory channels of different memory capacity connected to two different controllers. In other embodiments, a virtual group may have memory from memory channels having different memory capacities.
- Creation of virtual groups may be informed by performance information of the memory modules, as in 131. For example, if an executing processor in a distributed shared memory system has greater processor affinity to a certain group of DIMMs, those DIMMs may be used for the virtual group assigned to an application executed on that processor.
- Once the virtual groups are created, memory from the virtual groups may be allocated to applications, as in 120. The application's priority, criticality, or memory access characteristics may inform the operating system or hypervisor as to which virtual group may be allocated to the application, as in 121. For example, if an application is known to have fairly linear memory access or is non-critical, a virtual group providing deeper memory access or limited to fewer memory modules may be used, so that memory for applications with more diffuse memory access or requiring greater fault tolerance may use virtual groups having a greater usage of memory modules. The virtual group may be targeted by or allocated to the application, as in 122. The application's performance may be monitored to determine the appropriateness of the virtual group for that application.
- The memory modules in a virtual group may be monitored for performance and power consumption, as in 130. Information of the memory modules, such as performance and power consumption, may be collected, as in 131. The information may be used as feedback to determine memory module configuration options, as in 132. These memory module configuration options may be used to physically configure or populate the memory modules so as to be improve memory access, such as by increasing memory affinity or optimizing throughput. These configuration options may be used as DIMM plug rules when the DIMMs are off-line.
-
FIG. 2A is a diagram of a memory system, according to embodiments of the disclosure. Aprocessor 201 may be connected to one or more memory controllers 202. The memory controller 202 may be part of the processor itself, as shown inFIG. 2 , or on a separate chip. In this embodiment, the processor contains amemory controller A 202A and amemory controller B 202B. - Each memory controller may support one or more memory buffers 203. The memory buffer 203 may be part of the memory controller 202 or on a separate chip. Shown here,
memory controller A 202A is connected to memory buffer A 203A, andmemory controller B 202B is connected tomemory buffer B 203B. Each memory controller 202 or memory buffer 203 may be connected to one or more memory modules 204 through one or more memory channels 209. Shown here, memory buffer A 203A is connected tomemory module A 204A andmemory module C 204C throughmemory channel A 209A, andmemory buffer B 203B is connected toDIMM B 204B through memory channel B. The performance of the memory modules 204 and theprocessor 201 may be monitored byperformance monitor logic 207. - The memory system may contain a
service processor 205. Theservice processor 205 may be a hardware or firmware unit configured for virtual memory management. Theservice processor 205 may be configured to createvirtual groups 206 of memory from the memory modules 204 of different memory channels 209. Theservice processor 205 may receive feedback from theperformance monitor logic 207 as to performance of memory modules 204 in thevirtual groups 206 and applications assigned to certainvirtual groups 206. This performance information may be used by ahypervisor 208 to assign applications tovirtual groups 206 or to provide configuration options for physical configuration of the DIMMs 204. -
FIG. 2B is a diagram of memory allocation in a memory system, according to embodiments of the disclosure.Service processor firmware 214 may create virtual memory groups frommemory 215. Thememory 215 may include memory modules from across a memory system, including memory modules from different physical groups behind different processors, memory controllers, and memory buffers. Anoperating system 212,hypervisor 213, orapplication 211 may allocatememory 215 from the memory groups to theapplication 211. Theservice processor firmware 214 may present thememory 215 to thehypervisor 213 oroperating system 212 as virtual groups. -
FIG. 3 is an example diagram of a memory system for use in the examples diagrams ofFIGS. 4 , 5A, 5B, and 5C, according to embodiments of the disclosure. In this example, aprocessor 300 has eight memory controllers, each connected to multiple DIMMs through one or more memory channels (and optionally one or more memory buffers, not shown). The memory contained behind each memory controller may be referred to as the memory controller segment (MCS) for the memory controller.Memory controller 1 301controls DIMM 1ADIMM 1BMCS 1;memory controller 2 302controls DIMM 2ADIMM 2BMCS 2;memory controller 3 303controls DIMM 3ADIMM 3BMCS 3;memory controller 4 304controls DIMM 4ADIMM 4BMCS 4;memory controller 5 305controls DIMM 5ADIMM 5BDIMM 5DDIMM 5DMCS 5;memory controller 6 306controls DIMM 6ADIMM 6BDIMM 6CDIMM 6DMCS 6;memory controller 7 307controls DIMM 7ADIMM 7BDIMM 7CDIMM 7DDIMM 7EDIMM 7FDIMM 7GDIMM 7HMCS 7; andmemory controller 8 308controls DIMM 8ADIMM 8BDIMM 8CDIMM 8DDIMM 8EDIMM 8FDIMM 8GDIMM 8HMCS 8. For this example, each DIMM may be equal to 1 gigabyte (GB) of memory for simplicity of explanation. -
FIG. 4 is an example diagram of physical and virtual groupings of memory segments for the system ofFIG. 3 , according to embodiments of the disclosure. For a physical grouping, memory from a memory controller segment (MCS) may be grouped and accessed with memory from other memory controller segments having the same size and configuration to form physical groups for memory access. In this example, three physical groups may be formed.Group 1 may contain 8 GB of total memory, comprising the 2 GB of memory behind each of the four memory controllers 1-4.Group 2 may contain 8 GB of total memory, comprising the 4 GB of memory behindmemory controllers Group 3 may contain 16 GB of total memory behindmemory controllers - When the memory is grouped virtually, memory access may not be constrained to physical memory groups or memory controller segments, and a greater number of memory access configurations may be created. By virtually grouping smaller, equal segments of memory across memory channels, a greater number of memory buffers and controllers may access memory at a time, reducing access time to the memory. In this example, virtual groups having the same size as the physical groups discussed above may be formed, but with different memory access configurations.
- For
virtual grouping group 3 to form a 16 GB group; 2 GB of memory from each memory controller 5-8 may be grouped intogroup 2 to form an 8 GB group; and 4 GB of memory from eachmemory controller group 1 to form an 8 GB group. - For
virtual grouping group 1 to form an 8 GB group; 4 GB of memory from eachmemory controller group 2 to form an 8 GB group; and 4 GB of memory from each memory controller 5-8 may be grouped intogroup 3 to form a 16 GB group. -
FIG. 5A ,FIG. 5B , andFIG. 5C are diagrams of the physical and virtual groupings of memory fromFIG. 4 , according to embodiments of the disclosure.FIG. 5A is a diagram of memory from memory controller segments in physical groups for the physical grouping, according to embodiments of the disclosure. As discussed above, each physical group contains memory from memory controller segments of the same size and configuration. -
FIG. 5B is a diagram of memory from memory controller segments in virtual groups for thevirtual grouping 1, according to embodiments of the disclosure. Memory access togroup 3 is spread across 8 memory controllers, which may allow for greater throughput. Processor operations that require accessing multiple segments of information simultaneously, such as parallel processing, or containing critical data may best utilize the memory access characteristics ofvirtual group 3. Critical process operations requiring similar fast access or high availability but for a smaller 8 GB capacity may best utilize the memory access characteristics ofvirtual group 2. Non-critical applications or application that may better utilize access to the same DIMM for information, such as deep or linear computing operations, may utilizevirtual group 1. The memory segments from each memory controller segment are similarly sized, and may be used for symmetrical processes such as memory mirroring and interleaving. - For memory access administered with a lower overhead or for fewer critical or parallel access operations, a different virtual grouping configuration may be used.
FIG. 5C is a diagram of memory from memory controller segments in virtual groups for thevirtual grouping 2, according to embodiments of the disclosure. Applications utilizing faster memory access for parallel processes or performing more critical operations may be assignedgroup 1. Applications involving non-critical storage may be assignedgroup 2. Operations involving linear memory access or minoring, such as database storage, may be assignedgroup 3, as access is spread across memory controllers. The 16 GB group capacity ofgroup 3 is divided among four memory controllers for redundancy, two of which may contain original data and two of which may contain copy data. - Although the present disclosure has been described in terms of specific embodiments, it is anticipated that alterations and modifications thereof will become apparent to those skilled in the art. Therefore, it is intended that the following claims be interpreted as covering all such alterations and modifications as fall within the true spirit and scope of the disclosure.
Claims (17)
1. A method, comprising:
identifying, in a memory system, a capacity for each of a plurality of memory modules for a first memory channel having a first amount of memory and a second memory channel having a second amount of memory;
determining a memory segment size from the capacities of the memory modules;
identifying a first memory segment of the memory segment size for the first memory channel and a second memory segment of the memory segment size for the second memory channel; and
creating a virtual group that includes the first memory segment and the second memory segment and that uses less than the entire first amount of memory from the first memory channel.
2. The method of claim 1 , wherein the first amount of memory and the second amount of memory are not equal.
3. The method of claim 1 , wherein the first memory channel is connected to a first memory controller and the second memory channel is connected to a second memory controller.
4. The method of claim 1 , wherein the memory segment size is a capacity of one or more memory modules in common for each of the first memory channel and the second memory channel.
5. The method of claim 4 , wherein the memory segment size is a size of a smallest memory module in common for each of the first memory channel and the second memory channel.
6. The method of claim 1 , wherein identifying the capacity for each of a plurality of memory modules comprises:
collecting vital product data for each of the plurality of memory modules; and
determining the capacity from the vital product data for each of the plurality of memory modules.
7. The method of claim 1 , further comprising:
determining memory access characteristics of an application; and
assigning the virtual group to the application based on the memory access characteristics.
8. The method of claim 1 , further comprising:
collecting performance information from the memory modules having memory in the virtual group; and
determining memory module population rules from the performance information for the memory modules having memory in the virtual group.
9. The method of claim 8 , further comprising configuring memory modules in the memory system according to the memory module population rules.
10. The method of claim 7 , wherein at least one memory access characteristic involves memory mirroring.
11. A method, comprising:
identifying a capacity for each of a plurality of memory modules for a first memory channel and a second memory channel in a memory system;
determining a first portion of memory modules and a second portion of memory modules from the capacities of the memory modules for each of the first and second memory channels;
creating a first virtual group that includes the first portion of the memory modules from the first memory channel and the first portion of memory modules from the second memory channel; and
creating a second virtual group that includes the second portion of the memory modules from the first memory channel and the second portion of memory modules from the second memory channel.
12. The method of claim 11 , wherein the first memory channel and the second memory channel are connected to a memory buffer.
13. The method of claim 11 , wherein identifying the capacity for each of a plurality of memory modules comprises:
collecting vital product data for each of the plurality of memory modules; and
determining the capacity from the vital product data for each of the plurality of memory modules.
14. The method of claim 11 , further comprising:
determining memory access characteristics of an application; and
assigning the virtual group to the application based on the memory access characteristics.
15. The method of claim 11 , further comprising:
collecting performance information from the memory modules in the virtual group; and
determining memory population rules from the performance information for the memory modules in the virtual group.
16. The method of claim 11 , further comprising configuring memory modules in the memory system according to the memory population rules.
17-20. (canceled)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/104,438 US20150169445A1 (en) | 2013-12-12 | 2013-12-12 | Virtual grouping of memory |
US14/247,331 US20150169446A1 (en) | 2013-12-12 | 2014-04-08 | Virtual grouping of memory |
US15/244,010 US9600187B2 (en) | 2013-12-12 | 2016-08-23 | Virtual grouping of memory |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/104,438 US20150169445A1 (en) | 2013-12-12 | 2013-12-12 | Virtual grouping of memory |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/247,331 Continuation US20150169446A1 (en) | 2013-12-12 | 2014-04-08 | Virtual grouping of memory |
US15/244,010 Continuation US9600187B2 (en) | 2013-12-12 | 2016-08-23 | Virtual grouping of memory |
Publications (1)
Publication Number | Publication Date |
---|---|
US20150169445A1 true US20150169445A1 (en) | 2015-06-18 |
Family
ID=53368597
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/104,438 Abandoned US20150169445A1 (en) | 2013-12-12 | 2013-12-12 | Virtual grouping of memory |
US14/247,331 Abandoned US20150169446A1 (en) | 2013-12-12 | 2014-04-08 | Virtual grouping of memory |
US15/244,010 Expired - Fee Related US9600187B2 (en) | 2013-12-12 | 2016-08-23 | Virtual grouping of memory |
Family Applications After (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/247,331 Abandoned US20150169446A1 (en) | 2013-12-12 | 2014-04-08 | Virtual grouping of memory |
US15/244,010 Expired - Fee Related US9600187B2 (en) | 2013-12-12 | 2016-08-23 | Virtual grouping of memory |
Country Status (1)
Country | Link |
---|---|
US (3) | US20150169445A1 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9600187B2 (en) | 2013-12-12 | 2017-03-21 | International Business Machines Corporation | Virtual grouping of memory |
JP2018136922A (en) * | 2017-02-23 | 2018-08-30 | ハネウェル・インターナショナル・インコーポレーテッドHoneywell International Inc. | Memory division for computing system having memory pool |
US20190163379A1 (en) * | 2017-11-29 | 2019-05-30 | International Business Machines Corporation | Prevent disk hardware failure for cloud applications |
US20240220428A1 (en) * | 2015-06-09 | 2024-07-04 | Rambus Inc. | Memory system design using buffer(s) on a mother board |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20160188534A1 (en) * | 2014-12-31 | 2016-06-30 | Samsung Electronics Co., Ltd. | Computing system with parallel mechanism and method of operation thereof |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020010875A1 (en) * | 2000-01-25 | 2002-01-24 | Johnson Jerome J. | Hot-upgrade/hot-add memory |
US20050091454A1 (en) * | 2003-10-23 | 2005-04-28 | Hitachi, Ltd. | Storage having logical partitioning capability and systems which include the storage |
US20080052462A1 (en) * | 2006-08-24 | 2008-02-28 | Blakely Robert J | Buffered memory architecture |
US20090037652A1 (en) * | 2003-12-02 | 2009-02-05 | Super Talent Electronics Inc. | Command Queuing Smart Storage Transfer Manager for Striping Data to Raw-NAND Flash Modules |
US20110093726A1 (en) * | 2009-10-15 | 2011-04-21 | Microsoft Corporation | Memory Object Relocation for Power Savings |
US8244965B2 (en) * | 2007-06-28 | 2012-08-14 | Memoright Memoritech (Wuhan) Co., Ltd. | Control method for logical strips based on multi-channel solid-state non-volatile storage device |
US8275936B1 (en) * | 2009-09-21 | 2012-09-25 | Inphi Corporation | Load reduction system and method for DIMM-based memory systems |
US20140052908A1 (en) * | 2012-08-15 | 2014-02-20 | Lsi Corporation | Methods and structure for normalizing storage performance across a plurality of logical volumes |
US20150100746A1 (en) * | 2013-10-03 | 2015-04-09 | Qualcomm Incorporated | System and method for uniform interleaving of data across a multiple-channel memory architecture with asymmetric storage capacity |
US20150261698A1 (en) * | 2012-10-12 | 2015-09-17 | Huawei Technologies Co., Ltd. | Memory system, memory module, memory module access method, and computer system |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5845319A (en) * | 1995-08-23 | 1998-12-01 | Fujitsu Limited | Disk array device which separates local and physical disks using striping and operation mode selection |
US5953243A (en) * | 1998-09-30 | 1999-09-14 | International Business Machines Corporation | Memory module identification |
TWI350526B (en) | 2005-11-21 | 2011-10-11 | Infortrend Technology Inc | Data access methods and storage subsystems thereof |
CN100530138C (en) * | 2007-06-28 | 2009-08-19 | 忆正存储技术(深圳)有限公司 | Self-adaptive control method based on multi-passage flash memory apparatus logic strip |
US8082330B1 (en) * | 2007-12-28 | 2011-12-20 | Emc Corporation | Application aware automated storage pool provisioning |
US8099570B2 (en) | 2008-02-22 | 2012-01-17 | International Business Machines Corporation | Methods, systems, and computer program products for dynamic selective memory mirroring |
US8302102B2 (en) | 2008-02-27 | 2012-10-30 | International Business Machines Corporation | System utilization through dedicated uncapped partitions |
KR101477849B1 (en) | 2008-08-08 | 2014-12-30 | 휴렛-팩커드 디벨롭먼트 컴퍼니, 엘.피. | Independently controllable and reconfigurable virtual memory devices in memory modules that are pin-compatible with standard memory modules |
US8103776B2 (en) * | 2008-08-29 | 2012-01-24 | Red Hat, Inc. | Systems and methods for storage allocation in provisioning of virtual machines |
US8972694B1 (en) * | 2012-03-26 | 2015-03-03 | Emc Corporation | Dynamic storage allocation with virtually provisioned devices |
WO2013138587A1 (en) | 2012-03-14 | 2013-09-19 | Convergent .Io Technologies Inc. | Systems, methods and devices for management of virtual memory systems |
US9110592B2 (en) * | 2013-02-04 | 2015-08-18 | Microsoft Technology Licensing, Llc | Dynamic allocation of heterogenous memory in a computing system |
US20150169445A1 (en) | 2013-12-12 | 2015-06-18 | International Business Machines Corporation | Virtual grouping of memory |
-
2013
- 2013-12-12 US US14/104,438 patent/US20150169445A1/en not_active Abandoned
-
2014
- 2014-04-08 US US14/247,331 patent/US20150169446A1/en not_active Abandoned
-
2016
- 2016-08-23 US US15/244,010 patent/US9600187B2/en not_active Expired - Fee Related
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020010875A1 (en) * | 2000-01-25 | 2002-01-24 | Johnson Jerome J. | Hot-upgrade/hot-add memory |
US20050091454A1 (en) * | 2003-10-23 | 2005-04-28 | Hitachi, Ltd. | Storage having logical partitioning capability and systems which include the storage |
US20090037652A1 (en) * | 2003-12-02 | 2009-02-05 | Super Talent Electronics Inc. | Command Queuing Smart Storage Transfer Manager for Striping Data to Raw-NAND Flash Modules |
US20080052462A1 (en) * | 2006-08-24 | 2008-02-28 | Blakely Robert J | Buffered memory architecture |
US8244965B2 (en) * | 2007-06-28 | 2012-08-14 | Memoright Memoritech (Wuhan) Co., Ltd. | Control method for logical strips based on multi-channel solid-state non-volatile storage device |
US8275936B1 (en) * | 2009-09-21 | 2012-09-25 | Inphi Corporation | Load reduction system and method for DIMM-based memory systems |
US20110093726A1 (en) * | 2009-10-15 | 2011-04-21 | Microsoft Corporation | Memory Object Relocation for Power Savings |
US20140052908A1 (en) * | 2012-08-15 | 2014-02-20 | Lsi Corporation | Methods and structure for normalizing storage performance across a plurality of logical volumes |
US20150261698A1 (en) * | 2012-10-12 | 2015-09-17 | Huawei Technologies Co., Ltd. | Memory system, memory module, memory module access method, and computer system |
US20150100746A1 (en) * | 2013-10-03 | 2015-04-09 | Qualcomm Incorporated | System and method for uniform interleaving of data across a multiple-channel memory architecture with asymmetric storage capacity |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9600187B2 (en) | 2013-12-12 | 2017-03-21 | International Business Machines Corporation | Virtual grouping of memory |
US20240220428A1 (en) * | 2015-06-09 | 2024-07-04 | Rambus Inc. | Memory system design using buffer(s) on a mother board |
JP2018136922A (en) * | 2017-02-23 | 2018-08-30 | ハネウェル・インターナショナル・インコーポレーテッドHoneywell International Inc. | Memory division for computing system having memory pool |
JP7242170B2 (en) | 2017-02-23 | 2023-03-20 | ハネウェル・インターナショナル・インコーポレーテッド | Memory partitioning for computing systems with memory pools |
US20190163379A1 (en) * | 2017-11-29 | 2019-05-30 | International Business Machines Corporation | Prevent disk hardware failure for cloud applications |
US10831382B2 (en) * | 2017-11-29 | 2020-11-10 | International Business Machines Corporation | Prevent disk hardware failure for cloud applications |
Also Published As
Publication number | Publication date |
---|---|
US20150169446A1 (en) | 2015-06-18 |
US9600187B2 (en) | 2017-03-21 |
US20160357459A1 (en) | 2016-12-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9798471B2 (en) | Performance of de-clustered disk array by disk grouping based on I/O statistics | |
EP3100184B1 (en) | Prioritizing data reconstruction in distributed storage systems | |
US9600187B2 (en) | Virtual grouping of memory | |
US11137940B2 (en) | Storage system and control method thereof | |
US11797387B2 (en) | RAID stripe allocation based on memory device health | |
CN104123228A (en) | Data storage system and application method thereof | |
JP7419456B2 (en) | Storage system and its control method | |
JP6232936B2 (en) | Information processing apparatus, storage device control circuit, and storage device control method | |
US9785372B2 (en) | Storage device and method for configuring raid group | |
CN111857535B (en) | Method, electronic device, and computer-readable storage medium for storage management | |
US11256428B2 (en) | Scaling raid-based storage by redistributing splits | |
US8990523B1 (en) | Storage apparatus and its data processing method | |
US20240427524A1 (en) | Multipath initiator for data storage device arrays | |
US12175094B1 (en) | Fast and flexible data capacity upgrade via efficient reconfiguration | |
US20240201862A1 (en) | Disk array load balancing via interchangeable spare and data allocation | |
CN203102262U (en) | Memory device with multiple processors | |
US20240329857A1 (en) | Self-healing service level storage | |
JP2015090631A (en) | Storage control device, storage system, storage control method and program |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DELL, TIMOTHY J.;JAYARAMAN, PRASANNA;LINGAMBUDI, ANIL B.;AND OTHERS;SIGNING DATES FROM 20131209 TO 20131210;REEL/FRAME:031773/0001 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |