US20150021776A1

US20150021776A1 - Polysilicon layer

Info

Publication number: US20150021776A1
Application number: US14/507,317
Authority: US
Inventors: Chien-Liang Lin; Yu-Ren Wang; Ying-Wei Yen; Wen-Yi Teng; Chan-Lon Yang
Original assignee: United Microelectronics Corp
Current assignee: United Microelectronics Corp
Priority date: 2011-01-31
Filing date: 2014-10-06
Publication date: 2015-01-22
Also published as: US8895435B2; US20120193796A1

Abstract

A polysilicon layer including an amorphous polysilicon layer and a crystallized polysilicon layer is provided. The crystallized polysilicon layer is disposed on the amorphous polysilicon layer. Besides, the amorphous polysilicon layer has a first grain size, the crystallized polysilicon layer has a second grain size, and the first grain size is smaller than the second grain size. The amorphous polysilicon layer with a smaller grain size can serve as a base for the following deposition, so that the crystallized polysilicon layer formed thereon has a flatter topography, and thus, the surface roughness is reduced and the Rs uniformity within a wafer is improved.

Description

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional application of U.S. application Ser. No. 13/018,009, filed on Jan. 31, 2011, now allowed. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND OF THE INVENTION

1. Field of Invention
The present invention relates to a polysilicon layer and a method of forming the same, and more generally to a polysilicon layer with different grain sizes and a method of forming the same.
2. Description of Related Art
As the design rule of a semiconductor device is scaled down, the standard for the flatness of the gate is accordingly increased. The gate is usually fanned from polysilicon by a chemical vapor deposition (CVD) process. It is found that when the surface of the polysilicon layer is not flat enough, the surface roughness (Rq and Ra) of the polysilicon layer and the sheet resistance (Rs) uniformity within a wafer are affected, and the performance of the device is degraded.
Therefore, how to form a uniform polysilicon layer to improve the device performance has been one of the main topics in the industry.

SUMMARY OF THE INVENTION

The present invention provides a polysilicon layer with different grain sizes, in which smaller grains serving as a base are formed below larger grains, so that the surface uniformity of the polysilicon layer is improved. The present invention further provides a method to form the above-mentioned polysilicon layer.
The present invention provides a polysilicon layer including an amorphous polysilicon layer and a crystallized polysilicon layer disposed on the amorphous polysilicon layer. Besides, the amorphous polysilicon layer has a first grain size, the crystallized polysilicon layer has a second grain size, and the first grain size is smaller than the second grain size.
According to an embodiment of the present invention, the first grain size is about 10-20 nm, and the second grain size is about 25-30 nm.
According to an embodiment of the present invention, a thickness of the amorphous polysilicon layer is smaller than a thickness of the crystallized polysilicon layer.
According to an embodiment of the present invention, a thickness ratio of the amorphous polysilicon layer to the crystallized polysilicon layer is from about 1:2.5 to about 1:6.
According to an embodiment of the present invention, the thickness of the amorphous polysilicon layer is about 100-200 Å, and the thickness of the crystallized polysilicon layer is about 500-600 Å.
According to an embodiment of the present invention, the amorphous polysilicon layer is undoped, while the crystallized polysilicon layer is doped.
According to an embodiment of the present invention, at least a doped layer is disposed in the crystallized polysilicon layer to prevent dopants from diffusing to the amorphous polysilicon layer.
According to an embodiment of the present invention, at least a doped layer is substantially disposed at an interface between the amorphous polysilicon layer and the crystallized polysilicon layer or higher than the interface.
According to an embodiment of the present invention the amorphous polysilicon layer and the crystallized polysilicon layer have a total height H, and at least a doped layer is disposed larger than or equal to ⅔ H from a top surface of the crystallized polysilicon layer.
In view of above, the first polysilicon layer with a smaller grain size is formed by introducing an inhibitive gas or lowering a chamber temperature to inhibit the decomposition rate of the silicon-containing gas. The first polysilicon layer with the smaller grain size can serve as a base for the following deposition, so that the second polysilicon layer formed thereon has a flatter topography. Accordingly, the surface roughness of the polysilicon layer is reduced, the Rs uniformity within a wafer is improved, and the performance of the device is enhanced.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, a preferred embodiment accompanied with figures is described in detail below.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

FIGS. 1A to 1C schematically illustrate, in a cross-sectional view, a method of forming a polysilicon layer according to a first embodiment of the present invention.

FIGS. 2A to 2C schematically illustrate, in a cross-sectional view, a method of foaming a polysilicon layer according to a second embodiment of the present invention.

FIG. 3 schematically illustrates a cross-sectional view of a polysilicon layer according to an embodiment of the present invention.

DESCRIPTION OF EMBODIMENTS

First Embodiment

FIGS. 1A to 1C schematically illustrate, in a cross-sectional view, a method of forming a polysilicon layer according to a first embodiment of the present invention.
Referring to FIG. 1A, a first polysilicon layer 102 with a first grain size is formed on a substrate 100. The substrate 100 can be a semiconductor substrate, such as a silicon substrate. The first polysilicon layer 102 is formed by introducing a silicon-containing gas 104 and an inhibitive gas 106 into a CVD chamber. The silicon-containing gas 104 includes silane (SiH₄) or disilane (Si₂H₆), for example. The inhibitive gas 106 is for inhibiting the decomposition rate of the silicon-containing gas 104. The inhibitive gas 106 includes hydrogen (H₂), for example. The flow rate ratio of the silicon-containing gas 104 to the inhibitive gas 106 is from about 1:50 to about 1:60. For example, the flow rate of the silicon-containing gas 104 is about 50-60 sccm, and the flow rate of the inhibitive gas 106 is about 2,500-3,600 sccm. In an embodiment, the flow rates of the silicon-containing gas 104 and the inhibitive gas 106 keep the same during the process step. In another embodiment, the flow rate of the silicon-containing gas 104 keeps the same, while the flow of the inhibitive gas 106 increases over time. The chamber temperature is about 700-750° C., and the chamber pressure is about 50-500 torr. The formed first grain size is about 10-20 nm under the described process condition.
In an embodiment, an insulating layer 101 is optionally formed between the substrate 100 and the first polysilicon layer 102. The method of forming the insulating layer 101 includes performing a thermal oxidation process or a CVD process, for example. The insulating layer 101 includes silicon oxide or a high-k material, for example.
Referring to FIG. 1B, a second polysilicon layer 108 with a second grain size is formed on the first polysilicon layer 102. The second polysilicon layer 108 is formed by introducing the silicon-containing gas 104 into the same CVD chamber. That is, the entire deposition sequence is an in situ process. In operation, the valve for controlling the inhibitive gas 106 is simply turned off without changing other process parameters (i.e., chamber temperature, pressure, time, etc.) Since the inhibitive gas 106 is not present, the silicon-containing gas 104 (e.g., disilane) is decomposed more quickly and larger silicon grains are formed. Accordingly, the second grain size is about 25-30 nm and greater than the first grain size.
In addition, the thickness of the first polysilicon layer 102 is smaller than that of the second polysilicon layer 108. The thickness ratio of the first polysilicon layer 102 to the second polysilicon layer 108 is from about 1:2.5 to about 1:6. For example, the thickness of the first polysilicon layer 102 is about 100-200 Å, and the thickness of the second polysilicon layer 108 is about 500-600 Å.
Referring to FIG. 1C, a first ion implantation process is performed to the second polysilicon layer 108, so as to dope the second polysilicon layer 108 and form a doped region 110 in the second polysilicon layer 108. The first ion implantation process is for reducing the poly sheet resistance (poly Rs). In an embodiment, the doped region 110 includes phosphor for a NMOS transistor, example. In another embodiment, the doped region 110 includes boron for a PMOS transistor, for example.
If required, a second ion implantation process is performed before the step of performing a first ion implantation process, so as to form a barrier layer 109 in the second polysilicon layer 108 to prevent dopants from diffusing to the first polysilicon layer 102. In an embodiment, the barrier layer 109 includes germanium for a NMOS transistor, example. In another embodiment, the barrier layer 109 includes germanium for a PMOS transistor, for example.
Further, when the first polysilicon layer 102 and the second polysilicon layer 108 have a total height H, the barrier layer 109 and the bottom of the doped region 110 are disposed larger than or equal to ⅔ H from the top surface of the second polysilicon layer 108. In this embodiment, the interface between the first polysilicon layer 102 and the second polysilicon layer 108, the bather layer 109, and the bottom of the doped region 110 are substantially at the same depth. However, the present invention is not limited thereto. It is appreciated by persons skilled in the art that the interface between the first polysilicon layer 102 and the second polysilicon layer 108, the barrier layer 109, and the bottom of the doped region 110 can be at different depths.
Thereafter, an annealing process is performed to substrate 100, so as to repair the damage caused by the above-mentioned ion implantation processes.
In the first embodiment, the first polysilicon layer 102 with a smaller grain size is formed by introducing the inhibitive gas 106 to inhibit the decomposition rate of the silicon-containing gas 104. It is noted that the first polysilicon layer 102 with the smaller grain size can serve as a base for the following deposition, so that the second polysilicon layer 108 formed thereon has a flatter topography, and thus, the surface roughness is reduced and the Rs uniformity within a wafer is improved. It is also noted that the first polysilicon layer 102 is amorphous while the second polysilicon layer 108 is crystallized.

Second Embodiment

FIGS. 2A to 2C schematically illustrate, in a cross-sectional view, a method of forming a polysilicon layer according to a second embodiment of the present invention.
Referring to FIG. 2A, a first polysilicon layer 202 with a first grain size is rimmed on a substrate 200. The substrate 200 can be a semiconductor substrate, such as a silicon substrate. The first polysilicon layer 202 is formed by introducing a silicon-containing gas 204 into a lower-temperature CVD chamber. The silicon-containing gas 204 includes silane (SiH₄) or disilane (Si₂H₆), for example. The chamber temperature is about 550-650° C. and lower than the conventional chamber temperature of about 700-750° C. The flow rate of the silicon-containing gas 204 is about 50-60 sccm, and the chamber pressure is about 50-500 torr. The lower chamber temperature decreases the decomposition rate of the silicon-containing gas 204, so that smaller silicon grains are formed. Accordingly, the formed first grain size is about 10-20 nm.
In an embodiment, an insulating layer 201 is optionally formed between the substrate 200 and the first polysilicon layer 202. The forming method and the material of the insulating layer 201 are similar to those of the insulating layer 101 in the first embodiment, and the details are not iterated herein.
Referring to FIG. 2B, a second polysilicon layer 208 with a second grain size is formed on the first polysilicon layer 202. The second polysilicon layer 208 is formed by introducing the silicon-containing gas 204 into another higher-temperature CVD chamber. The chamber temperature is about 700-750° C. and similar to the conventional chamber temperature. In operation, the substrate 200 is sequentially transferred to the lower-temperature CVD chamber and the higher-temperature CVD chamber, while other process parameters (i.e., gas composition, gas flow rate, chamber pressure, time, etc.) between the two chambers keep the same. Higher chamber temperature results in larger silicon grains. Accordingly, the formed second grain size is about 25-30 nm and greater than the first grain size.
In addition, the thickness ranges of the first polysilicon layer 202 and the second polysilicon layer 208 are similar to those of the first polysilicon layer 102 and the second polysilicon layer 108 in the first embodiment, and the details are not iterated herein.
Referring to FIG. 2C, a first ion implantation process is performed to the second polysilicon layer 208, so as to dope the second polysilicon layer 208 and form a doped region 210 in the second polysilicon layer 208. If required, a second ion implantation process is performed before the step of performing a first ion implantation process, so as to form a barrier layer 209 in the second polysilicon layer 208 to prevent dopants from diffusing to the first polysilicon layer 202. The dopant types used for the first and second implantation processes have been described above, and the details are not iterated herein. Thereafter, an annealing process is performed to substrate 200, so as to repair the damage caused by the above-mentioned ion implantation processes.
In the second embodiment, the first polysilicon layer 202 with a smaller grain size is formed by lowering the chamber temperature to decrease the decomposition rate of the silicon-containing gas 204. It is noted that the first polysilicon layer 202 with the smaller grain size can serve as a base for the following deposition, so that the second polysilicon layer 208 formed thereon has a flatter topography, and thus, the surface roughness is reduced and the Rs uniformity within a wafer is improved. It is also noted that the first polysilicon layer 202 is amorphous while the second polysilicon layer 208 is crystallized.
The above-mentioned embodiments in which different process conditions are described are provided for illustration purposes, and are not construed as limiting the present invention. Specifically, in the first embodiment, different forming gases are used for forming the first polysilicon layer 202 and the second polysilicon layer 208. In the second embodiment, different forming temperatures are used for forming the first polysilicon layer 202 and the second polysilicon layer 208. However, the present invention is not limited thereto. It is appreciated by persons skilled in the art that the process conditions of the first and second embodiments can be combined upon the requirement.
The two-layer polysilicon structure of the present invention is illustrated by FIG. 2C in the following. Referring to FIG. 2C, the polsilicon layer of the present invention includes a first polysilicon layer 202 with a first grain size and a second polysilicon layer 208 with a second grain size, wherein the first grain size is smaller than the second grain size. Specifically, the first polysilicon layer 202 is an amorphous polysilicon layer while the second polysilicon layer 208 is a crystallized polysilicon layer. In an embodiment, the first grain size is about 10-20 nm, and the second grain size is about 25-30 nm. The thickness of the first polysilicon layer 202 is smaller than that of the second polysilicon layer 208. The thickness ratio of the first polysilicon layer 202 to the second polysilicon layer 208 is from about 1:2.5 to about 1:6. In an embodiment, the thickness of the first polysilicon layer 202 is about 100-200 Å, and the thickness of the second polysilicon layer 208 is about 500-600 Å. It is noted that the first polysilicon layer 202 is undoped, while the second polysilicon layer 208 is doped. At least one doped layer (e.g., barrier layer 209) is further disposed in the second polysilicon layer 208 to prevent dopants in the doped region 210 from diffusing to the first polysilicon layer 202. In this embodiment, as shown in FIG. 2C, the barrier layer 209 is disposed higher than the interface between the first polysilicon layer 202 and the second polysilicon layer 208. When the first polysilicon layer 102 and the second polysilicon layer 108 have a total height H, the barrier layer 109 is disposed larger than or equal to ⅔ H from the top surface of the second polysilicon layer 108. In another embodiment, as shown in FIG. 3, the barrier layer 209 is substantially disposed at the interface between the first polysilicon layer 202 and the second polysilicon layer 208.
An experimental group and a control group are provided below to prove the performance of the present invention.

Experimental Group

In accordance with the method of the present invention, a first polysilicon layer of 200 Å thick is formed on a silicon substrate by introducing disilane and hydrogen. Thereafter, a second polysilicon layer of 600 Å thick is formed on the first polysilicon layer by only introducing disilane. Afterwards, a germanium ion implantation process with a dose of 3E14 and an energy of 12 keV is performed to the second polysilicon layer, so as to form a barrier layer. Further, a phorphorous ion implantation process with a does of 5E15 and an energy of 5 KeV is performed to the second polysilicon layer, so as to form a doped region in the second polysilicon layer. Next, an activation annealing process is performed to the silicon substrate at 1025° C.

Control Group

A polysilicon layer of 800 Å thick is formed on a silicon substrate by only introducing disilane. Afterwards, a germanium ion implantation process with a dose of 3E14 and an energy of 12 keV is performed to the polysilicon layer, so as to form a barrier layer. Further, a phorphorous ion implantation process with a does of 5E15 and an energy of 5 KeV is performed to the polysilicon layer, so as to form a doped region in the polysilicon layer. Next, an activation annealing process is performed to the silicon substrate at 1025° C.
Table 1 lists the process parameters and testing results of the experimental group and the control group.

TABLE 1

						Grain
Process	Temp.	Press.	Si₂H₆	H₂	Thk.	size	Rq	Ra	Rs
step	(° C.)	(torr)	(sccm)	(sccm)	(Å)	(nm)	(nm)	(nm)	uniformity

Experimental	Step 1	710	50	60	3200	200	20	3.75	2.81	6.9%
Group	Step 2	710	50	60	0	600	25-30
Control	Single	710	50	60	0	800	25-30	4.25	3.18	10.2%
Group	step

* Ra means average roughness; Rq means root mean square roughness; Ra uniformity is obtained by measuring 121 points within a wafer.

Referring to Table 1, as compared with the single polysilicon layer in the control group, the two-layer polysilicon structure in the experimental group provides lower surface roughness (Rq and Ra) and better Rs uniformity within a wafer.
In summary, the first polysilicon layer with a smaller grain size is foamed by introducing an inhibitive gas or lowering a chamber temperature to inhibit the decomposition rate of the silicon-containing gas. The first polysilicon layer with the smaller grain size can serve as a base for the following deposition, so that the second polysilicon layer formed thereon has a flatter topography. However, the present invention is not limited thereto. It is appreciated by persons skilled in the art that introducing the inhibitive gas and lowering the chamber temperature can be applied at the same time, so as to foam a first polysilicon layer with an even smaller grain size serving as a base. Accordingly, the surface roughness of the polysilicon layer is reduced, the Rs uniformity within a wafer is improved, and the performance of the device is enhanced.
This invention has been disclosed above in the preferred embodiments, but is not limited to those. It is known to persons skilled in the art that some modifications and innovations may be made without departing from the spirit and scope of this invention. Hence, the scope of this invention should be defined by the following claims.

Claims

What is claimed is:

1. A polysilicon layer, comprising:

an amorphous polysilicon layer; and

a crystallized polysilicon layer, disposed on the amorphous polysilicon layer,

wherein the amorphous polysilicon layer has a first grain size, the crystallized polysilicon layer has a second grain size, and the first grain size is smaller than the second grain size.

2. The polysilicon layer of claim 1, wherein the first grain size is about 10-20 nm, and the second grain size is about 25-30 nm.

3. The polysilicon layer of claim 1, wherein a thickness of the amorphous polysilicon layer is smaller than a thickness of the crystallized polysilicon layer.

4. The polysilicon layer of claim 3, wherein a thickness ratio of the amorphous polysilicon layer to the crystallized polysilicon layer is from about 1:2.5 to about 1:6.

5. The polysilicon layer of claim 4, wherein the thickness of the amorphous polysilicon layer is about 100-200 Å, and the thickness of the crystallized polysilicon layer is about 500-600 Å.

6. The polysilicon layer of claim 1, wherein the amorphous polysilicon layer is undoped, while the crystallized polysilicon layer is doped.

7. The polysilicon layer of claim 6, wherein at least a doped layer is disposed in the crystallized polysilicon layer to prevent dopants from diffusing to the amorphous polysilicon layer.

8. The polysilicon layer of claim 6, wherein at least a doped layer is substantially disposed at an interface between the amorphous polysilicon layer and the crystallized polysilicon layer or higher than the interface.

9. The polysilicon layer of claim 6, wherein the amorphous polysilicon layer and the crystallized polysilicon layer have a total height H, and at least a doped layer is disposed larger than or equal to ⅔ H from a top surface of the crystallized polysilicon layer.