+

US20140273404A1 - Advanced Targeted Microwave Degas System - Google Patents

Advanced Targeted Microwave Degas System Download PDF

Info

Publication number
US20140273404A1
US20140273404A1 US14/091,854 US201314091854A US2014273404A1 US 20140273404 A1 US20140273404 A1 US 20140273404A1 US 201314091854 A US201314091854 A US 201314091854A US 2014273404 A1 US2014273404 A1 US 2014273404A1
Authority
US
United States
Prior art keywords
substrate
processing
process chamber
deposition
microwave radiation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US14/091,854
Inventor
Kent Riley Child
Minh Huu Le
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intermolecular Inc
Original Assignee
Intermolecular Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intermolecular Inc filed Critical Intermolecular Inc
Priority to US14/091,854 priority Critical patent/US20140273404A1/en
Assigned to INTERMOLECULAR, INC. reassignment INTERMOLECULAR, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LE, MINH HUU, CHILD, KENT RILEY
Publication of US20140273404A1 publication Critical patent/US20140273404A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76853Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76864Thermal treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002Preparing wafers
    • H01L21/02005Preparing bulk and homogeneous wafers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02181Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02189Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing zirconium, e.g. ZrO2
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10Measuring as part of the manufacturing process
    • H01L22/12Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10Measuring as part of the manufacturing process
    • H01L22/14Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/40FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/20Electrodes characterised by their shapes, relative sizes or dispositions 
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10FINORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/011Manufacture or treatment of image sensors covered by group H10F39/12
    • H10F39/028Manufacture or treatment of image sensors covered by group H10F39/12 performed after manufacture of the image sensors, e.g. annealing, gettering of impurities, short-circuit elimination or recrystallisation
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10FINORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10Integrated devices
    • H10F39/12Image sensors
    • H10F39/18Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10FINORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80Constructional details of image sensors
    • H10F39/805Coatings
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/881Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being a two-dimensional material
    • H10D62/882Graphene

Definitions

  • the present disclosure relates generally to use of degas processes used in the manufacture of microelectronic devices.
  • Degassing is a standard production technology for electronics manufacturing.
  • degas systems employing resistive heaters have been used to remove adsorbed moisture and contaminants from wafers during the manufacture of semiconductor devices, typically before subsequent deposition processes.
  • High volume manufacturing degas systems have been designed to create uniform temperatures across the substrate surface.
  • degas systems have been used to provide uniform temperature for entire substrates using resistive heating.
  • the substrates often include temperature sensitive materials or structures (e.g. dopant implants) that constrain the maximum temperature and/or the thermal budget for the device.
  • adsorbed species such as water vapor and/or contaminants must be removed from the surface of the substrate before subsequent deposition processes to ensure a clean interface and good device performance. What is needed is a system that allows adsorbed water vapor and/or contaminants to be removed without degrading the performance of temperature sensitive materials or structures formed on the substrate.
  • apparatus allow the investigation of process variables used in microwave-based degas systems to remove adsorbed species from the surface of a substrate.
  • the apparatus allow process variables such as power, dwell time, frequency, backside cooling gas usage, backside cooling gas flow rate, and the like to be investigated.
  • methods are described that allow the processing of a substrate using microwave-based degas systems.
  • the methods allow process variables such as power, dwell time, frequency, backside cooling gas usage, backside cooling gas flow rate, and the like to be investigated.
  • FIG. 1 illustrates a schematic diagram for implementing combinatorial processing and evaluation.
  • FIG. 2 presents a schematic diagram for illustrating various process sequences using combinatorial processing and evaluation.
  • FIG. 3 illustrates a processing system enabling combinatorial processing.
  • FIG. 4 presents a flow chart illustrating the steps of methods according to some embodiments.
  • FIG. 5 illustrates an apparatus according to some embodiments.
  • site-isolated refers to providing distinct processing conditions, such as controlled temperature, flow rates, chamber pressure, processing time, plasma composition, and plasma energies.
  • Site isolation may provide complete isolation between regions or relative isolation between regions.
  • the relative isolation is sufficient to provide a control over processing conditions within ⁇ 10%, within ⁇ 5%, within ⁇ 2%, within ⁇ 1%, or within ⁇ 0.1% of the target conditions. Where one region is processed at a time, adjacent regions are generally protected from any exposure that would alter the substrate surface in a measurable way.
  • site-isolated region is used herein to refer to a localized area on a substrate which is, was, or is intended to be used for processing or formation of a selected material.
  • the region can include one region and/or a series of regular or periodic regions predefined on the substrate.
  • the region may have any convenient shape, e.g., circular, rectangular, elliptical, wedge-shaped, etc.
  • a region may be, for example, a test structure, single die, multiple dies, portion of a die, other defined portion of substrate, or an undefined area of a substrate, e.g., blanket substrate which is defined through the processing.
  • substrate may refer to any workpiece on which formation or treatment of material layers is desired.
  • Substrates may include, without limitation, silicon, germanium, silicon-germanium alloy, silica, sapphire, zinc oxide, silicon carbide, aluminum nitride, gallium nitride, Spinel, coated silicon, silicon on oxide, silicon carbide on oxide, glass, gallium arsenide, indium phosphide, and combinations (or alloys) thereof.
  • substrate or “wafer” may be used interchangeably herein. Semiconductor wafer shapes and sizes can vary and include commonly used round wafers of 2′′, 4′′, 200 mm, or 300 mm in diameter.
  • microwave radiation refers to electromagnetic waves with frequencies between 300 MHz and 300 GHz. These frequencies correspond to wavelengths between 1 cm and 1 m.
  • remote microwave source refers to a microwave source located at a distance from a deposition or treatment location sufficient to allow some filtering of the microwave components.
  • degas refers to a process whereby adsorbed gases (e.g. water vapor, organic vapors, volatile contaminants, etc.) are substantially removed from a surface of a substrate prior to subsequent processing.
  • adsorbed gases e.g. water vapor, organic vapors, volatile contaminants, etc.
  • HPC processing techniques have been successfully adapted to wet chemical processing such as etching and cleaning. HPC processing techniques have also been successfully adapted to deposition processes such as physical vapor deposition (PVD), atomic layer deposition (ALD), and chemical vapor deposition (CVD).
  • PVD physical vapor deposition
  • ALD atomic layer deposition
  • CVD chemical vapor deposition
  • Embodiments of the present invention provide a system for systematic exploration of plasma treatment process variables in a combinatorial manner with the possibility of performing many variations on a single substrate.
  • the combinatorial processing permits a single substrate to be systematically explored using different plasma processing conditions, and reduces or eliminates variables that interfere with research quality.
  • the apparatuses and methods disclosed herein permit the systematic exploration of plasma treatments on a single substrate using combinatorial methods, and removes the run to run variability and inconsistencies between substrates that hamper research and optimization of process variables.
  • FIG. 1 illustrates a schematic diagram, 100 , for implementing combinatorial processing and evaluation using primary, secondary, and tertiary screening.
  • the schematic diagram, 100 illustrates that the relative number of combinatorial processes run with a group of substrates decreases as certain materials and/or processes are selected.
  • combinatorial processing includes performing a large number of processes during a primary screen, selecting promising candidates from those processes, performing the selected processing during a secondary screen, selecting promising candidates from the secondary screen for a tertiary screen, and so on.
  • feedback from later stages to earlier stages can be used to refine the success criteria and provide better screening results.
  • Materials discovery stage, 102 is also known as a primary screening stage performed using primary screening techniques.
  • Primary screening techniques may include dividing substrates into coupons and depositing materials using varied processes.
  • the materials are then evaluated, and promising candidates are advanced to the secondary screen, or materials and process development stage, 104 . Evaluation of the materials is performed using metrology tools such as electronic testers and imaging tools (i.e., microscopes).
  • the materials and process development stage, 104 may evaluate hundreds of materials (i.e., a magnitude smaller than the primary stage) and may focus on the processes used to deposit or develop those materials. Promising materials and processes are again selected, and advanced to the tertiary screen or process integration stage, 106 , where tens of materials and/or processes and combinations are evaluated.
  • the tertiary screen or process integration stage, 106 may focus on integrating the selected processes and materials with other processes and materials.
  • the most promising materials and processes from the tertiary screen are advanced to device qualification, 108 .
  • device qualification the materials and processes selected are evaluated for high volume manufacturing, which normally is conducted on full substrates within production tools, but need not be conducted in such a manner. The results are evaluated to determine the efficacy of the selected materials and processes. If successful, the use of the screened materials and processes can proceed to pilot manufacturing, 110 .
  • the schematic diagram, 100 is an example of various techniques that may be used to evaluate and select materials and processes for the development of new materials and processes.
  • the descriptions of primary, secondary, etc. screening and the various stages, 102 - 110 are arbitrary and the stages may overlap, occur out of sequence, be described and be performed in many other ways.
  • the composition or thickness of the layers or structures or the actions is substantially uniform through each discrete region.
  • different materials or processes may be used for corresponding layers or steps in the formation of a structure in different regions of the substrate during the combinatorial processing
  • the application of each layer or use of a given process is substantially consistent or uniform throughout the different regions in which it is intentionally applied.
  • the processing is uniform within a region (inter-region uniformity) and between regions (intra-region uniformity), as desired.
  • the process can be varied between regions, for example, where a thickness of a layer is varied or a material may be varied between the regions, etc., as desired by the design of the experiment.
  • the result is a series of regions on the substrate that contain structures or unit process sequences that have been uniformly applied within that region and, as applicable, across different regions.
  • This process uniformity allows comparison of the properties within and across the different regions such that the variations in test results are due to the varied parameter (e.g., materials, unit processes, unit process parameters, hardware details, or process sequences) and not the lack of process uniformity.
  • the positions of the discrete regions on the substrate can be defined as needed, but are preferably systematized for ease of tooling and design of experimentation.
  • the number, variants and location of structures within each region are designed to enable valid statistical analysis of the test results within each region and across regions to be performed.
  • FIG. 2 is a simplified schematic diagram illustrating a general methodology for combinatorial process sequence integration that includes site-isolated processing and/or conventional processing in accordance with one embodiment of the invention.
  • the substrate is initially processed using conventional process N.
  • the substrate is then processed using site-isolated process N+1.
  • an HPC module may be used, such as the HPC module described in U.S. patent application Ser. No. 11/352,077 filed on Feb. 10, 2006.
  • the substrate can then be processed using site-isolated process N+2, and thereafter processed using conventional process N+3. Testing is performed and the results are evaluated.
  • the testing can include physical, chemical, acoustic, magnetic, electrical, optical, etc. tests.
  • a particular process from the various site-isolated processes may be selected and fixed so that additional combinatorial process sequence integration may be performed using site-isolated processing for either process N or N+3.
  • a next process sequence can include processing the substrate using site-isolated process N, conventional processing for processes N+1, N+2, and N+3, with testing performed thereafter.
  • the combinatorial process sequence integration can be applied to any desired segments and/or portions of an overall process flow. Characterization, including physical, chemical, acoustic, magnetic, electrical, optical, etc. testing, can be performed after each process operation, and/or series of process operations within the process flow as desired. The feedback provided by the testing is used to select certain materials, processes, process conditions, and process sequences and eliminate others. Furthermore, the above process flows can be applied to entire monolithic substrates, or portions of the monolithic substrates.
  • a processing material delivered to a first and second region can be the same or different. If the processing material delivered to the first region is the same as the processing material delivered to the second region, this processing material can be offered to the first and second regions on the substrate at different concentrations. In addition, the material can be deposited under different processing parameters.
  • Parameters which can be varied include, but are not limited to, process material amounts, reactant species, processing temperatures, processing times, processing pressures, processing flow rates, processing powers, processing reagent compositions, the rates at which the reactions are quenched, atmospheres in which the processes are conducted, the order in which materials are deposited, hardware details of the gas distribution assembly, etc. It should be appreciated that these process parameters are exemplary and not meant to be an exhaustive list as other process parameters commonly used with plasma exposure systems may be varied.
  • the process conditions are substantially uniform, in contrast to gradient processing techniques which rely on the inherent non-uniformity of the material deposition. That is, the embodiments, described herein locally perform the processing in a conventional manner, e.g., substantially consistent and substantially uniform, while globally over the substrate, the materials, processes, and process sequences may vary. Thus, the testing will find optimums without interference from process variation differences between processes that are meant to be the same. It should be appreciated that a region may be adjacent to another region in one embodiment or the regions may be isolated and, therefore, non-overlapping.
  • regions When the regions are adjacent, there may be a slight overlap wherein the materials or precise process interactions are not known, however, a portion of the regions, normally at least 50% or more of the area, is uniform and all testing occurs within that region. Further, the potential overlap is only allowed with material of processes that will not adversely affect the result of the tests. Both types of regions are referred to herein as regions or discrete regions.
  • Substrates may be a conventional round 200 mm, 300 mm, or any other larger or smaller substrate/wafer size. In other embodiments, substrates may be square, rectangular, or other shape. One skilled in the art will appreciate that substrate may be a blanket substrate, a coupon (e.g., partial wafer), or even a patterned substrate having predefined regions. In some embodiments, a substrate may have regions defined through the processing described herein.
  • the process parameters comprise selection of one or more source gases for the plasma generator, plasma filtering parameters, exposure time, substrate temperature, power, frequency, plasma generation method, substrate bias, pressure, gas flow, or combinations thereof.
  • FIG. 3 is a simplified schematic diagram illustrating an integrated high productivity combinatorial (HPC) system in accordance with some embodiments of the invention.
  • the HPC system includes a frame 300 supporting a plurality of processing modules. It will be appreciated that frame 300 may be a unitary frame in accordance with some embodiments. In some embodiments, the environment within frame 300 is controlled.
  • a load lock 302 provides access into the plurality of modules of the HPC system.
  • a robot 314 provides for the movement of substrates (and masks) between the modules and for the movement into and out of the load lock 302 .
  • Modules 304 - 312 may be any set of modules and preferably include one or more combinatorial modules.
  • module 304 may be an orientation/degassing module
  • module 306 may be a clean module, either plasma or non-plasma based
  • modules 308 and/or 310 may be combinatorial/conventional dual purpose modules.
  • Module 312 may provide conventional clean or degas as necessary for the experiment design.
  • a centralized controller i.e., computing device 316
  • a plurality of methods may be employed to deposit material upon a substrate employing combinatorial processes.
  • Degas processes are used in several stages or steps during the manufacture of semiconductor, optoelectronic, and thin film photovoltaic devices.
  • the degas process may be used as a thermal treatment, wherein the substrate is heated in an inert atmosphere.
  • current degas systems are designed to produce a uniform temperature across the entire surface of the substrate using resistive heating.
  • the substrates often include temperature sensitive materials or structures (e.g. dopant implants) that constrain the maximum temperature and/or the thermal budget for the device.
  • adsorbed species such as water vapor and/or contaminants must be removed from the surface of the substrate before subsequent deposition processes to ensure a clean interface and good device performance.
  • Degas processes are needed for both conventional and high productivity combinatorial processing flows.
  • Microwave radiation is generally understood to refer to electromagnetic waves with frequencies between 300 MHz and 300 GHz. Government regulations limit industrial and medical application frequencies to 27.12 MHz, 915 MHz, and 2.45 GHz. Typical heating applications use microwave radiation with frequencies of 2.45 GHz so that they do not interfere with telecommunications and cellular phone frequencies. Microwave radiation with frequencies of 2.45 GHz has energies of about 0.0016 eV. Clearly these energy levels are not high enough to directly break chemical bonds. As an example, Van der Waals bonds have typical energies of about 0.044 eV, hydrogen bonds have typical energies of about 0.2 eV, ionic bonds have typical energies of about 0.17 to 0.3 eV, and single covalent bonds have typical energies of about 2 to 5 eV. Therefore, the microwave radiation cannot directly induce chemical reactions.
  • the microwave radiation will interact with dipoles formed by chemical bonding and interactions of adsorbed species with surfaces. As the dipoles are exposed to the microwave radiation, they will attempt to align with the oscillating electric field. In condensed phases (e.g. liquids and solids), steric hindrance prevents the dipoles from efficiently following the oscillating electric field, causing a phase delay between the electric field and the dipole alignment. This phase delay causes energy, in the form of heat, to be lost from the dipole by molecular friction and collisions. The increase in temperature is sufficient to overcome the bonding between the adsorbed species (e.g. water vapor, organic vapors, volatile contaminants, etc.) and the surface.
  • the adsorbed species e.g. water vapor, organic vapors, volatile contaminants, etc.
  • the adsorbed species can be removed from the surface without degrading the performance of temperature sensitive materials or structures that may be formed on the substrate.
  • the substrate and bulk materials formed on the substrate interact only very weakly with the microwave radiation due to the absence of strong dipoles (e.g. the bonding is largely symmetric within the substrate and bulk materials).
  • the efficacy of the microwave degas process may be influenced by process parameters such as power, dwell time, frequency, backside cooling gas usage, backside cooling gas flow rate.
  • FIG. 4 presents a flow chart illustrating the steps of methods according to some embodiments.
  • a substrate is provided to a degas module of a cluster system as described previously, or to some other suitably equipped chamber.
  • the substrate may be one of silicon, germanium, silicon-germanium alloy, silica, sapphire, zinc oxide, silicon carbide, aluminum nitride, gallium nitride, Spinel, coated silicon, silicon on oxide, silicon carbide on oxide, glass, gallium arsenide, indium phosphide, and combinations (or alloys) thereof.
  • the substrate will have gases and/or contaminant species adsorbed on the surface. Typical gases and/or contaminant species include water vapor, organic vapors, volatile contaminants, etc.
  • the substrate is exposed to microwave radiation.
  • the microwave radiation is generated in a remote source and is delivered to the degas module using a wave guide.
  • the frequency of the microwave radiation is varied in a continuous manner during the exposing so that localized hot spots do not form on isolated portions of the substrate.
  • the frequency of the microwave electromagnetic radiation can be varied in a range around 2.45 GHz.
  • the backside of the substrate may be heated to further enhance the degas process.
  • the backside of the substrate may be cooled to further protect temperature sensitive materials and/or structures on the substrate during the degas process.
  • the methods allow process variables such as power, dwell time, frequency, backside cooling gas usage, backside cooling gas flow rate, and the like to be varied to improve the degas process performance.
  • the substrate is transported to another process module if necessary for subsequent processing.
  • the transport typically occurs under vacuum within a cluster system (e.g. as discussed previously) or similar controlled environment so that additional water vapor and other contaminants do not adsorb on the degassed surface.
  • Typical subsequent processes include surface treatment processes and deposition processes.
  • the surface treatment processes may be one or more of plasma surface treatment or thermal surface treatment.
  • the deposition processes may be one or more of atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), pulsed laser deposition (PLD), or molecular beam epitaxy (MBE).
  • ALD atomic layer deposition
  • PEALD plasma enhanced atomic layer deposition
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • PLD pulsed laser deposition
  • MBE molecular beam epitaxy
  • FIG. 5 illustrates a first process chamber enabling degas processing using microwave radiation.
  • the first process chamber includes a substrate support, 502 , used to support a substrate, 500 .
  • the substrate support may include the capability of active heating and/or cooling.
  • the substrate support is contained within a processing chamber, 504 .
  • the processing chamber is held at a pressure between 1 mTorr and 760 Torr during the degas process.
  • An ancillary structure, 506 houses a remote microwave source, 508 .
  • the remote microwave source, 508 is operable to generate microwave radiation at a frequency of about 2.45 GHz.
  • the frequency of the microwave radiation is varied in a continuous manner (e.g.
  • the microwave radiation is delivered to the process chamber using a waveguide, 510 .
  • the waveguide includes a section of bellows, thus allowing the distance from the process chamber to the ancillary structure to be adjusted.
  • the microwave radiation is delivered to the surface of the substrate through delivery nozzle, 512 .
  • the microwave radiation may irradiate the entire substrate or may irradiate a portion of the substrate. In embodiments where the microwave radiation irradiates only portions of the surface of the substrate, the substrate may be moved (e.g.
  • the first process chamber allows process variables such as power, dwell time, frequency, backside cooling gas usage, backside cooling gas flow rate, and the like to be varied to improve the degas process performance.
  • a second process chamber (not shown) is used to apply a subsequent process to the surface of the substrate after the degas process.
  • the substrate may be transported to the second process chamber by a robot (not shown in FIG. 5 ).

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Chemical Vapour Deposition (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Formation Of Insulating Films (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

In some embodiments, methods are described that allow the processing of a substrate using microwave-based degas systems. The methods allow process variables such as power, dwell time, frequency, backside cooling gas usage, backside cooling gas flow rate, and the like to be investigated. In some embodiments, apparatus are described that allow the investigation of process variables used in microwave-based degas systems to remove adsorbed species from the surface of a substrate. The apparatus allow process variables such as power, dwell time, frequency, backside cooling gas usage, backside cooling gas flow rate, and the like to be investigated.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application claims priority to U.S. Provisional Patent Application No. 61/779,740, filed on Mar. 13, 2013, which is herein incorporated by reference for all purposes.
  • TECHNICAL FIELD
  • The present disclosure relates generally to use of degas processes used in the manufacture of microelectronic devices.
  • BACKGROUND
  • Degassing is a standard production technology for electronics manufacturing. In particular, degas systems employing resistive heaters have been used to remove adsorbed moisture and contaminants from wafers during the manufacture of semiconductor devices, typically before subsequent deposition processes. High volume manufacturing degas systems have been designed to create uniform temperatures across the substrate surface.
  • Heretofore, degas systems have been used to provide uniform temperature for entire substrates using resistive heating. However, the substrates often include temperature sensitive materials or structures (e.g. dopant implants) that constrain the maximum temperature and/or the thermal budget for the device. Yet, adsorbed species such as water vapor and/or contaminants must be removed from the surface of the substrate before subsequent deposition processes to ensure a clean interface and good device performance. What is needed is a system that allows adsorbed water vapor and/or contaminants to be removed without degrading the performance of temperature sensitive materials or structures formed on the substrate.
  • SUMMARY
  • The following summary of the disclosure is included in order to provide a basic understanding of some aspects and features of the invention. This summary is not an extensive overview of the invention and as such it is not intended to particularly identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented below.
  • In some embodiments, apparatus are described that allow the investigation of process variables used in microwave-based degas systems to remove adsorbed species from the surface of a substrate. The apparatus allow process variables such as power, dwell time, frequency, backside cooling gas usage, backside cooling gas flow rate, and the like to be investigated.
  • In some embodiments, methods are described that allow the processing of a substrate using microwave-based degas systems. The methods allow process variables such as power, dwell time, frequency, backside cooling gas usage, backside cooling gas flow rate, and the like to be investigated.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. The drawings are not to scale and the relative dimensions of various elements in the drawings are depicted schematically and not necessarily to scale.
  • The techniques of the present invention can readily be understood by considering the following detailed description in conjunction with the accompanying drawings, in which:
  • FIG. 1 illustrates a schematic diagram for implementing combinatorial processing and evaluation.
  • FIG. 2 presents a schematic diagram for illustrating various process sequences using combinatorial processing and evaluation.
  • FIG. 3 illustrates a processing system enabling combinatorial processing.
  • FIG. 4 presents a flow chart illustrating the steps of methods according to some embodiments.
  • FIG. 5 illustrates an apparatus according to some embodiments.
  • DETAILED DESCRIPTION
  • A detailed description of one or more embodiments is provided below along with accompanying figures. The detailed description is provided in connection with such embodiments, but is not limited to any particular example. The scope is limited only by the claims and numerous alternatives, modifications, and equivalents are encompassed. Numerous specific details are set forth in the following description in order to provide a thorough understanding. These details are provided for the purpose of example and the described techniques may be practiced according to the claims without some or all of these specific details. For the purpose of clarity, technical material that is known in the technical fields related to the embodiments has not been described in detail to avoid unnecessarily obscuring the description.
  • Before various embodiments are described in detail, it is to be understood that unless otherwise indicated, this invention is not limited to specific layer compositions or surface treatments. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of the present invention.
  • It must be noted that as used herein and in the claims, the singular forms “a,” “and” and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to “a layer” includes two or more layers, and so forth.
  • Where a range of values is provided, it is understood that each intervening value, to the tenth of the unit of the lower limit unless the context clearly dictates otherwise, between the upper and lower limit of that range, and any other stated or intervening value in that stated range, is encompassed within the invention. The upper and lower limits of these smaller ranges may independently be included in the smaller ranges, and are also encompassed within the invention, subject to any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included in the invention. The term “about” generally refers to ±10% of a stated value.
  • The term “site-isolated” as used herein refers to providing distinct processing conditions, such as controlled temperature, flow rates, chamber pressure, processing time, plasma composition, and plasma energies. Site isolation may provide complete isolation between regions or relative isolation between regions. Preferably, the relative isolation is sufficient to provide a control over processing conditions within ±10%, within ±5%, within ±2%, within ±1%, or within ±0.1% of the target conditions. Where one region is processed at a time, adjacent regions are generally protected from any exposure that would alter the substrate surface in a measurable way.
  • The term “site-isolated region” is used herein to refer to a localized area on a substrate which is, was, or is intended to be used for processing or formation of a selected material. The region can include one region and/or a series of regular or periodic regions predefined on the substrate. The region may have any convenient shape, e.g., circular, rectangular, elliptical, wedge-shaped, etc. In the semiconductor field, a region may be, for example, a test structure, single die, multiple dies, portion of a die, other defined portion of substrate, or an undefined area of a substrate, e.g., blanket substrate which is defined through the processing.
  • The term “substrate” as used herein may refer to any workpiece on which formation or treatment of material layers is desired. Substrates may include, without limitation, silicon, germanium, silicon-germanium alloy, silica, sapphire, zinc oxide, silicon carbide, aluminum nitride, gallium nitride, Spinel, coated silicon, silicon on oxide, silicon carbide on oxide, glass, gallium arsenide, indium phosphide, and combinations (or alloys) thereof. The term “substrate” or “wafer” may be used interchangeably herein. Semiconductor wafer shapes and sizes can vary and include commonly used round wafers of 2″, 4″, 200 mm, or 300 mm in diameter.
  • The term “microwave radiation” as used herein refers to electromagnetic waves with frequencies between 300 MHz and 300 GHz. These frequencies correspond to wavelengths between 1 cm and 1 m.
  • The term “remote microwave source” as used herein refers to a microwave source located at a distance from a deposition or treatment location sufficient to allow some filtering of the microwave components.
  • The term “degas” as used herein refers to a process whereby adsorbed gases (e.g. water vapor, organic vapors, volatile contaminants, etc.) are substantially removed from a surface of a substrate prior to subsequent processing.
  • Systems and methods for High Productivity Combinatorial (HPC) processing are described in U.S. Pat. No. 7,544,574 filed on Feb. 10, 2006, U.S. Pat. No. 7,824,935 filed on Jul. 2, 2008, U.S. Pat. No. 7,871,928 filed on May 4, 2009, U.S. Pat. No. 7,902,063 filed on Feb. 10, 2006, and U.S. Pat. No. 7,947,531 filed on Aug. 28, 2009 which are all herein incorporated by reference. Systems and methods for HPC processing are further described in U.S. patent application Ser. No. 11/352,077 filed on Feb. 10, 2006, claiming priority from Oct. 15, 2005, U.S. patent application Ser. No. 11/419,174 filed on May 18, 2006, claiming priority from Oct. 15, 2005, U.S. patent application Ser. No. 11/674,132 filed on Feb. 12, 2007, claiming priority from Oct. 15, 2005, and U.S. patent application Ser. No. 11/674,137 filed on Feb. 12, 2007, claiming priority from Oct. 15, 2005 which are all herein incorporated by reference.
  • HPC processing techniques have been successfully adapted to wet chemical processing such as etching and cleaning. HPC processing techniques have also been successfully adapted to deposition processes such as physical vapor deposition (PVD), atomic layer deposition (ALD), and chemical vapor deposition (CVD).
  • The present invention is described in one or more embodiments in the following description with reference to the Figures, in which like numerals represent the same or similar elements. While the invention is described in exemplary terms which include a best mode for achieving the invention's objectives, it will be appreciated by those skilled in the art that it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents as supported by the following disclosure and drawings.
  • Embodiments of the present invention provide a system for systematic exploration of plasma treatment process variables in a combinatorial manner with the possibility of performing many variations on a single substrate. The combinatorial processing permits a single substrate to be systematically explored using different plasma processing conditions, and reduces or eliminates variables that interfere with research quality. The apparatuses and methods disclosed herein permit the systematic exploration of plasma treatments on a single substrate using combinatorial methods, and removes the run to run variability and inconsistencies between substrates that hamper research and optimization of process variables.
  • FIG. 1 illustrates a schematic diagram, 100, for implementing combinatorial processing and evaluation using primary, secondary, and tertiary screening. The schematic diagram, 100, illustrates that the relative number of combinatorial processes run with a group of substrates decreases as certain materials and/or processes are selected. Generally, combinatorial processing includes performing a large number of processes during a primary screen, selecting promising candidates from those processes, performing the selected processing during a secondary screen, selecting promising candidates from the secondary screen for a tertiary screen, and so on. In addition, feedback from later stages to earlier stages can be used to refine the success criteria and provide better screening results.
  • For example, thousands of materials are evaluated during a materials discovery stage, 102. Materials discovery stage, 102, is also known as a primary screening stage performed using primary screening techniques. Primary screening techniques may include dividing substrates into coupons and depositing materials using varied processes. The materials are then evaluated, and promising candidates are advanced to the secondary screen, or materials and process development stage, 104. Evaluation of the materials is performed using metrology tools such as electronic testers and imaging tools (i.e., microscopes).
  • The materials and process development stage, 104, may evaluate hundreds of materials (i.e., a magnitude smaller than the primary stage) and may focus on the processes used to deposit or develop those materials. Promising materials and processes are again selected, and advanced to the tertiary screen or process integration stage, 106, where tens of materials and/or processes and combinations are evaluated. The tertiary screen or process integration stage, 106, may focus on integrating the selected processes and materials with other processes and materials.
  • The most promising materials and processes from the tertiary screen are advanced to device qualification, 108. In device qualification, the materials and processes selected are evaluated for high volume manufacturing, which normally is conducted on full substrates within production tools, but need not be conducted in such a manner. The results are evaluated to determine the efficacy of the selected materials and processes. If successful, the use of the screened materials and processes can proceed to pilot manufacturing, 110.
  • The schematic diagram, 100, is an example of various techniques that may be used to evaluate and select materials and processes for the development of new materials and processes. The descriptions of primary, secondary, etc. screening and the various stages, 102-110, are arbitrary and the stages may overlap, occur out of sequence, be described and be performed in many other ways.
  • This application benefits from High Productivity Combinatorial (HPC) techniques described in U.S. patent application Ser. No. 11/674,137 filed on Feb. 12, 2007 which is hereby incorporated for reference in its entirety. Portions of the '137 application have been reproduced below to enhance the understanding of the present invention.
  • While the combinatorial processing varies certain materials, hardware details, or process sequences, the composition or thickness of the layers or structures or the actions, such as cleaning, surface preparation, deposition, surface treatment, etc. is substantially uniform through each discrete region. Furthermore, while different materials or processes may be used for corresponding layers or steps in the formation of a structure in different regions of the substrate during the combinatorial processing, the application of each layer or use of a given process is substantially consistent or uniform throughout the different regions in which it is intentionally applied. Thus, the processing is uniform within a region (inter-region uniformity) and between regions (intra-region uniformity), as desired. It should be noted that the process can be varied between regions, for example, where a thickness of a layer is varied or a material may be varied between the regions, etc., as desired by the design of the experiment.
  • The result is a series of regions on the substrate that contain structures or unit process sequences that have been uniformly applied within that region and, as applicable, across different regions. This process uniformity allows comparison of the properties within and across the different regions such that the variations in test results are due to the varied parameter (e.g., materials, unit processes, unit process parameters, hardware details, or process sequences) and not the lack of process uniformity. In the embodiments described herein, the positions of the discrete regions on the substrate can be defined as needed, but are preferably systematized for ease of tooling and design of experimentation. In addition, the number, variants and location of structures within each region are designed to enable valid statistical analysis of the test results within each region and across regions to be performed.
  • FIG. 2 is a simplified schematic diagram illustrating a general methodology for combinatorial process sequence integration that includes site-isolated processing and/or conventional processing in accordance with one embodiment of the invention. In one embodiment, the substrate is initially processed using conventional process N. In one exemplary embodiment, the substrate is then processed using site-isolated process N+1. During site-isolated processing, an HPC module may be used, such as the HPC module described in U.S. patent application Ser. No. 11/352,077 filed on Feb. 10, 2006. The substrate can then be processed using site-isolated process N+2, and thereafter processed using conventional process N+3. Testing is performed and the results are evaluated. The testing can include physical, chemical, acoustic, magnetic, electrical, optical, etc. tests. From this evaluation, a particular process from the various site-isolated processes (e.g. from steps N+1 and N+2) may be selected and fixed so that additional combinatorial process sequence integration may be performed using site-isolated processing for either process N or N+3. For example, a next process sequence can include processing the substrate using site-isolated process N, conventional processing for processes N+1, N+2, and N+3, with testing performed thereafter.
  • It should be appreciated that various other combinations of conventional and combinatorial processes can be included in the processing sequence with regard to FIG. 2. That is, the combinatorial process sequence integration can be applied to any desired segments and/or portions of an overall process flow. Characterization, including physical, chemical, acoustic, magnetic, electrical, optical, etc. testing, can be performed after each process operation, and/or series of process operations within the process flow as desired. The feedback provided by the testing is used to select certain materials, processes, process conditions, and process sequences and eliminate others. Furthermore, the above process flows can be applied to entire monolithic substrates, or portions of the monolithic substrates.
  • Under combinatorial processing operations the processing conditions at different regions can be controlled independently. Consequently, process material amounts, reactant species, processing temperatures, processing times, processing pressures, processing flow rates, processing powers, processing reagent compositions, the rates at which the reactions are quenched, deposition order of process materials, process sequence steps, hardware details, etc., can be varied from region to region on the substrate. Thus, for example, when exploring materials, a processing material delivered to a first and second region can be the same or different. If the processing material delivered to the first region is the same as the processing material delivered to the second region, this processing material can be offered to the first and second regions on the substrate at different concentrations. In addition, the material can be deposited under different processing parameters. Parameters which can be varied include, but are not limited to, process material amounts, reactant species, processing temperatures, processing times, processing pressures, processing flow rates, processing powers, processing reagent compositions, the rates at which the reactions are quenched, atmospheres in which the processes are conducted, the order in which materials are deposited, hardware details of the gas distribution assembly, etc. It should be appreciated that these process parameters are exemplary and not meant to be an exhaustive list as other process parameters commonly used with plasma exposure systems may be varied.
  • As mentioned above, within a region, the process conditions are substantially uniform, in contrast to gradient processing techniques which rely on the inherent non-uniformity of the material deposition. That is, the embodiments, described herein locally perform the processing in a conventional manner, e.g., substantially consistent and substantially uniform, while globally over the substrate, the materials, processes, and process sequences may vary. Thus, the testing will find optimums without interference from process variation differences between processes that are meant to be the same. It should be appreciated that a region may be adjacent to another region in one embodiment or the regions may be isolated and, therefore, non-overlapping. When the regions are adjacent, there may be a slight overlap wherein the materials or precise process interactions are not known, however, a portion of the regions, normally at least 50% or more of the area, is uniform and all testing occurs within that region. Further, the potential overlap is only allowed with material of processes that will not adversely affect the result of the tests. Both types of regions are referred to herein as regions or discrete regions.
  • Substrates may be a conventional round 200 mm, 300 mm, or any other larger or smaller substrate/wafer size. In other embodiments, substrates may be square, rectangular, or other shape. One skilled in the art will appreciate that substrate may be a blanket substrate, a coupon (e.g., partial wafer), or even a patterned substrate having predefined regions. In some embodiments, a substrate may have regions defined through the processing described herein.
  • Software is provided to control the process parameters for each wafer for the combinatorial processing. The process parameters comprise selection of one or more source gases for the plasma generator, plasma filtering parameters, exposure time, substrate temperature, power, frequency, plasma generation method, substrate bias, pressure, gas flow, or combinations thereof.
  • FIG. 3 is a simplified schematic diagram illustrating an integrated high productivity combinatorial (HPC) system in accordance with some embodiments of the invention. The HPC system includes a frame 300 supporting a plurality of processing modules. It will be appreciated that frame 300 may be a unitary frame in accordance with some embodiments. In some embodiments, the environment within frame 300 is controlled. A load lock 302 provides access into the plurality of modules of the HPC system. A robot 314 provides for the movement of substrates (and masks) between the modules and for the movement into and out of the load lock 302. Modules 304-312 may be any set of modules and preferably include one or more combinatorial modules. For example, module 304 may be an orientation/degassing module, module 306 may be a clean module, either plasma or non-plasma based, modules 308 and/or 310 may be combinatorial/conventional dual purpose modules. Module 312 may provide conventional clean or degas as necessary for the experiment design.
  • Any type of chamber or combination of chambers may be implemented and the description herein is merely illustrative of one possible combination and not meant to limit the potential chamber or processes that can be supported to combine combinatorial processing or combinatorial plus conventional processing of a substrate or wafer. In some embodiments, a centralized controller, i.e., computing device 316, may control the processes of the HPC system. Further details of one possible HPC system are described in U.S. application Ser. Nos. 11/672,478 and 11/672,473, the entire disclosures of which are herein incorporated by reference. In a HPC system, a plurality of methods may be employed to deposit material upon a substrate employing combinatorial processes.
  • Degas processes are used in several stages or steps during the manufacture of semiconductor, optoelectronic, and thin film photovoltaic devices. The degas process may be used as a thermal treatment, wherein the substrate is heated in an inert atmosphere. As discussed previously, current degas systems are designed to produce a uniform temperature across the entire surface of the substrate using resistive heating. However, the substrates often include temperature sensitive materials or structures (e.g. dopant implants) that constrain the maximum temperature and/or the thermal budget for the device. Yet, adsorbed species such as water vapor and/or contaminants must be removed from the surface of the substrate before subsequent deposition processes to ensure a clean interface and good device performance. Degas processes are needed for both conventional and high productivity combinatorial processing flows.
  • Microwave radiation is generally understood to refer to electromagnetic waves with frequencies between 300 MHz and 300 GHz. Government regulations limit industrial and medical application frequencies to 27.12 MHz, 915 MHz, and 2.45 GHz. Typical heating applications use microwave radiation with frequencies of 2.45 GHz so that they do not interfere with telecommunications and cellular phone frequencies. Microwave radiation with frequencies of 2.45 GHz has energies of about 0.0016 eV. Clearly these energy levels are not high enough to directly break chemical bonds. As an example, Van der Waals bonds have typical energies of about 0.044 eV, hydrogen bonds have typical energies of about 0.2 eV, ionic bonds have typical energies of about 0.17 to 0.3 eV, and single covalent bonds have typical energies of about 2 to 5 eV. Therefore, the microwave radiation cannot directly induce chemical reactions.
  • The microwave radiation will interact with dipoles formed by chemical bonding and interactions of adsorbed species with surfaces. As the dipoles are exposed to the microwave radiation, they will attempt to align with the oscillating electric field. In condensed phases (e.g. liquids and solids), steric hindrance prevents the dipoles from efficiently following the oscillating electric field, causing a phase delay between the electric field and the dipole alignment. This phase delay causes energy, in the form of heat, to be lost from the dipole by molecular friction and collisions. The increase in temperature is sufficient to overcome the bonding between the adsorbed species (e.g. water vapor, organic vapors, volatile contaminants, etc.) and the surface. In this manner, the adsorbed species can be removed from the surface without degrading the performance of temperature sensitive materials or structures that may be formed on the substrate. Those skilled in the art will understand that the substrate and bulk materials formed on the substrate interact only very weakly with the microwave radiation due to the absence of strong dipoles (e.g. the bonding is largely symmetric within the substrate and bulk materials). The efficacy of the microwave degas process may be influenced by process parameters such as power, dwell time, frequency, backside cooling gas usage, backside cooling gas flow rate.
  • FIG. 4 presents a flow chart illustrating the steps of methods according to some embodiments. In step 400, a substrate is provided to a degas module of a cluster system as described previously, or to some other suitably equipped chamber. The substrate may be one of silicon, germanium, silicon-germanium alloy, silica, sapphire, zinc oxide, silicon carbide, aluminum nitride, gallium nitride, Spinel, coated silicon, silicon on oxide, silicon carbide on oxide, glass, gallium arsenide, indium phosphide, and combinations (or alloys) thereof. Typically, the substrate will have gases and/or contaminant species adsorbed on the surface. Typical gases and/or contaminant species include water vapor, organic vapors, volatile contaminants, etc.
  • In step 402, the substrate is exposed to microwave radiation. Typically, the microwave radiation is generated in a remote source and is delivered to the degas module using a wave guide. In some embodiments, the frequency of the microwave radiation is varied in a continuous manner during the exposing so that localized hot spots do not form on isolated portions of the substrate. The frequency of the microwave electromagnetic radiation can be varied in a range around 2.45 GHz. In some embodiments, the backside of the substrate may be heated to further enhance the degas process. In some embodiments, the backside of the substrate may be cooled to further protect temperature sensitive materials and/or structures on the substrate during the degas process. The methods allow process variables such as power, dwell time, frequency, backside cooling gas usage, backside cooling gas flow rate, and the like to be varied to improve the degas process performance.
  • In step 404, the substrate is transported to another process module if necessary for subsequent processing. The transport typically occurs under vacuum within a cluster system (e.g. as discussed previously) or similar controlled environment so that additional water vapor and other contaminants do not adsorb on the degassed surface. Typical subsequent processes include surface treatment processes and deposition processes. The surface treatment processes may be one or more of plasma surface treatment or thermal surface treatment. The deposition processes may be one or more of atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), pulsed laser deposition (PLD), or molecular beam epitaxy (MBE).
  • FIG. 5 illustrates a first process chamber enabling degas processing using microwave radiation. The first process chamber includes a substrate support, 502, used to support a substrate, 500. The substrate support may include the capability of active heating and/or cooling. The substrate support is contained within a processing chamber, 504. Typically, the processing chamber is held at a pressure between 1 mTorr and 760 Torr during the degas process. An ancillary structure, 506, houses a remote microwave source, 508. The remote microwave source, 508, is operable to generate microwave radiation at a frequency of about 2.45 GHz. In some embodiments, the frequency of the microwave radiation is varied in a continuous manner (e.g. in a frequency range centered around 2.45 GHz) during the exposing so that localized hot spots do not form on isolated portions of the substrate. The microwave radiation is delivered to the process chamber using a waveguide, 510. In some embodiments, the waveguide includes a section of bellows, thus allowing the distance from the process chamber to the ancillary structure to be adjusted. The microwave radiation is delivered to the surface of the substrate through delivery nozzle, 512. The microwave radiation may irradiate the entire substrate or may irradiate a portion of the substrate. In embodiments where the microwave radiation irradiates only portions of the surface of the substrate, the substrate may be moved (e.g. rotated and/or translated) so that the entire surface may be exposed to the microwave radiation at some time during the degas process. The first process chamber allows process variables such as power, dwell time, frequency, backside cooling gas usage, backside cooling gas flow rate, and the like to be varied to improve the degas process performance.
  • In some embodiments, a second process chamber (not shown) is used to apply a subsequent process to the surface of the substrate after the degas process. As discussed previously with reference to FIG. 3, the substrate may be transported to the second process chamber by a robot (not shown in FIG. 5).
  • Although the foregoing examples have been described in some detail for purposes of clarity of understanding, the invention is not limited to the details provided. There are many alternative ways of implementing the invention. The disclosed examples are illustrative and not restrictive.

Claims (20)

What is claimed:
1. A method for processing a substrate, the method comprising
transferring a substrate into a first process chamber;
exposing a surface of the substrate to microwave radiation, wherein the microwave radiation has a frequency of about 2.45 GHz;
after the exposing, transferring the substrate to a second process chamber; and
after the transferring, processing the substrate.
2. The method of claim 1, wherein the frequency of the microwave radiation is varied in a continuous manner around 2.45 GHz during the exposing.
3. The method of claim 1, wherein the substrate comprises one of silicon, germanium, silicon-germanium alloy, silica, sapphire, zinc oxide, silicon carbide, aluminum nitride, gallium nitride, Spinel, coated silicon, silicon on oxide, silicon carbide on oxide, glass, gallium arsenide, indium phosphide, and combinations (or alloys) thereof.
4. The method of claim 1, further comprising heating a backside of the substrate during the exposing.
5. The method of claim 1, further comprising cooling a backside of the substrate during the exposing.
6. The method of claim 1, wherein a pressure within the first process chamber during the exposing is between 1 mTorr and 760 Torr.
7. The method of claim 1, wherein processing the substrate comprises a surface treatment process.
8. The method of claim 7, wherein processing the substrate comprises a plasma treatment process.
9. The method of claim 7, wherein processing the substrate comprises a thermal treatment process.
10. The method of claim 1, wherein processing the substrate comprises a deposition process.
11. The method of claim 10, wherein the processing the substrate comprises one of atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), pulsed laser deposition (PLD), or molecular beam epitaxy (MBE).
12. The method of claim 1, wherein processing the substrate comprises one of a conventional process or a high productivity combinatorial process.
13. An apparatus comprising:
a first process chamber;
a remote microwave source;
a waveguide, wherein the waveguide is operable to deliver microwave radiation from the remote microwave source to the first process chamber;
a substrate support; and
a delivery nozzle, wherein the delivery nozzle is operable to deliver microwave radiation from the waveguide to a surface of a substrate disposed upon the substrate support.
14. The apparatus of claim 13, wherein the remote microwave source generates microwave radiation having a frequency of about 2.45 GHz.
15. The apparatus of claim 13, further comprising a second process chamber.
16. The apparatus of claim 15, further comprising a robot, wherein the robot is operable to transport the substrate from the first process chamber to the second process chamber.
17. The apparatus of claim 15, wherein the second process chamber is operable to apply a plasma surface treatment to the substrate.
18. The apparatus of claim 15, wherein the second process chamber is operable to apply a thermal surface treatment to the substrate.
19. The apparatus of claim 15, wherein the second process chamber is operable to apply a deposition process to the substrate.
20. The apparatus of claim 19, wherein the deposition process comprises one of atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), pulsed laser deposition (PLD), or molecular beam epitaxy (MBE).
US14/091,854 2013-03-13 2013-11-27 Advanced Targeted Microwave Degas System Abandoned US20140273404A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/091,854 US20140273404A1 (en) 2013-03-13 2013-11-27 Advanced Targeted Microwave Degas System

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201361779740P 2013-03-13 2013-03-13
US14/091,854 US20140273404A1 (en) 2013-03-13 2013-11-27 Advanced Targeted Microwave Degas System

Publications (1)

Publication Number Publication Date
US20140273404A1 true US20140273404A1 (en) 2014-09-18

Family

ID=51523560

Family Applications (7)

Application Number Title Priority Date Filing Date
US14/019,961 Abandoned US20140273525A1 (en) 2013-03-13 2013-09-06 Atomic Layer Deposition of Reduced-Leakage Post-Transition Metal Oxide Films
US14/031,975 Expired - Fee Related US8987143B2 (en) 2013-03-13 2013-09-19 Hydrogen plasma cleaning of germanium oxide surfaces
US14/091,854 Abandoned US20140273404A1 (en) 2013-03-13 2013-11-27 Advanced Targeted Microwave Degas System
US14/135,431 Expired - Fee Related US9076641B2 (en) 2013-03-13 2013-12-19 Ultra-low resistivity contacts
US14/137,183 Abandoned US20140264281A1 (en) 2013-03-13 2013-12-20 Channel-Last Methods for Making FETS
US14/137,866 Abandoned US20140264507A1 (en) 2013-03-13 2013-12-20 Fluorine Passivation in CMOS Image Sensors
US14/721,248 Abandoned US20150255332A1 (en) 2013-03-13 2015-05-26 Ultra-Low Resistivity Contacts

Family Applications Before (2)

Application Number Title Priority Date Filing Date
US14/019,961 Abandoned US20140273525A1 (en) 2013-03-13 2013-09-06 Atomic Layer Deposition of Reduced-Leakage Post-Transition Metal Oxide Films
US14/031,975 Expired - Fee Related US8987143B2 (en) 2013-03-13 2013-09-19 Hydrogen plasma cleaning of germanium oxide surfaces

Family Applications After (4)

Application Number Title Priority Date Filing Date
US14/135,431 Expired - Fee Related US9076641B2 (en) 2013-03-13 2013-12-19 Ultra-low resistivity contacts
US14/137,183 Abandoned US20140264281A1 (en) 2013-03-13 2013-12-20 Channel-Last Methods for Making FETS
US14/137,866 Abandoned US20140264507A1 (en) 2013-03-13 2013-12-20 Fluorine Passivation in CMOS Image Sensors
US14/721,248 Abandoned US20150255332A1 (en) 2013-03-13 2015-05-26 Ultra-Low Resistivity Contacts

Country Status (2)

Country Link
US (7) US20140273525A1 (en)
WO (2) WO2014160467A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI667721B (en) * 2014-12-11 2019-08-01 瑞士商艾維太克股份有限公司 Thermal treatment chamber, apparatus comprising such a chamber and method of manufacturing thermally treated workpieces
US11776825B2 (en) 2016-03-08 2023-10-03 Evatec Ag Chamber for degassing substrates

Families Citing this family (96)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140034632A1 (en) * 2012-08-01 2014-02-06 Heng Pan Apparatus and method for selective oxidation at lower temperature using remote plasma source
US9132436B2 (en) 2012-09-21 2015-09-15 Applied Materials, Inc. Chemical control features in wafer process equipment
US10256079B2 (en) 2013-02-08 2019-04-09 Applied Materials, Inc. Semiconductor processing systems having multiple plasma configurations
US9362130B2 (en) 2013-03-01 2016-06-07 Applied Materials, Inc. Enhanced etching processes using remote plasma sources
US20150024152A1 (en) 2013-07-19 2015-01-22 Agilent Technologies, Inc. Metal components with inert vapor phase coating on internal surfaces
US10767259B2 (en) 2013-07-19 2020-09-08 Agilent Technologies, Inc. Components with an atomic layer deposition coating and methods of producing the same
US20150093887A1 (en) * 2013-10-02 2015-04-02 GlobalFoundries, Inc. Methods for removing a native oxide layer from germanium susbtrates in the fabrication of integrated circuitsi
US20150093889A1 (en) * 2013-10-02 2015-04-02 Intermolecular Methods for removing a native oxide layer from germanium susbtrates in the fabrication of integrated circuits
US9224594B2 (en) * 2013-11-18 2015-12-29 Intermolecular, Inc. Surface preparation with remote plasma
US9299557B2 (en) 2014-03-19 2016-03-29 Asm Ip Holding B.V. Plasma pre-clean module and process
US20150270134A1 (en) * 2014-03-19 2015-09-24 Qualcomm Incorporated Methods of forming a metal-insulator-semiconductor (mis) structure and a dual contact device
US9324804B2 (en) * 2014-03-21 2016-04-26 Wisconsin Alumni Research Foundation Graphene-on-semiconductor substrates for analog electronics
US9309598B2 (en) 2014-05-28 2016-04-12 Applied Materials, Inc. Oxide and metal removal
US9287359B1 (en) 2014-09-15 2016-03-15 Wisconsin Alumni Research Foundation Oriented bottom-up growth of armchair graphene nanoribbons on germanium
US9355922B2 (en) 2014-10-14 2016-05-31 Applied Materials, Inc. Systems and methods for internal surface conditioning in plasma processing equipment
US9966240B2 (en) 2014-10-14 2018-05-08 Applied Materials, Inc. Systems and methods for internal surface conditioning assessment in plasma processing equipment
US11637002B2 (en) 2014-11-26 2023-04-25 Applied Materials, Inc. Methods and systems to enhance process uniformity
US10573496B2 (en) 2014-12-09 2020-02-25 Applied Materials, Inc. Direct outlet toroidal plasma source
US9474163B2 (en) * 2014-12-30 2016-10-18 Asm Ip Holding B.V. Germanium oxide pre-clean module and process
US11257693B2 (en) 2015-01-09 2022-02-22 Applied Materials, Inc. Methods and systems to improve pedestal temperature control
CN112575313A (en) * 2015-01-14 2021-03-30 安捷伦科技有限公司 Component with atomic layer deposition coating and method of making the same
US20160225652A1 (en) 2015-02-03 2016-08-04 Applied Materials, Inc. Low temperature chuck for plasma processing systems
US9728437B2 (en) 2015-02-03 2017-08-08 Applied Materials, Inc. High temperature chuck for plasma processing systems
US10373850B2 (en) 2015-03-11 2019-08-06 Asm Ip Holding B.V. Pre-clean chamber and process with substrate tray for changing substrate temperature
EP3326203B1 (en) 2015-07-24 2024-03-06 Artilux, Inc. Multi-wafer based light absorption apparatus and applications thereof
US10644187B2 (en) * 2015-07-24 2020-05-05 Artilux, Inc. Multi-wafer based light absorption apparatus and applications thereof
US9691645B2 (en) 2015-08-06 2017-06-27 Applied Materials, Inc. Bolted wafer chuck thermal management systems and methods for wafer processing systems
US9741593B2 (en) 2015-08-06 2017-08-22 Applied Materials, Inc. Thermal management systems and methods for wafer processing systems
US9349605B1 (en) 2015-08-07 2016-05-24 Applied Materials, Inc. Oxide etch selectivity systems and methods
US10504700B2 (en) 2015-08-27 2019-12-10 Applied Materials, Inc. Plasma etching systems and methods with secondary plasma injection
US9484255B1 (en) 2015-11-03 2016-11-01 International Business Machines Corporation Hybrid source and drain contact formation using metal liner and metal insulator semiconductor contacts
US9595449B1 (en) * 2015-12-21 2017-03-14 International Business Machines Corporation Silicon-germanium semiconductor devices and method of making
US9627615B1 (en) * 2016-01-26 2017-04-18 Arm Ltd. Fabrication of correlated electron material devices
JP6827633B2 (en) * 2016-03-02 2021-02-10 東京エレクトロン株式会社 Etching with adjustable selectivity of isotropic silicon and silicon germanium
CA3023259A1 (en) * 2016-05-05 2017-11-09 Veloce Biopharma, Llc Compositions and methods for treatment of inflammation or infection of the eye
US10522371B2 (en) 2016-05-19 2019-12-31 Applied Materials, Inc. Systems and methods for improved semiconductor etching and component protection
US10504754B2 (en) 2016-05-19 2019-12-10 Applied Materials, Inc. Systems and methods for improved semiconductor etching and component protection
US11222959B1 (en) * 2016-05-20 2022-01-11 Hrl Laboratories, Llc Metal oxide semiconductor field effect transistor and method of manufacturing same
US9865484B1 (en) 2016-06-29 2018-01-09 Applied Materials, Inc. Selective etch using material modification and RF pulsing
US9761669B1 (en) 2016-07-18 2017-09-12 Wisconsin Alumni Research Foundation Seed-mediated growth of patterned graphene nanoribbon arrays
US10269714B2 (en) 2016-09-06 2019-04-23 International Business Machines Corporation Low resistance contacts including intermetallic alloy of nickel, platinum, titanium, aluminum and type IV semiconductor elements
US10629473B2 (en) 2016-09-09 2020-04-21 Applied Materials, Inc. Footing removal for nitride spacer
US9934942B1 (en) 2016-10-04 2018-04-03 Applied Materials, Inc. Chamber with flow-through source
US10546729B2 (en) 2016-10-04 2020-01-28 Applied Materials, Inc. Dual-channel showerhead with improved profile
US10062579B2 (en) 2016-10-07 2018-08-28 Applied Materials, Inc. Selective SiN lateral recess
US10163696B2 (en) 2016-11-11 2018-12-25 Applied Materials, Inc. Selective cobalt removal for bottom up gapfill
US10026621B2 (en) 2016-11-14 2018-07-17 Applied Materials, Inc. SiN spacer profile patterning
US10566206B2 (en) 2016-12-27 2020-02-18 Applied Materials, Inc. Systems and methods for anisotropic material breakthrough
US10431429B2 (en) 2017-02-03 2019-10-01 Applied Materials, Inc. Systems and methods for radial and azimuthal control of plasma uniformity
US10319739B2 (en) 2017-02-08 2019-06-11 Applied Materials, Inc. Accommodating imperfectly aligned memory holes
US10943834B2 (en) 2017-03-13 2021-03-09 Applied Materials, Inc. Replacement contact process
US10319649B2 (en) 2017-04-11 2019-06-11 Applied Materials, Inc. Optical emission spectroscopy (OES) for remote plasma monitoring
US11276590B2 (en) 2017-05-17 2022-03-15 Applied Materials, Inc. Multi-zone semiconductor substrate supports
US11276559B2 (en) 2017-05-17 2022-03-15 Applied Materials, Inc. Semiconductor processing chamber for multiple precursor flow
KR102398688B1 (en) 2017-05-26 2022-05-16 주식회사 디비하이텍 Image sensor and method of manufacturing the same
US10497579B2 (en) 2017-05-31 2019-12-03 Applied Materials, Inc. Water-free etching methods
CN107248496B (en) * 2017-06-07 2019-11-15 西安电子科技大学 Correction method of sheet resistance in ohmic contact area
US10920320B2 (en) 2017-06-16 2021-02-16 Applied Materials, Inc. Plasma health determination in semiconductor substrate processing reactors
US10541246B2 (en) 2017-06-26 2020-01-21 Applied Materials, Inc. 3D flash memory cells which discourage cross-cell electrical tunneling
US10727080B2 (en) 2017-07-07 2020-07-28 Applied Materials, Inc. Tantalum-containing material removal
US10541184B2 (en) 2017-07-11 2020-01-21 Applied Materials, Inc. Optical emission spectroscopic techniques for monitoring etching
US10043674B1 (en) 2017-08-04 2018-08-07 Applied Materials, Inc. Germanium etching systems and methods
US10297458B2 (en) 2017-08-07 2019-05-21 Applied Materials, Inc. Process window widening using coated parts in plasma etch processes
US10283324B1 (en) * 2017-10-24 2019-05-07 Applied Materials, Inc. Oxygen treatment for nitride etching
US10424487B2 (en) 2017-10-24 2019-09-24 Applied Materials, Inc. Atomic layer etching processes
KR102018075B1 (en) * 2017-11-30 2019-09-04 무진전자 주식회사 Dry clean apparatus and method for removing polysilicon seletively
US10903054B2 (en) 2017-12-19 2021-01-26 Applied Materials, Inc. Multi-zone gas distribution systems and methods
US11328909B2 (en) 2017-12-22 2022-05-10 Applied Materials, Inc. Chamber conditioning and removal processes
US10290719B1 (en) 2017-12-27 2019-05-14 International Business Machines Corporation Indium gallium arsenide metal oxide semiconductor field effect transistor having a low contact resistance to metal electrode
US10854426B2 (en) 2018-01-08 2020-12-01 Applied Materials, Inc. Metal recess for semiconductor structures
US10679870B2 (en) 2018-02-15 2020-06-09 Applied Materials, Inc. Semiconductor processing chamber multistage mixing apparatus
US10964512B2 (en) 2018-02-15 2021-03-30 Applied Materials, Inc. Semiconductor processing chamber multistage mixing apparatus and methods
TWI716818B (en) 2018-02-28 2021-01-21 美商應用材料股份有限公司 Systems and methods to form airgaps
US10593560B2 (en) 2018-03-01 2020-03-17 Applied Materials, Inc. Magnetic induction plasma source for semiconductor processes and equipment
US10319600B1 (en) 2018-03-12 2019-06-11 Applied Materials, Inc. Thermal silicon etch
US10497573B2 (en) 2018-03-13 2019-12-03 Applied Materials, Inc. Selective atomic layer etching of semiconductor materials
US10573527B2 (en) 2018-04-06 2020-02-25 Applied Materials, Inc. Gas-phase selective etching systems and methods
US10490406B2 (en) 2018-04-10 2019-11-26 Appled Materials, Inc. Systems and methods for material breakthrough
US10699879B2 (en) 2018-04-17 2020-06-30 Applied Materials, Inc. Two piece electrode assembly with gap for plasma control
US10886137B2 (en) 2018-04-30 2021-01-05 Applied Materials, Inc. Selective nitride removal
US10755941B2 (en) 2018-07-06 2020-08-25 Applied Materials, Inc. Self-limiting selective etching systems and methods
US10872778B2 (en) 2018-07-06 2020-12-22 Applied Materials, Inc. Systems and methods utilizing solid-phase etchants
US10672642B2 (en) 2018-07-24 2020-06-02 Applied Materials, Inc. Systems and methods for pedestal configuration
US11049755B2 (en) 2018-09-14 2021-06-29 Applied Materials, Inc. Semiconductor substrate supports with embedded RF shield
US10892198B2 (en) 2018-09-14 2021-01-12 Applied Materials, Inc. Systems and methods for improved performance in semiconductor processing
US11062887B2 (en) 2018-09-17 2021-07-13 Applied Materials, Inc. High temperature RF heater pedestals
US11417534B2 (en) 2018-09-21 2022-08-16 Applied Materials, Inc. Selective material removal
US11682560B2 (en) 2018-10-11 2023-06-20 Applied Materials, Inc. Systems and methods for hafnium-containing film removal
US11121002B2 (en) 2018-10-24 2021-09-14 Applied Materials, Inc. Systems and methods for etching metals and metal derivatives
US11437242B2 (en) 2018-11-27 2022-09-06 Applied Materials, Inc. Selective removal of silicon-containing materials
US11088028B2 (en) * 2018-11-30 2021-08-10 Taiwan Semiconductor Manufacturing Company, Ltd. Fin field-effect transistor device and method of forming the same
US11721527B2 (en) 2019-01-07 2023-08-08 Applied Materials, Inc. Processing chamber mixing systems
US10920319B2 (en) 2019-01-11 2021-02-16 Applied Materials, Inc. Ceramic showerheads with conductive electrodes
CN112986357A (en) * 2019-12-13 2021-06-18 成都今是科技有限公司 Microelectrode of gene sequencing chip, preparation method thereof and gene sequencing chip
WO2022098517A1 (en) * 2020-11-03 2022-05-12 Tokyo Electron Limited Method for filling recessed features in semiconductor devices with a low-resistivity metal
US11618681B2 (en) 2021-06-28 2023-04-04 Wisconsin Alumni Research Foundation Graphene nanoribbons grown from aromatic molecular seeds

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030232501A1 (en) * 2002-06-14 2003-12-18 Kher Shreyas S. Surface pre-treatment for enhancement of nucleation of high dielectric constant materials
US6714300B1 (en) * 1998-09-28 2004-03-30 Therma-Wave, Inc. Optical inspection equipment for semiconductor wafers with precleaning
US7892985B1 (en) * 2005-11-15 2011-02-22 Novellus Systems, Inc. Method for porogen removal and mechanical strength enhancement of low-k carbon doped silicon oxide using low thermal budget microwave curing

Family Cites Families (82)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3676756A (en) * 1969-09-18 1972-07-11 Innotech Corp Insulated gate field effect device having glass gate insulator
GB1417085A (en) * 1973-05-17 1975-12-10 Standard Telephones Cables Ltd Plasma etching
US4361461A (en) 1981-03-13 1982-11-30 Bell Telephone Laboratories, Incorporated Hydrogen etching of semiconductors and oxides
US4675073A (en) * 1986-03-07 1987-06-23 Texas Instruments Incorporated Tin etch process
US5116679A (en) * 1988-07-29 1992-05-26 Alcan International Limited Process for producing fibres composed of or coated with carbides or nitrides
KR0144932B1 (en) * 1995-01-26 1998-07-01 김광호 Capacitor of semiconductor device and manufacturing method thereof
US6020243A (en) * 1997-07-24 2000-02-01 Texas Instruments Incorporated Zirconium and/or hafnium silicon-oxynitride gate dielectric
US7012292B1 (en) * 1998-11-25 2006-03-14 Advanced Technology Materials, Inc Oxidative top electrode deposition process, and microelectronic device structure
US7053002B2 (en) * 1998-12-04 2006-05-30 Applied Materials, Inc Plasma preclean with argon, helium, and hydrogen gases
JP2002016248A (en) * 2000-06-30 2002-01-18 Mitsubishi Electric Corp Method for manufacturing semiconductor device
US6613695B2 (en) * 2000-11-24 2003-09-02 Asm America, Inc. Surface preparation prior to deposition
US6900498B2 (en) * 2001-05-08 2005-05-31 Advanced Technology Materials, Inc. Barrier structures for integration of high K oxides with Cu and Al electrodes
CN100468638C (en) * 2001-12-18 2009-03-11 松下电器产业株式会社 Manufacturing method of semiconductor element
DE10221503A1 (en) * 2002-05-14 2003-11-27 Infineon Technologies Ag Metal object intended for at least partial coating with a substance
US6804136B2 (en) * 2002-06-21 2004-10-12 Micron Technology, Inc. Write once read only memory employing charge trapping in insulators
JP2004186567A (en) * 2002-12-05 2004-07-02 Toshiba Corp Semiconductor device and method of manufacturing semiconductor device
US6756291B1 (en) * 2003-01-24 2004-06-29 Taiwan Semiconductor Manufacturing Co., Ltd Method for hardening gate oxides using gate etch process
CN1841675A (en) * 2003-02-12 2006-10-04 松下电器产业株式会社 Manufacturing method of semiconductor device
CN101457338B (en) 2003-02-14 2011-04-27 应用材料股份有限公司 Cleaning of native oxide with hydrogen-containing radicals
JP4315701B2 (en) * 2003-02-25 2009-08-19 シャープ株式会社 Nitride III-V compound semiconductor electrode and method for producing the same
KR100541678B1 (en) * 2003-06-30 2006-01-11 주식회사 하이닉스반도체 How to Form Metal Wiring
US6811448B1 (en) 2003-07-15 2004-11-02 Advanced Micro Devices, Inc. Pre-cleaning for silicidation in an SMOS process
US20050056219A1 (en) * 2003-09-16 2005-03-17 Tokyo Electron Limited Formation of a metal-containing film by sequential gas exposure in a batch type processing system
JP3729826B2 (en) * 2004-01-09 2005-12-21 松下電器産業株式会社 Method for manufacturing solid-state imaging device
CN1960860B (en) * 2004-02-25 2012-06-27 旭硝子北美平板玻璃公司 Heat stabilized sub-stoichiometric dielectrics
JP2005268312A (en) 2004-03-16 2005-09-29 Semiconductor Leading Edge Technologies Inc Resist removing method and semiconductor device manufactured using same
US6946368B1 (en) * 2004-03-23 2005-09-20 Applied Materials, Inc. Reduction of native oxide at germanium interface using hydrogen-based plasma
US7279413B2 (en) * 2004-06-16 2007-10-09 International Business Machines Corporation High-temperature stable gate structure with metallic electrode
US8084400B2 (en) * 2005-10-11 2011-12-27 Intermolecular, Inc. Methods for discretized processing and process sequence integration of regions of a substrate
US7465674B2 (en) * 2005-05-31 2008-12-16 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor device
JP5067158B2 (en) * 2005-07-08 2012-11-07 日本電気株式会社 Electrode structure, semiconductor element, and manufacturing method thereof
US7402534B2 (en) * 2005-08-26 2008-07-22 Applied Materials, Inc. Pretreatment processes within a batch ALD reactor
US20070107750A1 (en) 2005-11-14 2007-05-17 Sawin Herbert H Method of using NF3 for removing surface deposits from the interior of chemical vapor deposition chambers
US8772772B2 (en) * 2006-05-18 2014-07-08 Intermolecular, Inc. System and method for increasing productivity of combinatorial screening
EP1994550A4 (en) * 2006-02-10 2012-01-11 Intermolecular Inc Method and apparatus for combinatorially varying materials, unit process and process sequence
US20080087890A1 (en) * 2006-10-16 2008-04-17 Micron Technology, Inc. Methods to form dielectric structures in semiconductor devices and resulting devices
US8169078B2 (en) * 2006-12-28 2012-05-01 Renesas Electronics Corporation Electrode structure, semiconductor element, and methods of manufacturing the same
FR2913146B1 (en) * 2007-02-23 2009-05-01 Saint Gobain DISCONTINUOUS ELECTRODE, ORGANIC ELECTROLUMINESCENCE DEVICE INCORPORATING THE SAME, AND THEIR MANUFACTURING
US8344375B2 (en) * 2007-03-05 2013-01-01 Intermolecular, Inc. Nonvolatile memory elements with metal deficient resistive switching metal oxides
CN101711431B (en) * 2007-05-09 2015-11-25 分子间公司 Resistive-switching nonvolatile memory elements
KR100864932B1 (en) 2007-07-23 2008-10-22 주식회사 동부하이텍 Cleaning Method of Semiconductor Substrate
TW200929526A (en) * 2007-12-24 2009-07-01 Powerchip Semiconductor Corp Non-volatile memory and fabricating method thereof
FR2925981B1 (en) * 2007-12-27 2010-02-19 Saint Gobain CARRIER SUBSTRATE OF AN ELECTRODE, ORGANIC ELECTROLUMINESCENT DEVICE INCORPORATING IT.
US8343813B2 (en) * 2009-04-10 2013-01-01 Intermolecular, Inc. Resistive-switching memory elements having improved switching characteristics
TWI450399B (en) * 2008-07-31 2014-08-21 Semiconductor Energy Lab Semiconductor device and method of manufacturing same
US8124992B2 (en) * 2008-08-27 2012-02-28 Showa Denko K.K. Light-emitting device, manufacturing method thereof, and lamp
US8441060B2 (en) * 2008-10-01 2013-05-14 Panasonic Corporation Nonvolatile memory element and nonvolatile memory device incorporating nonvolatile memory element
KR20100101450A (en) * 2009-03-09 2010-09-17 삼성전자주식회사 Semiconductor device and associated methods of manufacture
EP2259267B1 (en) * 2009-06-02 2013-08-21 Imec Method for manufacturing a resistive switching memory cell comprising a nickel oxide layer operable at low-power and memory cells obtained thereof
US8394669B2 (en) * 2009-07-13 2013-03-12 Panasonic Corporation Resistance variable element and resistance variable memory device
CN102630341A (en) * 2009-09-17 2012-08-08 西奥尼克斯股份有限公司 Photosensitive imaging device and related method
US8476681B2 (en) * 2009-09-17 2013-07-02 Sionyx, Inc. Photosensitive imaging devices and associated methods
US8106469B2 (en) * 2010-01-14 2012-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of fluorine passivation
EP2348531B1 (en) * 2010-01-26 2021-05-26 Samsung Electronics Co., Ltd. Thin film transistor and method of manufacturing the same
US8435902B2 (en) 2010-03-17 2013-05-07 Applied Materials, Inc. Invertable pattern loading with dry etch
KR101312906B1 (en) * 2010-03-19 2013-09-30 파나소닉 주식회사 Non-volatile storage element, method of manufacturing the same, method of supporting design thereof and non-volatile storage device
US8629523B2 (en) * 2010-04-16 2014-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Inserted reflective shield to improve quantum efficiency of image sensors
JP5320601B2 (en) * 2010-04-23 2013-10-23 シャープ株式会社 Nonvolatile variable resistance element and nonvolatile semiconductor memory device
JP5186634B2 (en) * 2010-06-29 2013-04-17 シャープ株式会社 Nonvolatile semiconductor memory device
JP4948688B2 (en) * 2010-07-02 2012-06-06 パナソニック株式会社 Resistance variable nonvolatile memory element, variable resistance nonvolatile memory device, and method of manufacturing variable resistance nonvolatile memory element
US8374018B2 (en) * 2010-07-09 2013-02-12 Crossbar, Inc. Resistive memory using SiGe material
JP5148025B2 (en) * 2010-11-19 2013-02-20 パナソニック株式会社 Method for manufacturing nonvolatile semiconductor memory element
WO2012070238A1 (en) * 2010-11-24 2012-05-31 パナソニック株式会社 Nonvolatile memory element, production method therefor, nonvolatile memory unit, and design assistance method for nonvolatile memory element
JP5000027B1 (en) * 2010-12-15 2012-08-15 パナソニック株式会社 Nonvolatile memory device
US8349731B2 (en) * 2011-03-25 2013-01-08 GlobalFoundries, Inc. Methods for forming copper diffusion barriers for semiconductor interconnect structures
US8546781B2 (en) * 2011-05-31 2013-10-01 The Board Of Trustees Of The Leland Stanford Junior University Nitrogen doped aluminum oxide resistive random access memory
US20120313205A1 (en) * 2011-06-10 2012-12-13 Homayoon Haddad Photosensitive Imagers Having Defined Textures for Light Trapping and Associated Methods
US8846443B2 (en) * 2011-08-05 2014-09-30 Intermolecular, Inc. Atomic layer deposition of metal oxides for memory applications
US8659001B2 (en) * 2011-09-01 2014-02-25 Sandisk 3D Llc Defect gradient to boost nonvolatile memory performance
US8288297B1 (en) * 2011-09-01 2012-10-16 Intermolecular, Inc. Atomic layer deposition of metal oxide materials for memory applications
WO2013035327A1 (en) * 2011-09-09 2013-03-14 パナソニック株式会社 Cross-point variable resistance non-volatile storage device and writing method for same
WO2013046603A1 (en) * 2011-09-27 2013-04-04 パナソニック株式会社 Non-volatile memory element, non-volatile memory device, and method for manufacturing same
US8822265B2 (en) * 2011-10-06 2014-09-02 Intermolecular, Inc. Method for reducing forming voltage in resistive random access memory
US9082968B2 (en) * 2011-11-17 2015-07-14 Panasonic Intellectual Property Management Co., Ltd. Variable resistance non-volatile memory device and manufacturing method thereof
JP5845866B2 (en) * 2011-12-07 2016-01-20 富士通セミコンダクター株式会社 Manufacturing method of semiconductor device
US8920618B2 (en) * 2011-12-29 2014-12-30 Intermolecular, Inc. Combinatorial processing using high deposition rate sputtering
WO2013111548A1 (en) * 2012-01-23 2013-08-01 パナソニック株式会社 Nonvolatile storage element and method of manufacturing thereof
JP2013157469A (en) * 2012-01-30 2013-08-15 Sharp Corp Variable resistive element, and nonvolatile semiconductor storage device
US8569104B2 (en) * 2012-02-07 2013-10-29 Intermolecular, Inc. Transition metal oxide bilayers
US20140011339A1 (en) 2012-07-06 2014-01-09 Applied Materials, Inc. Method for removing native oxide and residue from a germanium or iii-v group containing surface
US20140124817A1 (en) * 2012-11-05 2014-05-08 Intermolecular, Inc. Contact Layers
US9331293B2 (en) * 2013-03-14 2016-05-03 Nutech Ventures Floating-gate transistor photodetector with light absorbing layer

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6714300B1 (en) * 1998-09-28 2004-03-30 Therma-Wave, Inc. Optical inspection equipment for semiconductor wafers with precleaning
US6930771B2 (en) * 1998-09-28 2005-08-16 Therma-Wave, Inc. Optical inspection equipment for semiconductor wafers with precleaning
US7068370B2 (en) * 1998-09-28 2006-06-27 Therma-Wave, Inc. Optical inspection equipment for semiconductor wafers with precleaning
US20030232501A1 (en) * 2002-06-14 2003-12-18 Kher Shreyas S. Surface pre-treatment for enhancement of nucleation of high dielectric constant materials
US7892985B1 (en) * 2005-11-15 2011-02-22 Novellus Systems, Inc. Method for porogen removal and mechanical strength enhancement of low-k carbon doped silicon oxide using low thermal budget microwave curing

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI667721B (en) * 2014-12-11 2019-08-01 瑞士商艾維太克股份有限公司 Thermal treatment chamber, apparatus comprising such a chamber and method of manufacturing thermally treated workpieces
US10403522B2 (en) 2014-12-11 2019-09-03 Evatec Ag Chamber for degassing substrates
US10580671B2 (en) 2014-12-11 2020-03-03 Evatec Ag Chamber for degassing substrates
US11776825B2 (en) 2016-03-08 2023-10-03 Evatec Ag Chamber for degassing substrates

Also Published As

Publication number Publication date
WO2014160467A1 (en) 2014-10-02
US9076641B2 (en) 2015-07-07
US8987143B2 (en) 2015-03-24
US20140264507A1 (en) 2014-09-18
US20140273525A1 (en) 2014-09-18
WO2014160460A1 (en) 2014-10-02
US20140264281A1 (en) 2014-09-18
US20140273493A1 (en) 2014-09-18
US20150255332A1 (en) 2015-09-10
US20140264825A1 (en) 2014-09-18

Similar Documents

Publication Publication Date Title
US20140273404A1 (en) Advanced Targeted Microwave Degas System
US9023438B2 (en) Methods and apparatus for combinatorial PECVD or PEALD
US8821987B2 (en) Combinatorial processing using a remote plasma source
KR102436174B1 (en) How to process the object
US20140127422A1 (en) Method and Apparatus for High-K Gate Performance Improvement and Combinatorial Processing
KR20200019983A (en) Etching Method and Etching Apparatus
KR102654243B1 (en) Eliminating first wafer metal contamination effect in high density plasma chemical vapor deposition systems
US8822313B2 (en) Surface treatment methods and systems for substrate processing
US20140069459A1 (en) Methods and apparatus for cleaning deposition chambers
US9082729B2 (en) Combinatorial method for solid source doping process development
US20200290095A1 (en) Method of forming process film
US20120315396A1 (en) Apparatus and method for combinatorial plasma distribution through a multi-zoned showerhead
US9087864B2 (en) Multipurpose combinatorial vapor phase deposition chamber
US20130153536A1 (en) Combinatorial processing using a remote plasma source
US8815012B2 (en) Emissivity profile control for thermal uniformity
US8974649B2 (en) Combinatorial RF bias method for PVD
US9023739B2 (en) Site-isolated rapid thermal processing methods and apparatus
US20130136862A1 (en) Multi-cell mocvd apparatus
KR20160030364A (en) Plasma processing apparatus and cleaning method
US9721766B2 (en) Method for processing target object
US20130153054A1 (en) Combinatorial Processing Tool
US20160189931A1 (en) Plasma processing apparatus and method for determining replacement of member of plasma processing apparatus
US20140147593A1 (en) Liquid Cooled Sputter Apertured Shields
US20140183161A1 (en) Methods and Systems for Site-Isolated Combinatorial Substrate Processing Using a Mask
US20140179095A1 (en) Methods and Systems for Controlling Gate Dielectric Interfaces of MOSFETs

Legal Events

Date Code Title Description
AS Assignment

Owner name: INTERMOLECULAR, INC., CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHILD, KENT RILEY;LE, MINH HUU;SIGNING DATES FROM 20131122 TO 20131127;REEL/FRAME:031685/0892

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION

点击 这是indexloc提供的php浏览器服务,不要输入任何密码和下载