US20140219007A1

US20140219007A1 - Dram with segmented page configuration

Info

Publication number: US20140219007A1
Application number: US13/761,996
Authority: US
Inventors: William James Dally
Original assignee: Nvidia Corp
Current assignee: Nvidia Corp
Priority date: 2013-02-07
Filing date: 2013-02-07
Publication date: 2014-08-07
Also published as: DE102013114251A1; TWI555022B; US10026468B2; US20170154667A1; TW201432697A

Abstract

This description is directed to a dynamic random access memory (DRAM) array having a plurality of rows and a plurality of columns. The array further includes a plurality of cells, each of which are associated with one of the columns and one of the rows. Each cell includes a capacitor that is selectively coupled to a bit line of its associate column so as to share charge with the bit line when the cell is selected. There is a segmented word line circuit for each row, which is controllable to cause selection of only a portion of the cells in the row.

Description

BACKGROUND

Conventional dynamic random access memory (DRAM) arrays have a large page size—the number of bits that are read into sense amplifiers during row activate operations. The large page size, typically 8,192 bits, is beneficial in that it allows the entire array to be refreshed with fewer operations. On the other hand the large page size can result in considerable wasted energy. One example of unnecessary energy expenditure is a read operation in which, as typically is the case, only a small number (4-32) of the bits in the page are of interest. Despite this, all of the bit lines in the page are charged and discharged to perform such a read in conventional DRAMs. So energy is expended to read the entire page when data from only a portion of the page is needed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 schematically shows an exemplary dynamic random access memory (DRAM) array according to the present description, having a segmented page configuration.

FIG. 2 schematically depicts a column and associated structures of the DRAM array of FIG. 1.

DETAILED DESCRIPTION

This description is directed to a dynamic random access memory (DRAM) array which can be operated in a more energy efficient manner. The DRAM array is organized as a matrix of cells in rows and columns, such that each cell is uniquely associated with a specific row and column. The DRAM array has a width, also referred to as the page width, which is equal to the number of columns in the array. The DRAM array is configured so that certain operations can be implemented so as to affect only some of the columns, or only a portion of the width of the array. For example, the rows of the array may have segmented word lines, so that each row has multiple local word lines. Instead of activating the entire row and thereby expending energy to read and restore bits that may not be of interest (i.e., wasted energy due to “overfetch,”) one or more selected local word lines may be used to select and read only those cells associated with the local word lines. The columns associated with the non-selected local word lines are not used, providing an energy savings over what would be expended if all of the columns were used. Specifically, the bit lines of those non-selected columns do not need to be charged and discharged to perform the targeted read. Nor do the cells and dummy cells for those columns need to be restored.
FIG. 1 shows an exemplary DRAM array 100 according to the present description. DRAM array 100 includes storage cells arranged in a matrix of rows and columns, such that each storage cell is uniquely associated with a specific row and column. In the example of FIG. 1, the array has r rows, one of which is indicated at 102 in the figure, and 8192 columns (eight kilobit page size). The 8192 columns are grouped into 32 groups or “subpages” of 256 columns each. The vertical stack of elements headed by each box labeled “dummy cells” corresponds to one of the 32 groups of 256 columns. Therefore, each column has r cells (the number of rows in the array) and each row has 8192 cells (the number of columns in the array). Where dummy cells are employed, each column will also have two dummy cells, one even and one odd. The specific numbers of rows, columns, cells and columns per group are arbitrary in the example; other numbers may be employed as appropriate to the implementation.
FIG. 2 schematically shows an example column 200 of DRAM array 100. Column 200 includes a pair of bit lines—even bit line 202 and odd bit line 204—that are coupled to sense amplifier 206. The figure shows six cells: four regular storage cells 208 and two dummy cells 210. Each cell 208 has a capacitor 212 coupled to one of the bit lines via a transistor 214 that is gate-coupled to a word line 216 that is asserted to turn on the transistor. Cells 208 a and 208 c are coupled to even bit line 202, and cells 208 b and 208 d are coupled to odd bit line 204. Cells 208 a and 208 c may therefore be referred to as “even cells,” and cells 208 b and 208 d as “odd cells.” Their associated word lines may be designated similarly, i.e., 216 a and 216 c are even word lines and 216 b and 216 d are odd word lines.
Dummy cells 210 include similar configurations of capacitors 220, transistors 222 and word lines 224. Dummy cell 210 a is coupled to even bit line 202, and it and its dummy word line 224 a may therefore be referred to as “even.” Dummy cell 210 b and dummy word line 224 b in turn are “odd.”
Prior to reading the logical HI or logical LO values stored in the cells, bit lines 202 and 204, and dummy cells 210, are precharged to 50% of the logical HI voltage. For simplicity, logical HI and logical LO will be referred to herein as Vdd and Vss, respectively. A row is then activated by asserting one of the word lines 216 so as to turn on the transistor and cause the logical HI or LO voltage stored on the cell capacitor to be shared with the pre-charged bit line. Typically the capacitance of the bit line is relatively high compared to the capacitance of the cell. Accordingly, if the stored value is HI, the resulting voltage on the bit line after charge sharing will he slightly higher than the precharged 50% value (Vdd/2 plus a small amount). If the stored value is LO (Vss), then the resulting voltage after charge sharing will be slightly less than the 50% value (Vdd/2 minus a small amount).
At the same time that the specific word line 216 is asserted, a complementary dummy word line 224 is asserted. In other words, if an even row is activated ( line 216 a or 216 c), then the odd dummy line 224 b is asserted to cause the odd dummy cell to share charge onto the precharged odd bit line 204, and vice versa.
At this point, one of the bit lines is slightly above or below Vdd/2, respectively reflecting whether the stored value in the cell was HI or LO, and the other is at Vdd/2 due to precharge and the Vdd/2 value on the dummy cell capacitor. There may be some movement due to noise and other factors, but the use of the dummy cell facilitates producing an accurately measurable differential signal on the bit lines in the face of noise and other issues. The sense amplifier is then triggered to capture the differential signal and convert the small differential into a logical HI or LO output, depending on the value that was on the storage cell capacitor. The column may also optionally include a latch 226 to provide an additional bit of storage. For example a value may be held active in the latch while refresh or precharge operations are being performed that affect the sense amplifier. In addition to capturing the differential signal, the sense amplifier also drives the bit line full swing to restore the capacitor to its charge level existing just prior to the destructive read. Once the charge is restored across the cell capacitor, the cell's word line is lowered.
Returning now to FIG. 1, DRAM array 100 is configured so that certain DRAM commands affect only a selected portion of the width of the array. In terms of the array's columns, control may be implemented to control which columns of the DRAM array are involved during word line assertions, bit line precharge, sense amp operation, latch control, column selection and other commanded DRAM operations. In terms of a given row, this control may be understood as creating a condition in which a DRAM command affects only a portion of the row.
DRAM array 100 includes 32 subpages, designated “Subpage 0” through “Subpage 31” at the top of the figure. Each subpage includes a group of 256 columns. Each column is as described with reference to FIG. 2—i.e., each column has dummy cells 106 and regular storage cells 108 coupled to bit line pairs 110 that are connected to sense amplifiers 112. As indicated, one or more latches 114 may also be included in each column to store the sense amplifier output and thereby provide one or more additional bits of storage. To simplify the figure, reference numbers are designated only on the first subpage and only a single latch per column is shown.
At the row level, the subpage configuration is implemented with segmented word lines. Specifically, each row has a segmented word line circuit including a global word line and a plurality of local word lines. Each local word line is associated with one of the subpages of the array. Referring specifically to row 102, segmented word line circuit 104 includes a global word line (gwl0) and 32 local word lines lwl0.0 through lwl0.31. Among other things, as will be described below, the segmented word line circuits are controllable to cause selection of only a portion of the cells in an active row of the array (e.g., turn on cell transistors only in a selected subpage or subpages.)
Decode and select functions are performed by one or more decoders that select rows, subpages and columns for various operations. In the present example, DRAM array 100 includes a row decoder 120, subpage decoder 122 and column selectors 124. DRAM array 100 is thus addressed with row, subpage and column fields. Typically, only one row is selected at a time, so in the case of an array with 256 rows, the row field would be eight bits wide. If only one subpage is selected at a time, the 32 subpages would be addressed with a 5-bit field, though implementations are possible in which more than one subpage is selected at a time. Still further, it will at times be desirable to have all of the subpages of the array selected. The 256 individual columns within a subpage may be addressed with an 8-bit field in order to select a single column. Additional command bandwidth may be provided for multi-I/O configurations in which multiple columns are selected.
A row activate operation will now be described, in which cell charges are read onto bit lines, bit line values are sensed, and cells are restored to the charge values present before the destructive read of the charge on the cell capacitors. To activate a subpage of a row, row decoder 120 decodes a row address ROW in order to select a single global word line gwl(ROW) to go high. In parallel, subpage decoder 122 decodes a subpage address SUBPAGE to generate a subpage select signal that drives a single subpage select line sps(SUBPAGE) to go high. These two asserted signals are ANDed (e.g., with AND gate 126) such that their coincidence causes a single local word line lwl(ROW.SUBPAGE) to go high, as a result of the subpage select signal gating the global word line. This selects the 256 cells (switches on their transistors) on that row and in that subpage so that the cell capacitors are connected to and share their charge with their precharged bit lines. The sps(SUBPAGE) assertion also triggers the associated subpage of sense amplifiers to sense and capture the signal on the bit lines and restore it to full swing. Once the restored charge is written back to the selected cells, the word line can be lowered.
The column groupings and subpage decoding in FIG. 1 are arbitrary and provided as an illustrative example; different configurations may be employed without departing from the spirit of this description. Subpages can have any practicable number of columns. Additional decode command bandwidth can be provided to select multiple subpages, instead of one at a time. For example, a power-of-2 scheme could be employed allowing for selection of 2, 4, 8 or 16 of the 32 subpages, In such a case, the array provides variable page width operation, in which the decoder output determines the size of the portion of the row being activated—a first control can cause a first set of subpages to be activated, with a second control activating a larger set of subpages. In the most general case, subpage decoding can be implemented as a mask (32 bits in the current example) in which any combination and number of subpages can be selected.
The subpage implementation can also allow for targeted precharge operations, which can produce significant energy savings. As discussed above, the row activate operation ends with values being restored across the cell capacitors. Therefore, the precharge operation needs only to precharge the sense amplifiers and set the dummy cells and bit lines to their 50% values. The subpage select signals can again be employed so that the precharge operation only affects the selected columns and their associated bit lines, cells, etc. Assuming a read operation on only one subpage, a subsequent precharge can be limited to that portion of the array, thereby avoiding expending energy to precharge the columns in non-selected subpages. These savings can be significant given that activate and precharge operations can occur at much higher frequencies than refresh.
It will be desirable at times to have all subpages selected at the same time, for example during a refresh operation. In the example of FIG. 1, signaling is provided to activate a global word line and cause all of the subpage select lines to go high. This connects all of the cells in the the row and the appropriate dummy cells to their respective sense amplifiers, which are also triggered by the subpage select lines. As described above, this causes the appropriate charge to be restored to the cell, after which the word line is lowered. If an extra latch is provided for each column, as in FIG. 1, a refresh can be performed without enabling the latch, allowing the pages to be held active during a refresh. Alternatively a special refresh—effectively a global row activate—can perform a refresh and enable the latch allowing all of the subpages of a page to be activated in a single operation.
A column address COLUMN is used in read and write operations. FIG. 1 shows column selectors 124 with which such an address may be used. In single-bit I/O operations (i.e., reading or writing a single column), COLUMN would be an 8-bit field which, when combined with the subpage address SUBPAGE, would specify a particular individual column within a designated subpage. Once a subpage has been loaded into the sense amplifiers (or the latches if present), the combination of the subpage and column address causes a specific column to be read out onto the data bus. These addresses are also used during write operations, to cause data to be loaded from the data bus into specific sense amplifiers or latches.
When multi-bit I/O is employed (i.e., reading/writing multiple cells simultaneously), it typically will be desirable to limit the activity to as few subpages as possible, to take advantage of the energy-saving features of the described segmentation. For example, if a 32-bit read is performed, taking one bit from each sub-page would entail reading 8 k bits into the sense amplifiers. Alternately, the 32 bits could all be read from a single subpage, thereby avoiding the overfetch energy expenditure needed to read from the other 31 subpages.
This written description uses examples to disclose the invention, including the best mode, and also to enable a person of ordinary skill in the relevant art to practice the invention, including making and using any devices or systems and performing any incorporated methods. The patentable scope of the invention is defined by the claims, and may include other examples as understood by those of ordinary skill in the art. Such other examples are intended to be within the scope of the claims.

Claims

1. A dynamic random access memory (DRAM) array, comprising:

a plurality of rows;

a plurality of columns;

a plurality of cells, each being associated with one of the columns and with one of the rows, where each cell includes a capacitor that is selectively coupled to a bit line of its associated column so as to share charge with the bit line when the cell is selected; and

a segmented word line circuit for each row, the segmented word line circuit being controllable to cause selection of only a portion of the cells in that row.

2. The DRAM array of claim L where for each row, the segmented word line circuit includes:

a global word line; and

a plurality of local word lines that are each coupled with the global word line and an associated subpage of the cells in the row, where the cells of a given subpage are selected to share charge with their bit lines by (i) asserting the global word line and (ii) gating the asserted global word line with an asserted subpage select signal in order to assert the local word line coupled with the given subpage of cells.

3. The DRAM array of claim 1, further comprising a decoder configured to generate subpage select signals that control which bit lines of the DRAM array are involved in a commanded DRAM operation.

4. The DRAM array of claim 3, where the commanded DRAM operation is a command to have cells in a row share the charge of their capacitors with the bit lines of their associated columns, the subpage select signals therefore controlling which bit lines are involved in such charge sharing.

5. The DRAM array of claim 3, where the commanded DRAM operation is a command to precharge bit lines, the subpage select signals therefore controlling which bit lines are precharged.

6. The DRAM array of claim 3, further comprising, for each column, a sense amp coupled to a bit line of the column, and where the commanded DRAM operation is a command to enable the sense amps to sense charge levels on their coupled bit lines, the subpage select signals therefore controlling which sense amps perform such charge sensing.

7. The DRAM array of claim 6, where the sense amps are configured to generate an output indicative of whether a cell that has shared charge with the bit line was storing a logical HI or logical LO voltage level.

8. The DRAM array of claim 7, further comprising a latch coupled to each of the sense amps and operative to store the output of the sense amp.

9. A dynamic random access memory (DRAM) array, comprising:

a plurality of rows;

a plurality of columns;

a plurality of cells, each being associated with one of the columns and with one of the rows; and

a decoder configured to generate subpage select signals that control which columns of the DRAM array are involved in a commanded DRAM operation.

10. The DRAM array of claim 9, were each cell includes a capacitor that is selectively coupled to a bit line of its associated column so as to share charge with the bit line when the cell is selected, and where the commanded DRAM operation is a command that selected capacitors in a selected row share charge with their associated bit lines, the specific capacitor selection being caused by the subpage select signals.

11. The DRAM array of claim 9, where each column includes a pair of bit lines coupled with a sense amp, and where the commanded DRAM operation is command to precharge selected bit lines, the specific bit line selection being caused by the subpage select signals.

12. The DRAM array of claim 9, where each column includes a pair of bit lines coupled with a sense amp, and where the commanded DRAM operation is a command to enable selected sense amps to sense charge levels on their coupled bit lines, the specific sense amp selection being caused by the subpage select signals.

13. The DRAM array of claim 9, where the decoder is controllable to provide variable page width operation such that, for a given one of the rows, the decoder is operable to activate a portion of the row which varies in size based on an output of the decoder.

14. A dynamic random access memory (DRAM) array, comprising:

a plurality of rows;

a plurality of columns;

a segmented word line circuit for each row where the segmented word line circuit includes a global word line and a plurality of local word lines that are each coupled with the global word line and an associated subpage of the cells in the row, where the cells of a given subpage are selected to share charge with their bit lines by (i) asserting the global word line and (ii) gating the asserted global word line with an asserted subpage select signal in order to assert the local word line coupled with the given subpage of cells.

15. The DRAM array of claim 14, further comprising a decoder configured to generate the subpage select signal.

16. The DRAM array of claim 15, where the decoder is further configured to generate signals to select rows and columns for use in DRAM operations.

17. The DRAM array of claim 14, further comprising a plurality of subpage select lines.

18. The DRAM array of claim 17, where each of the subpage select lines is associated with a subset of the plurality of columns.

19. The DRAM array of claim 18, where for each subset of the plurality of columns, each row has a local word line for the subpage of cells in those columns, the associated subpage select line being configured to select the local word line of the subset of the plurality of columns.

20. The DRAM array of claim 18, where for each subset of the plurality of columns, each column within the subset has a sense amp that is selectively enabled by the subpage select line associated with the subset of the plurality of columns.

21. The DRAM array of claim 20, where for each subset of the plurality of columns, each column has a latch coupled to its sense amp, the latch being triggered by the subpage select line associated with the subset of the plurality of columns.