US20130139884A1

US20130139884A1 - Solar cell and method for manufacturing the same

Info

Publication number: US20130139884A1
Application number: US13/469,824
Authority: US
Inventors: Kyoungsoo Lee; Seongeun Lee
Original assignee: LG Electronics Inc
Current assignee: LG Electronics Inc
Priority date: 2011-12-05
Filing date: 2012-05-11
Publication date: 2013-06-06
Also published as: KR20130062775A; EP2602835A3; EP2602835A2; US9515212B2; EP2602835B1; CN103137792B; US20150236176A1; US20150162467A1; CN103137792A; EP3288088A1; US9601644B2; US9029185B2

Abstract

A method for manufacturing a solar cell according to an embodiment of the present invention includes preparing a semiconductor substrate having a first conductive type dopant; ion-implanting a pre-amorphization elements into a front surface of the semiconductor substrate to form an amorphous layer; and forming an emitter layer by ion-implanting second conductive type dopant into the front surface of the semiconductor substrate. The method then further includes heat-treating the layers to activate the second conductive type dopant. The method further includes forming a back surface field layer at a back surface of the semiconductor substrate by ion-implanting a first conductive type dopant.

Description

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Korean Patent Application No. 10-2011-0129205, filed on Dec. 5, 2011, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference.

BACKGROUND

1. Field of the Disclosure
The present disclosure relates to a solar cell and a method for manufacturing the same, and more particularly, to a solar cell and a method for manufacturing the same where an ion-implantation method is applied.
2. Description of the Related Art
In recent times, as it becomes more accepted that conventional energy resource such as petroleum and coal will be exhausted within a foreseeable timeframe, interest in alternative energy sources for replacing the conventional energy resources is gradually increasing. Among them, a solar cell is spotlighted as a new generation cell using a semiconductor device for directly converting solar energy into electrical energy.
A solar cell is manufactured by forming a plurality of layers and patterning them through etching according to a predetermined design. In the manufacturing process, various methods and various process sequences may be applied.
For example, when doping predetermined conductive type dopants into a semiconductor substrate, an ion-implantation method may be applied. In the ion-implantation method, an ion-beam comprising the dopants is fired at the semiconductor substrate to implanted the dopants into the semiconductor substrate. The dopants break a lattice structure inside the semiconductor substrate, and thus necessitate a heat-treatment for recovery of the lattice structure. When a front surface and a back surface of the semiconductor substrate are doped with different dopants, temperatures of the heat-treatment suitable for the different dopants may differ. Generally, the heat-treatment is performed at the higher temperature between the different temperatures. But, the dopants needing to be heat-treated at the lower temperature are excessively diffused into the semiconductor substrate, adversely affecting the properties of the solar cell. Also, the cost increases and the process cannot be easily performed due to the higher temperature.

SUMMARY

This disclosure is directed to a solar cell and a method for manufacturing the same being able to simultaneously heat-treat different dopants having different suitable heat-treatment temperatures at a low temperature.
A method for manufacturing a solar cell according to an embodiment includes preparing a semiconductor substrate having a first conductive type; ion-implanting a pre-amorphization element into a front surface of the semiconductor substrate to form an amorphous layer; and forming an emitter layer by ion-implanting a second conductive type dopant into the front surface of the semiconductor substrate.
A solar cell according to another embodiment of the present invention includes a semiconductor substrate having a first conductive type dopant; an emitter layer formed at a front surface of the semiconductor substrate, the emitter layer comprising a second conductive type dopant and a pre-amorphization element having an atomic number larger than that of the second conductive type dopant; a first electrode electrically connected to the emitter layer; and a second electrode electrically connected to the semiconductor substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a solar cell according to an embodiment of the present invention.

FIG. 2 is a flow chart for illustrating a method for manufacturing a solar cell according to an embodiment of the present invention.

FIGS. 3 a to 3 g are cross-sectional views for illustrating a method for manufacturing a solar cell according to an embodiment of the present invention.

FIG. 4 is a graph illustrating an energy loss induced by nuclei stopping and electronic stopping according to energy, regarding boron, arsenic, and phosphorus.

FIG. 5 is a graph illustrating solid solubility of various first and second conductive type dopants in silicon.

FIG. 6 is a graph illustrating temperature of heat-treating for activating with respect to the dose of boron and phosphorus.

FIG. 7 illustrates channels formed in a <110> direction at a semiconductor substrate including silicon.

FIG. 8 is a cross-sectional view of a solar cell according to a modified embodiment of the present invention.

DETAILED DESCRIPTION

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to these embodiments, and various modifications of the exemplary embodiments are possible.
In order to clearly and concisely illustrate the embodiments, elements not related to the present invention are omitted in the figures. Also, elements similar to or the same as each other have the same reference numerals. In addition, the dimensions of layers and regions are exaggerated or schematically illustrated, or some layers are omitted for clarity of illustration. The dimensions of each part as drawn may not reflect an actual size (i.e., not to scale).
In the following description, when a layer or substrate “includes” another layer or portion, it can be understood that the layer or substrate further includes still another layer or portion. Also, when a layer or film is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers can also be present. Further, when a layer or film is referred to as being “directly on” another layer or substrate, it can be directly on the other layer or substrate, and thus, there is no intervening layer.
FIG. 1 is a cross-sectional view of a solar cell according to an embodiment of the present invention.
Referring to FIG. 1, a solar cell 100 according to one embodiment includes a semiconductor substrate 10, an emitter layer 20 formed at or adjacent to a first surface (hereinafter, referred to as “the front surface”) of the semiconductor substrate 10, and a back surface field layer 30 formed at or adjacent to a second surface (hereinafter, referred to as “the back surface”) of the semiconductor substrate 10. Also, the solar cell 100 may include an anti-reflection film 22 and a first electrode 24 (or a plurality of first electrodes) (hereinafter, referred to as “the front electrode”) formed on the front surface of the semiconductor substrate 10, and may include a passivation film 32 and a second electrode 34 (or a plurality of second electrodes) (hereinafter, referred to as “the back electrode”) formed on the back surface of the semiconductor substrate 10. Next, the detailed structure of the solar cell 100 will be described.
Semiconductor substrate 10 may include various semiconductor materials. For example, the substrate 10 may include silicon having a first conductivity type dopant. For the silicon, single crystal silicon or polycrystalline silicon may be used. The first conductivity type may be an n-type. That is, the semiconductor substrate 10 may include single crystal silicon or polycrystalline silicon having a Group V element, such as phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), or the like.
When the semiconductor substrate 10 having n-type dopants as in the above, the emitter layer 20 is formed having p-type dopants at the front surface of the semiconductor substrate 10, and thereby forming a p-n junction. When the sun light is incident on the solar cell 100, the electrons generated by the photoelectric effect move to the back surface of the semiconductor substrate 10, and the holes generated by the photoelectric effect move to the front surface of the semiconductor substrate 10. This migration of electrons and holes generates electric energy.
The holes, having less mobility than the electrons, move to the front surface of the semiconductor substrate 10 and not the back surface. This enhances the conversion efficiency of the solar cell 100.
The front and back surfaces of the semiconductor substrate 10 may be textured surfaces having protruded and/or dented portions of various shapes (such as pyramid shape). The reflectance of the incident sun light at the front surface of the semiconductor substrate 10 can be reduced by the texturing. Thus, the light reaching the p-n junction between the semiconductor substrate 10 and the emitter layer 20 can increase, thereby reducing an optical loss of the solar cell 100.
The back surface field 30 is formed at the back surface of the semiconductor substrate 10, and has the first conductive type dopant with a doping concentration higher than that of the semiconductor substrate 10. Back surface field 30 can prevent recombination of electron-hole pairs at the back surface of the semiconductor substrate 10, and therefore enhance the efficiency of the solar cell 100. Back surface field 30 may include a group V element, such as phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), or the like. For example, in the embodiment, because the phosphorus has an atomic number smaller than the arsenic or the like, the phosphorus may be used for reducing the energy less during ion-implanting. This will be described below in more detail.
For example, when the back surface field layer 30 has an electrical resistance of about 50-100 ohm/square and has a junction depth of about 500 nm˜1 μm, the surface concentration of the first conductive type dopants may be about 10×10²⁰˜10×10²²/cm³.
The passivation film 32 and the back electrode 34 may be formed at the back surface of the semiconductor substrate 10.
The passivation film 32 may be substantially at the entire back surface of the semiconductor substrate 10, except for the portions where the back electrode 34 is formed. The passivation film 32 elliminates a recombination site of minority carriers existing on the back surface of the semiconductor 10. Thus, an open circuit voltage (Voc) of the solar cell 100 can be increased.
The passivation film 32 may include a transparent insulating material for passing the light. That is, light can be incident to the back surface of the semiconductor substrate 10 through the passivation film 32, and thereby enhance the efficiency of the solar cell 100. The passivation film 32 may have a single film structure or a multi-layer film structure including, for example, at least one material selected from a group consisting of silicon nitride, silicon nitride including hydrogen, silicon oxide, silicon oxy nitride, MgF₂, ZnS, TiO₂, and CeO₂, but is not limited thereto, and thus, the passivation film 32 may include various materials.
The back electrode 34 may include various metals having high electrical conductivity. For example, the back electrode 34 may include silver (Ag) having high electrical conductivity and high reflectance. When the back electrode 34 includes silver having high reflectance, the back electrode 34 can reflect the light toward the back surface of the semiconductor substrate 10. Thus, the amount of the utilized light can be increased.
Back electrode 34 may have a width larger than the front electrode 24. Also, back electrode 34 may have various shapes in a plan view.
The emitter layer 20 having the second conductive type dopant may be formed at the front surface of the semiconductor substrate 10. Emitter layer 20 may include a p-type dopant such as a group III element, such as boron (B), aluminum (Al), gallium (Ga), or the like. Boron or gallium having a smaller atomic number and being light may be possibly used. In the embodiment, the emitter layer 20 includes the second conductive type dopant and a pre-amorphization element having an atomic number larger than that of the elements constituting the semiconductor substrate 10.
For amorphization of the semiconductor substrate 10, the pre-amorphization elements may have an atomic number larger than that of the elements constituting the semiconductor substrate 10. Also, the pre-amorphization elements may have similar properties with the semiconductor substrate 10 or may be inert elements not reacting with the semiconductor substrate 10, so that the pre-amorphization elements do not affect the properties (e.g., electrical properties) of the semiconductor substrate 10.
The pre-amorphization elements similar to the semiconductor substrate 10 may be carbon group elements (such as germanium (Ge) or the like) because the silicon constituting the semiconductor substrate 10 is the carbon group element. The inert pre-amorphization elements may be noble gas group elements (such as argon (Ar) or the like).
The emitter layer 20 includes a first layer 201 and a second layer 202. The first layer 201 is adjacent to the front surface of the semiconductor substrate 10 and includes the pre-amorphization elements and the second conductive type dopants. The second layer 202 is positioned at a portion of the semiconductor substrate 10 deeper than the first layer 201 and includes the second conductive type dopants without the pre-amorphization elements.
The front surface portion of the semiconductor substrate 10 becomes amorphous by implanting the pre-amorphization elements, and then, the second conductive type dopants are implanted. The second conductive type dopants are then diffused deeper into the semiconductor substrate 10 by a activation heat-treatment. The method and the effect of the pre-amorphization elements will be described in more detail in the description of the method for manufacturing the solar cell 100.
A ratio of a total thickness of the emitter layer 20 (that is, the junction depth) to a thickness of the first layer is about 1:0.05˜1:0.15. If the ratio is smaller than about 1:0.05, the effect by the pre-amorphization may be insufficient. If the ratio is larger than about 1:0.15, the junction depth after the heat-treatment for activation increases, and control of the junction depth may be difficult.
For example, when the emitter layer 20 may have an electrical resistance of about 50˜100 ohm/square and have a junction depth of about 500 nm˜1 μm and the surface concentration of the second conductive type dopants may be about 10˜10²⁰˜10×10²²/cm³.
The anti-reflection film 22 and the front electrode 24 may be formed on the emitter layer 20 at the front surface of the semiconductor substrate 10.
Anti-reflection film 22 may be substantially at the entire front surface of the semiconductor substrate 10, except for the portion where the front electrode 24 is formed. Anti-reflection film 22 reduces reflectance (or reflectivity) of sun light incident to the front surface of the semiconductor substrate 10. Also, the anti-reflection film 22 passivates defects at a surface or a bulk of the emitter layer 20.
Since the reflectance of the sun light is reduced by the anti-reflection film 22, an amount of the sun light reaching the p-n junction formed between the semiconductor substrate 10 and the emitter layer 20 is increased, thereby increasing short circuit current (Isc) of the solar cell 100. Also, because the defects at the emitter layer 20 are passivated, recombination sites of minority carrier are reduced or eliminated, thereby increasing an open-circuit voltage (Voc) of the solar cell 100. Accordingly, the open-circuit voltage (Voc) and the short-circuit current (Isc) of the solar cell 100 are increased by the anti-reflection layer 22, and thus, the efficiency of the solar cell 100 can be enhanced.
Anti-reflection film 22 may include various materials. Anti-reflection film 22 may have a single film structure or a multi-layer film structure including, for example, at least one material selected from a group consisting of silicon nitride, silicon nitride including hydrogen, silicon oxide, silicon oxy nitride, MgF₂, ZnS, TiO₂, and CeO₂, but is not limited thereto, and thus, the anti-reflection film 22 may include various materials.
The front electrode 24 may include various metals having high electrical conductivity. For example, the front electrode 24 may include silver (Ag) having high electrical conductivity, but is not limited thereto. The front electrode 24 may be a single layer including transparent conductive materials, or may have a stacked structure having a transparent conductive layer and a metal layer (called “a bus bar” or “a finger electrode”) on the transparent conductive layer.
In the embodiment, emitter layer 20 is formed by sequentially ion-implanting the pre-amorphization elements and the second conductive type dopants, and the back surface field layer 30 is formed by ion-implanting the first conductive type dopants. Thus, the portions where emitter layer 20 and back surface field layer 30 are formed can become amorphous, and more dopants can be activated by solid phase epitaxy (SPE) at a low temperature. For example, a ratio of an activation amount by the solid phase epitaxy to an activation amount by the general activation heat-treatment is about 1:0.5˜1:0.8. That is, the activation amount by the solid phase epitaxy is considerably larger than that by the general activation heat-treatment. The activation amount will be described in more detail in the description of the method for manufacturing the solar cell 100. In the following description, described portions from above will be omitted, and previously un-described portions from above will be described in more detail.
FIG. 2 is a flow chart for illustrating a method for manufacturing a solar cell according to an embodiment. FIGS. 3 a to 3 g are cross-sectional views for illustrating a method for manufacturing a solar cell according to an embodiment of the present invention.
Referring to FIG. 2, a method for manufacturing a solar cell according to the embodiment includes a step ST10 for preparing a semiconductor substrate, a step ST20 for ion-implanting pre-amorphization elements, a step ST30 for forming an emitter layer by ion-implanting second conductive type dopants, a step ST40 for forming a back surface field layer, a step ST50 for heat-treating for an activation, a step ST60 for forming an anti-reflection film and a passivation film, and a step ST70 for forming an electrode.
First, as shown in FIG. 3 a, in the step ST10 for preparing the semiconductor substrate, a semiconductor substrate 10 having first conductive type dopants is prepared. The front and back surfaces of the silicon semiconductor substrate 10 may be textured to have protruded and/or dented portions of various shapes (or to have an uneven surface). The texturing may be created using a wet etching method or a dry etching method. In the wet etching method, the substrate 10 may be dipped into a texturing solution. Wet etching process time can be short. In the dry etching method, the surface of the semiconductor substrate 10 is etched by a diamond drill or a laser. Dry etching can form substantially uniform protruded and/or dented portions, however, the semiconductor substrate 10 may be damaged in the process and the process time may be long. Accordingly, the semiconductor substrate 10 may be textured by various methods.
Next, as shown in FIG. 3 b, in the step ST20 for ion-implanting the pre-amorphization elements, the pre-amorphization elements are ion-implanted into the front surface of the semiconductor substrate 10. The pre-amorphization element has an atomic number larger than that of the elements (e.g., silicon) constituting the semiconductor substrate 10. The pre-amorphization may be a carbon group element (such as germanium (Ge) or the like) or a noble gas group element (such as argon (Ar) or the like). The ion-implantation forms an amorphous portion or layer 211 is formed at the front portion of the semiconductor substrate 10.
Here, a dose of pre-amorphization elements may be in a range of about 1×10¹⁴/cm²˜3×10¹⁵/cm². In the above range, the front portion of the semiconductor substrate 10 can become effectively amorphous. The dose of pre-amorphization elements is smaller than that of the first conductive type dopants for forming a back surface field layer 30. This is because the semiconductor substrate 10 can easily become amorphous by the pre-amorphization elements since the pre-amorphization elements are larger and heavier than the first conductive type dopants.
Next, as shown in FIG. 3 c, in the step ST30 for forming the emitter layer by ion-implanting the second conductive type dopants, the second conductive type dopants such as boron (B) or gallium (Ga) are ion-implanted into the front surface of the semiconductor substrate 10. The second conductive type dopants are implanted only into the amorphous portion or layer 211.
Thus, by controlling the implantation depth of the pre-amorphization elements, the implantation depth of the second conductive type dopants can be easily controlled, and thus, it is suitable to form a shallow emitter. On the other hand, in the prior art, since the second conductive type dopants are implanted without the pre-amorphization elements, it is difficult to control the implantation depth of the second conductive type dopants by a channeling effect, which will be described later in this disclosure.
The dose of the second conductive type dopants may be in a range of about 2×10¹⁵/cm²˜4×10¹⁵/cm². When the dose is above about 4×10¹⁵/_cm ², the semiconductor substrate 10 that is damaged by the pre-amorphization elements may be damaged more. Also, the above dose range is decided considering a resistance of the emitter layer 20.
Next, as shown in FIG. 3 d, in the step ST40 for forming the back surface field layer, the first conductive type dopants such as phosphorus (P) are ion-implanted into the back surface of the semiconductor substrate 10. The first conductive type dopants such as phosphorus (P) are larger and heavier than the silicon constituting the semiconductor substrate 10, and thus, a portion 311 where the first conductive type dopants are implanted becomes amorphous.
Here, a dose of the first conductive type dopants (e.g., phosphorus) may be larger than those of the pre-amorphization elements and the second conductive type dopants. For example, the dose of the first conductive type dopants (e.g., phosphorus) may be in a range of about 3×10¹⁵/cm²˜8×10¹⁵/cm². The above dose range is decided for reducing the temperature of the heat-treating for the activation and for increasing an amount of the activated dopants.
Next, as shown in FIG. 3 e, in the step ST50 for heat-treating for the activation, the second conductive type dopants and the first conductive type dopants ion-implanted into the semiconductor substrate 10 are simultaneously activated. That is, since the front surface of the semiconductor substrate 10 become amorphous by the pre-amorphization elements and the back surface of the semiconductor substrate 10 become amorphous by the first conductive type dopants, a growth through solid phase epitaxy (SPE) is induced at the front surface and the back surface of the semiconductor substrate 10 during the heat-treating. Thus, the first conductive type dopants and the second conductive type dopants can be activated at the relatively low temperature (e.g., about 400˜700° C.) compared to the temperature in the prior art.
When the temperature for heat-treating for the activation is above about 700° C., the problems due to the high temperature may be generated. When the temperature for heat-treating for the activation is below about 400° C., the growth through the solid phase epitaxy is not sufficiently induced.
In the embodiment, because the temperature of the heat-treating for the activation is relatively low, the problems due to the high temperature (e.g., degradation of the semiconductor substrate 10) can be minimized. In addition, by using the solid phase epitaxy, the temperature of the heat-treating for activating the first conductive type dopants and the temperature of the heat-treating for activating the second conductive type dopants are similar.
In known processes, the temperature of the heat-treating for activating the second conductive type dopants is higher than the temperature of the heat-treating for activating the first conductive type dopants. The temperature of the heat-treating for activating the second conductive type dopants is often above about 900° C. Thus, since the heat-treating for activating is performed above about 900° C., the first conductive type dopants are excessively diffused into the semiconductor substrate 10. This leads to difficulty in controlling the doping profile.
On the other hand, in the embodiment, because of the pre-amorphization elements, the temperature of the heat-treating for activating the first conductive type dopants and the temperature of the heat-treating for activating the second conductive type dopants are similar. Thus, the first and second conductive type dopants can be simultaneously heat-treated at the relatively low temperature. Accordingly, co-activation of the first and second conductive type dopants can be possible, and thus, the process can be simplified and the doping profile can be effectively controlled. This leads to properties of the solar cell being enhanced.
Here, in the heat-treating for forming the emitter layer 20, the second conductive type dopants are diffused into the semiconductor substrate 10 deeper than the pre-amorphization elements, and the pre-amorphization elements larger than the elements (e.g., silicon) constituting the semiconductor substrate 10 remain at the amorphous portion or layer 211 a of FIG. 3 d. Accordingly, the second conductive type dopants are positioned at the semiconductor substrate 10 deeper than the pre-amorphization. Thus, the emitter layer 20 includes a first layer 201 including the pre-amorphization elements and the second conductive type dopants, and a second layer 202 including the second conductive type dopants.
The reason for ion-implanting boron (B) or gallium (Ga) to form the emitter layer 20, the reason for using the phosphorus (P) to form the back surface field layer 30, and the reason for using the pre-amorphization will be described in more detail below with reference to FIGS. 4 to 7.
FIG. 4 is a graph illustrating an energy loss induced by nuclei stopping and electronic stopping according to energy, regarding boron, arsenic, and phosphorus, and FIG. 5 is a graph illustrating solid solubility of various first and second conductive type dopants in silicon. FIG. 6 is a graph illustrating temperature of heat-treating for activating according to dose of boron and phosphorus, and FIG. 7 illustrates channels formed in a <110> direction at a semiconductor substrate including silicon.
In the ion-implantation method, the ion is stopped at the semiconductor substrate 10 by the nuclei stopping and the electronic stopping.
The nuclei stopping is induced by mechanical collision of the implanted ion and the nucleus of the semiconductor substrate 10. The elements of the semiconductor substrate 10 move in the lattice, and thus, the damage induced by the implantation is generated. The nuclei stopping linearly increases as initial energy increases at a low energy region, and the nuclei stopping decreases as initial energy increases at a high energy region. This is because 100% of energy cannot be transferred as the time for transferring the energy decreases during the collision. That is, when the initial energy (or ion acceleration energy) is above predetermined energy, the energy loss by the nuclei stopping decreases and a projection range (Rp) (ion-implantation depth) increases. In addition, as the implanted ion becomes heavier, the energy loss by the nuclei stopping increases.
The electronic stopping is induced by ionization of the elements constituting the semiconductor substrate 10 caused by collision of the implanted ion and the electron of the semiconductor substrate 10 due to coulombic interaction. The electronic stopping is proportional to the velocity of the implanted ion, regardless of mass of the implanted ion. Thus, the electronic stopping power increases as the ion acceleration energy increases.
In the case of boron, the cross-ever energy is about 10 keV. Thus, above about 10 keV, the nuclei stopping is hardly induced, and only the electronic stopping is induced. That is, in an energy range of about 30˜300 keV that is usually used, boron does not damage the semiconductor substrate 10 and the energy is lost by the electronic stopping. Thus, boron may be implanted by using an energy of about 5˜20 keV not to damage the semiconductor substrate 10.
However, when the implant damage by the nuclei stopping is not induced by using the boron that is light and small for forming the emitter layer 20, the boron is activated only by the diffusion. Thus, the activation is not effective. Also, referring to FIG. 5, the second conductive type dopant such as boron or gallium has small solid solubility in the silicon constituting the semiconductor substrate 10. Thus, the temperature of the heat-treating for activating the second conductive type dopants is high (e.g., above about 900° C.).
Further, referring to FIG. 6, as the dose of the boron that is the second conductive type dopant increases, the temperature of the heat-treating for activating increases. This is because the solubility of the boron is low. Thus, the amount of the boron may be minimized not to generate the implant damage, and the boron may be activated by the diffusion.
In addition, when a light ion such as boron is used, the ion can be implanted deeper than a general projection range (or an ion-implantation depth) by the channeling effect according to the ion-implantation direction and the elements arrangement direction. Thus, the doping profile cannot be easily controlled. That is, as shown in FIG. 7, in the semiconductor substrate 10 including the silicon, channels are formed along a <110> direction. Thus, the boron implanted along the channel direction is implanted deeper than the general projection range (or the ion-implantation depth). Because the boron is light and small, the nuclei stopping is hardly induced and the electronic stopping is mostly induced. Thus, the channeling effect can be induced well at the low energy.
Accordingly, in the embodiment, when the emitter layer 20 is formed, the semiconductor substrate 10 becomes amorphous before ion-implanting the second conductive type dopants, the second conductive type dopant such as boron is implanted into the amorphous portion or layer, and the heat-treating for activation is performed. Then, the growth through the solid phase epitaxy is induced from the silicon constituting the semiconductor substrate 10. In this case, the silicon constituting the semiconductor substrate 10 acts as the seed. Thus, the activation can be performed at a relatively low temperature.
Meanwhile, regarding the back surface field layer 30, arsenic (As) has an atomic number of 33 and is very heavy (relative atomic mass ˜75). Thus, as shown in FIG. 4, in the case of arsenic, the energy loss by the nuclei stopping is mostly induced, and the cross-ever energy is about 700 keV. That is, in an energy range of about 30˜300 keV that is usually used, the energy is mostly lost by the nuclei stopping. Phosphorus (P) has an atomic number of 15 and has a medium mass (relative atomic mass ˜31). The cross-ever energy of the phosphorus is about 130 keV. Thus, the energy is generally lost by the nuclei stopping below about 130 keV, and the energy is generally lost by the electronic stopping above about 130 keV. Phosphorus may be used as the first conductive type dopants for forming the back surface field layer 30, since the amount of the energy loss of the arsenic is large.
Also, referring to FIG. 6, in the case of the phosphorus, the temperature for the heat-treating for activation decreases rapidly when the dose is above about 1×10¹⁵/cm². This is because the back surface of the semiconductor substrate 10 becomes amorphous by the phosphorus at the above dose range and the growth through the solid phase epitaxy is induced from the silicon constituting the semiconductor substrate 10. In this case, the silicon constituting the semiconductor substrate 10 acts as the seed.
That is, first conductive type dopants such as phosphorus may be implanted with the dose of about 3×10¹⁵/cm²˜8×10¹⁵/cm²by using an energy below about 130 keV to sufficiently damage the back surface of the semiconductor substrate 10. Because of the lattice damage, the growth through the solid state epitaxy can be easily induced.
Next, as shown in FIG. 3 f, in the step ST60 for forming the anti-reflection film and the passivation film, the anti-reflection film 22 and the passivation film 32 are formed on the front surface and the back surface of the semiconductor substrate 10, respectively. The anti-reflection film 22 and the passivation film 32 may be formed by various methods such as a vacuum evaporation, a chemical vapor deposition, a spin coating, a screen printing, or a spray coating.
Next, in the step ST70 for forming the electrode, a front electrode layer 240 and a back electrode layer 340 are formed on the front surface and the back surface of the semiconductor substrate 10, respectively, and are fired to form a front electrode 24 (shown in FIG. 1) and a back electrode 34 (as shown in FIG. 1).
The front and back electrode layers 240 and 340 may be formed by coating a paste including metal having a high electric property (for example, siliver), glass frit, a binder, and a solvent. The front and back electrode layers 240 and 340 are coated on the semiconductor substrate 10 by a printing method. When the front and back electrode layers 240 and 340 are fired, by firing through, the front electrode 24 penetrates the anti-reflection film 22 and is in contact to the emitter layer 20, and the back electrode 34 penetrates the passivation film 32 and is in contact to the back surface field layer 30. Accordingly, the solar cell as shown 100 (shown in FIG. 1) is manufactured.
In the above embodiment, the emitter layer 20 and the back surface field layer 30 are doped with a uniform doping concentration, and thus, they have a uniform resistance, but is not limited thereto. But, as shown in FIG. 8, an emitter layer 20 can be a selective emitter structure, and a back surface field layer 30 can have a selective back surface field structure.
Particularly, the emitter layer 20 includes a first portion 20 a formed adjacent to the anti-reflection film 22 between the front electrodes 24, and a second portion 20 b being in contact with the front electrode 24. The second portion 20 b has a doping concentration higher than that of the first portion 20 a, and thus, the second portion 20 b has a resistance lower than that of the first portion 20 a.
Then, a shallow emitter can be achieved at the first portion 20 a where the sun light is incident, and thereby enhance the efficiency of the solar cell 100 a. In addition, contact resistance with the front electrode 24 can be reduced at the second portion 20 b being in contact with the front electrode 24. That is, when the emitter layer 20 has the selective emitter structure, the efficiency of the solar cell 100 a can be maximized.
In order to form the emitter layer 20, in a step ST20 (of FIG. 2 and FIG. 3 b) for forming an emitter layer by ion-implanting a second conductive type dopants, the second conductive type dopants is ion-implanted by using a comb mask. The second conductive type dopants are then ion-implanted with a relatively high doping concentration at a portion corresponding to the second portion 20 b. After that, in a step ST50 for heat-treating for activation, the second portion 20 b having a relatively low resistance is formed. However, the embodiment is not limited thereto. While one method has been described, emitter layer 20 having the selective emitter structure may be formed by various other methods.
The back surface field layer 30 includes a first portion 30 a formed at a portion corresponding to a portion between the back electrodes 34, and a second portion 30 b being in contact with the back electrode 34. The second portion 30 b has a doping concentration higher than that of the first portion 30 a, and thus, the second portion 30 b has a resistance lower than that of the first portion 30 a.
Then, the first portion 30 a of the back surface field layer 30 effectively prevents the recombination of the electrons and the holes, and the contact resistance with the back electrode 34 can be reduced by the second portion 30 b having a relatively low resistance. Therefore, the loss by the recombination of the electrons and the holes is reduced, and the electrons or the holes generated by the photoelectric effect can be effectively transferred to the back electrode 34. Accordingly, the efficiency of the solar cell 100 a is further improved.
In order to form the back surface field layer 30, in a step ST40 (of FIG. 2 and FIG. 3 d) for forming a back surface field layer by ion-implanting a first conductive type dopants, the first conductive type dopants are ion-implanted by using a comb mask. The first conductive type dopants are then ion-implanted with a relatively high doping concentration at a portion corresponding the second portion 30 b. After that, in a step ST50 for heat-treating for activation, the second portion 30 b having a relatively low resistance is formed. However, the embodiment is not limited thereto. While one method has been desribed, back surface field layer 30 having the selective back surface field structure may be formed by various other methods.
In the embodiment illustrated by FIG. 8, it is shown that the emitter layer 20 has the selective emitter structure and the back surface field layer 30 has the selective back surface structure. However, it is possible that only one of the emitter layer 20 and the back surface field layer 30 can have the selective structure.
In the embodiment, by using a pre-amorphization element, the temperature of the heat-treating for activating the first conductive type dopants and the temperature of the heat-treating for activating the second conductive type dopants are similar. Thus, the first and second conductive type dopants can be simultaneously heat-treated at the relatively low temperature. Accordingly, co-activation of the first and second conductive type dopants can be possible, and thus, the process can be simplified and the doping profile can be effectively controlled. Finally, the properties of the solar cell can be enhanced.
Certain embodiments of the invention have been described. However, the invention is not limited to the specific embodiments described above, and various modifications of the embodiments are possible by those skilled in the art to which the invention belongs without leaving the scope of the invention defined by the appended claims. Also, modifications of the embodiments should not be understood individually from the technical principles or prospects of the invention.

Claims

What is claimed is:

1. A method for manufacturing a solar cell, comprising:

preparing a semiconductor substrate having a first conductive type dopant;

ion-implanting a pre-amorphization element into a front surface of the semiconductor substrate to form an amorphous layer; and

forming an emitter layer by ion-implanting a second conductive type dopant into the front surface of the semiconductor substrate.

2. The method according to claim 1, wherein the pre-amorphization element and the second conductive type dopant are different from each other.

3. The method according to claim 2, wherein the pre-amorphization element has an atomic number larger than that of the second conductive type dopant.

4. The method according to claim 1, wherein the pre-amorphization element comprises at least one element selected from the group consisting of carbon group elements and noble gas group elements.

5. The method according to claim 1, wherein the pre-amorphization element comprises at least one of argon (Ar) and germanium (Ge).

6. The method according to claim 1, wherein the semiconductor substrate has an n-type, and wherein the second conductive type dopant comprises at least one of boron (B) and gallium (Ga).

7. The method according to claim 1, wherein, in the ion-implanting of the pre-amorphization element, a dose of the pre-amorphization element is in a range of about 1×10¹⁴/cm²˜3×10¹⁵/cm², and

wherein, in the forming the emitter layer, a dose of the second conductive type dopant is in a range of about 2×10¹⁵/cm^2˜4×10 ¹⁵/cm².

8. The method according to claim 1, wherein, after forming the emitter layer, further comprising:

heat-treating for activating the second conductive type dopant,

wherein, in the heat-treating, the second conductive type dopant is diffused into the semiconductor substrate deeper than the pre-amorphization element.

9. The method according to claim 1, wherein the emitter layer comprises a first layer including the pre-amorphization element and the second conductive type dopant and a second layer including the second conductive type dopant, and wherein

a thickness ratio of the emitter layer to the first layer is 1:0.05˜1:0.15.

10. The method according to claim 8, wherein, temperature of the heat-treating is in a range of about 400˜700° C.

11. The method according to claim 8, further comprising, between the preparing the semiconductor substrate and the forming the emitter layer or between the forming the emitter layer and the heat-treating:

forming a back surface field layer at a back surface of the semiconductor substrate by ion-implanting the first conductive type dopant into the back surface,

wherein, in the heat-treating, the emitter layer and the back surface field layer are simultaneously activated.

12. The method according to claim 11, wherein the first conductive type dopant comprises phosphorus (P).

13. A solar cell, comprising:

a semiconductor substrate having a first conductive type dopant;

an emitter layer formed at a front surface of the semiconductor substrate, the emitter layer comprising a second conductive type dopant and a pre-amorphization element having an atomic number larger than that of the second conductive type dopant;

a first electrode electrically connected to the emitter layer; and

a second electrode electrically connected to the semiconductor substrate.

14. The solar cell according to claim 13, wherein the emitter layer comprises:

a first layer adjacent to the front surface of the semiconductor substrate and including the pre-amorphization element and the second conductive type dopant; and

a second layer positioned at a portion of the semiconductor substrate deeper than the first layer and including the second conductive type dopant.

15. The solar cell according to claim 13, wherein the pre-amorphization element comprises at least one element selected from the group consisting of carbon group elements and noble gas group elements.

16. The solar cell according to claim 15, wherein the pre-amorphization element comprises at least one of argon (Ar) and germanium (Ge).

17. The solar cell according to claim 13, wherein the semiconductor substrate has an n-type, and wherein the second conductive type dopant comprises at least one of boron (B) and gallium (Ga).

18. The solar cell according to claim 13, wherein the second layer has a thickness larger than that of the first layer.

19. The solar cell according to claim 18, wherein a thickness ratio of the emitter layer to the first layer is 1:0.05˜1:0.15.

20. The solar cell according to claim 13, wherein the first conductive type dopant comprises phosphorus (P).