+

US20130113095A1 - Packaging substrate and fabrication method thereof - Google Patents

Packaging substrate and fabrication method thereof Download PDF

Info

Publication number
US20130113095A1
US20130113095A1 US13/482,313 US201213482313A US2013113095A1 US 20130113095 A1 US20130113095 A1 US 20130113095A1 US 201213482313 A US201213482313 A US 201213482313A US 2013113095 A1 US2013113095 A1 US 2013113095A1
Authority
US
United States
Prior art keywords
opening
dielectric layer
sub
layer
metal layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US13/482,313
Inventor
Chien-Lung Chuang
Po-Yi Wu
Meng-Tsung Lee
Yih-Jenn Jiang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siliconware Precision Industries Co Ltd
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Assigned to SILICONWARE PRECISION INDUSTRIES CO., LTD. reassignment SILICONWARE PRECISION INDUSTRIES CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHUANG, CHIEN-LUNG, JIANG, YIH-JENN, LEE, MENG-TSUNG, WU, PO-YI
Publication of US20130113095A1 publication Critical patent/US20130113095A1/en
Priority to US15/411,204 priority Critical patent/US10192838B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02123—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body inside the bonding area
    • H01L2224/02125—Reinforcing structures
    • H01L2224/02126—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0239—Material of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/024—Material of the insulating layers therebetween
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H01L2224/03614—Physical or chemical etching by chemical means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/03622—Manufacturing methods by patterning a pre-deposited material using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0501—Shape
    • H01L2224/05016—Shape in side view
    • H01L2224/05018—Shape in side view being a conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H01L2224/05027—Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05558—Shape in side view conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05562—On the entire exposed surface of the internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05575—Plural external layers
    • H01L2224/0558—Plural external layers being stacked
    • H01L2224/05582—Two-layer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10125—Reinforcing structures
    • H01L2224/10126—Bump collar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13006—Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/053—Oxides composed of metals from groups of the periodic table
    • H01L2924/0544—14th Group
    • H01L2924/05442—SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/07—Polyamine or polyimide
    • H01L2924/07025—Polyimide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/206—Length ranges
    • H01L2924/2064—Length ranges larger or equal to 1 micron less than 100 microns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/37—Effects of the manufacturing process
    • H01L2924/37001—Yield

Definitions

  • the present invention relates to packaging substrates and fabrication methods thereof, and more particularly, to a packaging substrate for solder bumps to be formed thereon and a fabrication method thereof.
  • a plurality of solder bumps are formed on the conductive pads of a semiconductor chip and electrically connected to a packaging substrate so as to electrically connect the semiconductor chip to the packaging substrate.
  • the flip-chip technology provides shorter electrical path and better electrical performance. Further, the inactive surface of the semiconductor chip can be exposed from the package structure so as to improve the heat dissipating efficiency.
  • FIG. 1 is a schematic cross-sectional view showing a packaging substrate having a UBM (under bump metallurgy) layer as disclosed by U.S. Pat. No. 5,937,320.
  • a titanium layer 11 a and a copper layer 11 b are formed on the conductive pads 101 of a semiconductor chip 10 first and then solder bumps 12 are formed on the copper layer 11 b corresponding in position to the conductive pads 101 . Thereafter, portions of the titanium layer 11 a and the copper layer 11 b that are uncovered by the solder bumps 12 are removed by etching so as to define a UBM layer 11 under each of the solder bumps 12 . As such, the solder bumps 12 are securely attached to the conductive pads 101 of the semiconductor chip 10 through the UBM layer 11 .
  • the titanium layer 11 a is etched faster than the copper layer 11 b, it results in serious side-etching of the titanium layer 11 a.
  • a significant undercut structure is formed as shown in FIG. 1 .
  • the undercut structure induces stress concentration such that the overall solder bump structure easily cracks at the stress concentration point, thereby reducing the product reliability.
  • the present invention provides a packaging substrate, which comprises: a base body having at least a conductive pad on a surface thereof; a dielectric layer formed on the surface of the base body and having at least a first opening for exposing the at least a conductive pad and at least a second opening formed at a periphery of the at least of a first opening; and a metal layer formed on the at least a conductive pad and the dielectric layer and extending to a sidewall of the at east a second opening.
  • the packaging substrate can comprise at least a solder bump formed on the metal layer.
  • the present invention further provides a fabrication method of a packaging substrate, which comprises: providing a base body having at least a conductive pad on a surface thereof and forming a dielectric layer on the surface of the base body and at least a first opening in the dielectric layer for exposing the at least a conductive pad; forming at least a second opening in the dielectric layer around a periphery of the at least a first opening; forming a metal layer on the dielectric layer and the at least a conductive pad such that the metal layer extends to a sidewall of the at least a second opening; and forming at least a solder bump on the metal layer.
  • the metal layer has an outer periphery corresponding in position to a sidewall of the at least a second opening, i.e., the outer periphery of the metal layer extends downward along the sidewall of the at least a second opening. Since it is not easy for an etch solution to flow upward to etch the metal layer, the present invention significantly eliminate side-etching of the metal layer and avoids an undesired undercut structure from occurrence, thereby improving the reliability of the thus-obtained product.
  • FIG. 1 is a schematic cross-sectional view showing a conventional packaging substrate having a UBM layer
  • FIGS. 2A to 2F are schematic cross-sectional views showing a packaging substrate and a fabrication method thereof according to the present invention, wherein FIG. 2 F′ shows another embodiment of FIG. 2F .
  • FIGS. 2A to 2F are schematic cross-sectional views showing a packaging substrate and a fabrication method thereof according to the present invention. Therein, FIG. 2 F′ shows another embodiment of FIG. 2F .
  • a base body 20 having a plurality of conductive pads 202 on a surface 201 of the base body 20 is provided.
  • a first sub-dielectric layer 21 a is formed on the surface 201 of the base body 20 and has a plurality of openings 210 formed therein for exposing the conductive pads 202 , respectively.
  • the base body 20 is a semiconductor wafer.
  • the first sub-dielectric layer 21 a is a passivating protection layer for protecting the surface of the semiconductor wafer from undesired contact with air.
  • the first sub-dielectric layer 21 a can be made of, but not limited to, SiN or SiOx.
  • a second sub-dielectric layer 21 b is formed on the conductive pads 202 and the first sub-dielectric layer 21 a.
  • the second sub-dielectric layer 21 b has a thickness greater than 10 um.
  • the second sub-dielectric layer 21 b further has a plurality of first openings 211 each having a wide top and a narrow bottom, and a plurality of ring-shaped second openings 212 formed around peripheries of the first openings 211 .
  • the first openings 211 are allowed to expose the conductive pads 202 , respectively, and the second openings 212 are allowed to expose a portion of the first sub-dielectric layer 21 a.
  • the second sub-dielectric layer 21 b can be made of polyimide (PI) or bis-Benzo-Cyclo-Butene (BCB).
  • a bottom width W 1 of each of the second openings 212 is equal to or larger than 10 um and a top width W 2 of each of the second openings 212 is equal to or larger than 20 um, that is, a bevel edge of the second opening 212 has a horizontally projected width W 3 of about 5 um.
  • PI polyimide
  • BCB bis-Benzo-Cyclo-Butene
  • a dielectric layer 21 instead of the first and second sub-dielectric layers 21 a, 21 b can be formed in accordance with the present invention, and the second openings 212 can have other shapes in addition to a ring shape.
  • a metal layer 23 is formed on the second sub-dielectric layer 21 b, the conductive pads 202 and the first sub-dielectric layer 21 a.
  • the metal layer 23 is multilayered and can be made of Ti/Cu, i.e., the metal layer 23 can sequentially have a titanium layer 23 a and a copper layer 23 b stacked on the titanium layer 23 a. But it should be noted that the present invention is not limited thereto.
  • a resist layer 24 is formed on the metal layer 23 and has a plurality of openings 240 corresponding in position to the conductive pads 202 , respectively. Therein, the walls of the openings 240 are located on the sidewalls of the second openings 212 close to the first openings 211 . Then, solder bumps 25 are formed on the metal layer 23 in the openings 240 of the resist layer 24 by electroplating.
  • the resist layer 24 is removed and a reflow process can be performed.
  • solder bumps 25 by using the solder bumps 25 as a mask, portions of the metal layer 23 that are uncovered by the solder bumps 25 are removed by etching such that a UBM layer 23 ′ having a seagull-shaped cross section is defined under each of the solder bumps 25 .
  • the metal layer 23 ′ covers the exposed portion of each of the conductive pads 202 , the sidewall of each of the first openings 211 , a portion of the second sub-dielectric layer 21 b between the first opening 211 and the second opening 212 , and a portion of or all of the sidewall of each of the second openings 212 proximate to a corresponding one of the first opening 211 .
  • a base body 20 is provided with a plurality of conductive pads 203 .
  • a passivating protection layer 26 made of SiN or SiOx is formed on the base body 20 and has openings formed therein for exposing the conductive pads 203 , respectively.
  • a first sub-dielectric layer 21 a made of PI or BCB is formed on the conductive pads 203 and the passivating protection layer 26 , and a plurality of openings 210 are formed in the first sub-dielectric layer 21 a for exposing the conductive pads 203 , respectively.
  • a metal layer (not shown) is formed in the openings 210 of the first sub-dielectric layer 21 a and on the conductive pads 203 .
  • a conductive seed layer is formed by sputtering, and the metal layer is formed on the conductive seed layer through electroplating and then patterned so as to form a redistribution layer 200 .
  • the redistribution layer 200 can be made of Ti/Cu, Ti/Cu/Ni or Ti/NiV/Cu.
  • the redistribution layer 200 electrically connects the conductive pads 203 and has a plurality of conductive pads 202 extending therefrom so as to increase the circuit layout flexibility.
  • a second sub-dielectric layer 21 b is formed on the redistribution layer 200 .
  • the second sub-dielectric layer 21 b can be made of, but not limited to, PI or BCB. Similarly, the second sub-dielectric layer 21 b has a plurality of first openings 211 formed corresponding in position to the conductive pads 202 so as to expose portions of the conductive pads 202 . In the present embodiment, the second sub-dielectric layer 21 b has a thickness greater than 10 um. A plurality of first openings 211 each having a wide top and a narrow bottom and a plurality of ring-shaped second openings 212 are formed in the second sub-dielectric layer 21 b. The first openings 211 expose the conductive pads 202 , respectively.
  • the second openings 212 are formed around peripheries of the first openings 211 for exposing portions of the first sub-dielectric layer 21 a.
  • a bottom width W 1 of each of the second openings 212 is equal to or larger than 10 um and a top width W 2 of each of the second openings 212 is equal to or larger than 20 um, that is, a bevel edge of the second opening 212 has a horizontally projected width W 3 of about 5 um.
  • the present invention is not limited thereto.
  • a metal layer 23 ′ is formed on each of the conductive pads 202 so as to cover the exposed portion of the conductive pad 202 , the sidewall of the first opening 211 , a portion of the second sub-dielectric layer 21 b between the first opening 211 and the second opening 212 , and the sidewall of the second opening 212 .
  • the metal layer 23 ′ can be made of Ti/Cu, i.e., the metal layer 23 ′ can sequentially have a titanium layer 23 a and a copper layer 23 b stacked on the titanium layer 23 a. But it should be noted that the present invention is not limited thereto.
  • a solder bump 25 is formed on the metal layer 23 ′.
  • the solder bump 25 is made of a lead-free solder material and reflowed to cover the conductive pad 202 and the metal layer 23 ′, thereby defining a UBM layer 23 ′ having a seagull-shaped cross-section under the solder bump 25 .
  • the present invention further provides a packaging substrate, which has: a base body 20 having a conductive pads 202 on a surface 201 ; a dielectric layer 21 formed on the surface 201 of the base body 20 and having a plurality of first openings 211 for exposing the conductive pad 202 and a second plurality of openings 212 formed around a periphery of each of the first openings 211 ; and a metal layer 23 ′ formed on the conductive pads 202 and the dielectric layer 21 around the conductive pads 202 and extending to a sidewall of each of the second opening 212 .
  • the packaging substrate further has a plurality of solder bumps 25 disposed on the metal layer 23 ′.
  • the second openings 212 each are formed around the periphery of a corresponding one of the first opening 211 .
  • the metal layer 23 ′ continuously covers the conductive pads 202 , the sidewall of each of the first openings 211 , a portion of the dielectric layer 21 between the first openings 211 and the second openings 212 , and the sidewall of each of the second openings 212 .
  • the first opening 211 has a circular shape and the second opening 212 has a ring shape.
  • the first opening 211 and the second opening 212 are concentric.
  • the dielectric layer 21 has a first sub-dielectric layer 21 a formed on the surface 201 of the base body 20 and a second sub-dielectric layer 21 b formed on the first sub-dielectric layer 21 a and having the first openings 211 and the second openings 212 .
  • the second openings 21 expose a portion of the first sub-dielectric layer 21 a .
  • the base body 20 can be a semiconductor wafer.
  • the first sub-dielectric layer 21 a can be made of SiN.
  • the second sub-dielectric layer 21 b can be made of PI or BCB.
  • a bottom width of the second opening 212 is equal to or larger than 10 um, and a top width W 2 of the second opening 212 is equal to or larger than 20 um.
  • the second opening 212 has a wide top and a narrow bottom.
  • the UBM layer 23 ′ is made of Ti/Cu.
  • the packaging substrate can have a UBM layer. Further, the packaging substrate can be mounted to another packaging substrate in a flip-chip manner or applied to a wafer level chip scale package (WLCSP).
  • WLCSP wafer level chip scale package
  • the metal layer has an outer periphery corresponding in position to an inner sidewall of the second opening. Since it is not easy for an etch solution to flow upward to etch the metal layer, the present invention significantly suppresses side-etching of the metal layer and avoids an undesired undercut structure, thereby improving the reliability of the overall structure.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A packaging substrate includes a base body having at least a conductive pad on a surface thereof, a dielectric layer formed on the surface of the base body and having at least a first opening for exposing the conductive pad and at least a second opening formed at a periphery of the first opening, and a metal layer formed on the conductive pad and the dielectric layer and extending to a sidewall of the second opening, thereby effectively eliminating side-etching of the metal layer under a solder bump.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to packaging substrates and fabrication methods thereof, and more particularly, to a packaging substrate for solder bumps to be formed thereon and a fabrication method thereof.
  • 2. Description of Related Art
  • In a conventional flip-chip semiconductor package, a plurality of solder bumps are formed on the conductive pads of a semiconductor chip and electrically connected to a packaging substrate so as to electrically connect the semiconductor chip to the packaging substrate. Compared with wire bonding, the flip-chip technology provides shorter electrical path and better electrical performance. Further, the inactive surface of the semiconductor chip can be exposed from the package structure so as to improve the heat dissipating efficiency.
  • FIG. 1 is a schematic cross-sectional view showing a packaging substrate having a UBM (under bump metallurgy) layer as disclosed by U.S. Pat. No. 5,937,320. Referring to FIG. 1, a titanium layer 11 a and a copper layer 11 b are formed on the conductive pads 101 of a semiconductor chip 10 first and then solder bumps 12 are formed on the copper layer 11 b corresponding in position to the conductive pads 101. Thereafter, portions of the titanium layer 11 a and the copper layer 11 b that are uncovered by the solder bumps 12 are removed by etching so as to define a UBM layer 11 under each of the solder bumps 12. As such, the solder bumps 12 are securely attached to the conductive pads 101 of the semiconductor chip 10 through the UBM layer 11.
  • However, during the etching process, since the titanium layer 11 a is etched faster than the copper layer 11 b, it results in serious side-etching of the titanium layer 11 a. As such, a significant undercut structure is formed as shown in FIG. 1. The undercut structure induces stress concentration such that the overall solder bump structure easily cracks at the stress concentration point, thereby reducing the product reliability.
  • Therefore, there is a need to provide a packaging substrate and a fabrication method thereof such that the significant undercut structure caused by serious side-etching of the UBM layer can be avoided so as to increase the product reliability and yield.
    • SUMMARY OF THE INVENTION
  • Accordingly, the present invention provides a packaging substrate, which comprises: a base body having at least a conductive pad on a surface thereof; a dielectric layer formed on the surface of the base body and having at least a first opening for exposing the at least a conductive pad and at least a second opening formed at a periphery of the at least of a first opening; and a metal layer formed on the at least a conductive pad and the dielectric layer and extending to a sidewall of the at east a second opening.
  • Further, the packaging substrate can comprise at least a solder bump formed on the metal layer.
  • The present invention further provides a fabrication method of a packaging substrate, which comprises: providing a base body having at least a conductive pad on a surface thereof and forming a dielectric layer on the surface of the base body and at least a first opening in the dielectric layer for exposing the at least a conductive pad; forming at least a second opening in the dielectric layer around a periphery of the at least a first opening; forming a metal layer on the dielectric layer and the at least a conductive pad such that the metal layer extends to a sidewall of the at least a second opening; and forming at least a solder bump on the metal layer.
  • According to the present invention, the metal layer has an outer periphery corresponding in position to a sidewall of the at least a second opening, i.e., the outer periphery of the metal layer extends downward along the sidewall of the at least a second opening. Since it is not easy for an etch solution to flow upward to etch the metal layer, the present invention significantly eliminate side-etching of the metal layer and avoids an undesired undercut structure from occurrence, thereby improving the reliability of the thus-obtained product.
    • BRIEF DESCRIPTION OF DRAWINGS
  • FIG. 1 is a schematic cross-sectional view showing a conventional packaging substrate having a UBM layer; and
  • FIGS. 2A to 2F are schematic cross-sectional views showing a packaging substrate and a fabrication method thereof according to the present invention, wherein FIG. 2F′ shows another embodiment of FIG. 2F.
    •  DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
  • The following illustrative embodiments are provided to illustrate the disclosure of the present invention, these and other advantages and effects can be apparent to those in the art after reading this specification.
  • It should be noted that all the drawings are not intended to limit the present invention. Various modification and variations can be made without departing from the spirit of the present invention. Further, terms such as “one”, “on”, “top”, “bottom” etc. are merely for illustrative purpose and should not be construed to limit the scope of the present invention.
  • FIGS. 2A to 2F are schematic cross-sectional views showing a packaging substrate and a fabrication method thereof according to the present invention. Therein, FIG. 2F′ shows another embodiment of FIG. 2F.
  • Referring to FIG. 2A, a base body 20 having a plurality of conductive pads 202 on a surface 201 of the base body 20 is provided. A first sub-dielectric layer 21 a is formed on the surface 201 of the base body 20 and has a plurality of openings 210 formed therein for exposing the conductive pads 202, respectively. In the present embodiment, the base body 20 is a semiconductor wafer. The first sub-dielectric layer 21 a is a passivating protection layer for protecting the surface of the semiconductor wafer from undesired contact with air. The first sub-dielectric layer 21 a can be made of, but not limited to, SiN or SiOx.
  • Referring to FIG. 2B, a second sub-dielectric layer 21 b is formed on the conductive pads 202 and the first sub-dielectric layer 21 a. In the present embodiment, the second sub-dielectric layer 21 b has a thickness greater than 10 um. The second sub-dielectric layer 21 b further has a plurality of first openings 211 each having a wide top and a narrow bottom, and a plurality of ring-shaped second openings 212 formed around peripheries of the first openings 211. The first openings 211 are allowed to expose the conductive pads 202, respectively, and the second openings 212 are allowed to expose a portion of the first sub-dielectric layer 21 a. The second sub-dielectric layer 21 b can be made of polyimide (PI) or bis-Benzo-Cyclo-Butene (BCB). A bottom width W1 of each of the second openings 212 is equal to or larger than 10 um and a top width W2 of each of the second openings 212 is equal to or larger than 20 um, that is, a bevel edge of the second opening 212 has a horizontally projected width W3 of about 5 um. But it should be noted that the present invention is not limited thereto.
  • In addition, a dielectric layer 21 instead of the first and second sub-dielectric layers 21 a, 21 b can be formed in accordance with the present invention, and the second openings 212 can have other shapes in addition to a ring shape.
  • Referring to FIG. 2C, a metal layer 23 is formed on the second sub-dielectric layer 21 b, the conductive pads 202 and the first sub-dielectric layer 21 a. The metal layer 23 is multilayered and can be made of Ti/Cu, i.e., the metal layer 23 can sequentially have a titanium layer 23 a and a copper layer 23 b stacked on the titanium layer 23 a. But it should be noted that the present invention is not limited thereto.
  • Referring to FIG. 2D, a resist layer 24 is formed on the metal layer 23 and has a plurality of openings 240 corresponding in position to the conductive pads 202, respectively. Therein, the walls of the openings 240 are located on the sidewalls of the second openings 212 close to the first openings 211. Then, solder bumps 25 are formed on the metal layer 23 in the openings 240 of the resist layer 24 by electroplating.
  • Referring to FIG. 2E, the resist layer 24 is removed and a reflow process can be performed.
  • Referring to FIG. 2F, by using the solder bumps 25 as a mask, portions of the metal layer 23 that are uncovered by the solder bumps 25 are removed by etching such that a UBM layer 23′ having a seagull-shaped cross section is defined under each of the solder bumps 25. The metal layer 23′ covers the exposed portion of each of the conductive pads 202, the sidewall of each of the first openings 211, a portion of the second sub-dielectric layer 21 b between the first opening 211 and the second opening 212, and a portion of or all of the sidewall of each of the second openings 212 proximate to a corresponding one of the first opening 211.
  • In another embodiment of the present invention, as shown in FIG. 2F′, a base body 20 is provided with a plurality of conductive pads 203. A passivating protection layer 26 made of SiN or SiOx is formed on the base body 20 and has openings formed therein for exposing the conductive pads 203, respectively. A first sub-dielectric layer 21 a made of PI or BCB is formed on the conductive pads 203 and the passivating protection layer 26, and a plurality of openings 210 are formed in the first sub-dielectric layer 21 a for exposing the conductive pads 203, respectively. Thereafter, a metal layer (not shown) is formed in the openings 210 of the first sub-dielectric layer 21 a and on the conductive pads 203. Particularly, a conductive seed layer is formed by sputtering, and the metal layer is formed on the conductive seed layer through electroplating and then patterned so as to form a redistribution layer 200. The redistribution layer 200 can be made of Ti/Cu, Ti/Cu/Ni or Ti/NiV/Cu. The redistribution layer 200 electrically connects the conductive pads 203 and has a plurality of conductive pads 202 extending therefrom so as to increase the circuit layout flexibility. Further, a second sub-dielectric layer 21 b is formed on the redistribution layer 200. The second sub-dielectric layer 21 b can be made of, but not limited to, PI or BCB. Similarly, the second sub-dielectric layer 21 b has a plurality of first openings 211 formed corresponding in position to the conductive pads 202 so as to expose portions of the conductive pads 202. In the present embodiment, the second sub-dielectric layer 21 b has a thickness greater than 10 um. A plurality of first openings 211 each having a wide top and a narrow bottom and a plurality of ring-shaped second openings 212 are formed in the second sub-dielectric layer 21 b. The first openings 211 expose the conductive pads 202, respectively. The second openings 212 are formed around peripheries of the first openings 211 for exposing portions of the first sub-dielectric layer 21 a. A bottom width W1 of each of the second openings 212 is equal to or larger than 10 um and a top width W2 of each of the second openings 212 is equal to or larger than 20 um, that is, a bevel edge of the second opening 212 has a horizontally projected width W3 of about 5 um. But it should be noted that the present invention is not limited thereto. Thereafter, a metal layer 23′ is formed on each of the conductive pads 202 so as to cover the exposed portion of the conductive pad 202, the sidewall of the first opening 211, a portion of the second sub-dielectric layer 21 b between the first opening 211 and the second opening 212, and the sidewall of the second opening 212. The metal layer 23′ can be made of Ti/Cu, i.e., the metal layer 23′ can sequentially have a titanium layer 23 a and a copper layer 23 b stacked on the titanium layer 23 a. But it should be noted that the present invention is not limited thereto. Further, a solder bump 25 is formed on the metal layer 23′. In the present embodiment, the solder bump 25 is made of a lead-free solder material and reflowed to cover the conductive pad 202 and the metal layer 23′, thereby defining a UBM layer 23′ having a seagull-shaped cross-section under the solder bump 25.
  • The present invention further provides a packaging substrate, which has: a base body 20 having a conductive pads 202 on a surface 201; a dielectric layer 21 formed on the surface 201 of the base body 20 and having a plurality of first openings 211 for exposing the conductive pad 202 and a second plurality of openings 212 formed around a periphery of each of the first openings 211; and a metal layer 23′ formed on the conductive pads 202 and the dielectric layer 21 around the conductive pads 202 and extending to a sidewall of each of the second opening 212.
  • The packaging substrate further has a plurality of solder bumps 25 disposed on the metal layer 23′.
  • In the above-described packaging substrate, the second openings 212 each are formed around the periphery of a corresponding one of the first opening 211. The metal layer 23′ continuously covers the conductive pads 202, the sidewall of each of the first openings 211, a portion of the dielectric layer 21 between the first openings 211 and the second openings 212, and the sidewall of each of the second openings 212.
  • In the present embodiment, the first opening 211 has a circular shape and the second opening 212 has a ring shape. The first opening 211 and the second opening 212 are concentric. Further, the dielectric layer 21 has a first sub-dielectric layer 21 a formed on the surface 201 of the base body 20 and a second sub-dielectric layer 21 b formed on the first sub-dielectric layer 21 a and having the first openings 211 and the second openings 212. The second openings 21 expose a portion of the first sub-dielectric layer 21 a.
  • The base body 20 can be a semiconductor wafer. The first sub-dielectric layer 21 a can be made of SiN. The second sub-dielectric layer 21 b can be made of PI or BCB.
  • A bottom width of the second opening 212 is equal to or larger than 10 um, and a top width W2 of the second opening 212 is equal to or larger than 20 um.
  • The second opening 212 has a wide top and a narrow bottom. The UBM layer 23′ is made of Ti/Cu.
  • The packaging substrate can have a UBM layer. Further, the packaging substrate can be mounted to another packaging substrate in a flip-chip manner or applied to a wafer level chip scale package (WLCSP).
  • According to the present invention, the metal layer has an outer periphery corresponding in position to an inner sidewall of the second opening. Since it is not easy for an etch solution to flow upward to etch the metal layer, the present invention significantly suppresses side-etching of the metal layer and avoids an undesired undercut structure, thereby improving the reliability of the overall structure.
  • The above-described descriptions of the detailed embodiments are only to illustrate the preferred implementation according to the present invention, and it is not to limit the scope of the present invention. Accordingly, all modifications and variations completed by those with ordinary skill in the art should fall within the scope of present invention defined by the appended claims.

Claims (20)

What is claimed is:
1. A packaging substrate, comprising:
a base body having at least a conductive pad on a surface;
a dielectric layer formed on the surface of the base body and having at least a first opening for exposing the at last a conductive pad and at least a second opening formed at a periphery of the first opening; and
a metal layer formed on the at least a conductive pad and the dielectric layer and extending to a sidewall of the second opening.
2. The substrate of claim 1, further comprising at least of a solder bump disposed on the metal layer.
3. The substrate of claim 1, wherein the at least a second opening is formed around the periphery of the at least a first opening.
4. The substrate of claim 1, wherein the metal layer continuously covers the at least a conductive pad, a sidewall of the at least a first opening, a portion of the dielectric layer between the at least a first opening and the at least a second opening, and the sidewall of the at least a second opening.
5. The substrate of claim 1, wherein the at least a first opening has a circular shape, the at least a second opening has a ring shape, and the at least a first and second openings are concentric.
6. The substrate of claim 1, wherein the dielectric layer comprises a first sub-dielectric layer formed on the surface of the base body, and a second sub-dielectric layer formed on the first sub-dielectric layer and having the at least a first opening and the at least a second opening, wherein the at least a second opening exposes a portion of the first sub-dielectric layer.
7. The substrate of claim 6, wherein the first sub-dielectric layer is made of SiN, and the second sub-dielectric layer is made of polyimide (PI) or bis-Benzo-Cyclo-Butene (BCB).
8. The substrate of claim 1, wherein a bottom width of the at least a second opening is equal to or larger than 10 um.
9. The substrate of claim 1, wherein a top width of the at least a second opening is equal to or larger than 20 um.
10. The substrate of claim 1, wherein the at least a second opening has a wide top and a narrow bottom.
11. The substrate of claim 1, wherein the metal layer is multilayered and comprises Ti/Cu.
12. A fabrication method of a packaging substrate, comprising:
providing a base body having at least a conductive pad on a surface thereof and a dielectric layer formed on the surface of the base body and at least a first opening formed in the dielectric layer for exposing the at least a conductive pad;
forming at least a second opening in the dielectric layer around a periphery of the at least a first opening;
forming a metal layer on the dielectric layer and the at least a conductive pad, wherein the metal layer extends to a sidewall of the at least a second opening; and
forming at least a solder bump on the metal layer.
13. The method of claim 12, wherein forming the at least a solder bump on the metal layer comprises:
forming a resist layer on the metal layer, wherein the resist layer has at least an opening corresponding in position to the at least a conductive pad and the opening has a wall located on the sidewall of the at least a second opening;
forming the at least solder bump on the metal layer in the opening of the resist layer;
removing the resist layer; and
etching a portion of the metal layer uncovered by the at least a solder bump.
14. The method of claim 13, after removing the resist layer, further comprising reflowing the at least a solder bump.
15. The method of claim 12, wherein the dielectric layer comprises a first sub-dielectric layer formed on the surface of the base body, and a second sub-dielectric layer formed on the first sub-dielectric layer and having the at least a first opening and the at least a second opening, wherein a portion of the first sub-dielectric layer is exposed from the at least a second opening.
16. The method of claim 15, wherein the first sub-dielectric layer is made of SiN, and the second sub-dielectric layer is made of polyimide (PI) or bis-Benzo-Cyclo-Butene (BCB).
17. The method of claim 12, wherein a bottom width of the at least a second opening is equal to or larger than 10 um.
18. The method of claim 12, wherein a top width of the at least a second opening is equal to or larger than 20 um.
19. The method of claim 12, wherein the at least a second opening has a wide top and a narrow bottom.
20. The method of claim 12, wherein the metal layer is multilayered and comprises Ti/Cu.
US13/482,313 2011-11-04 2012-05-29 Packaging substrate and fabrication method thereof Abandoned US20130113095A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/411,204 US10192838B2 (en) 2011-11-04 2017-01-20 Fabrication method of packaging substrate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW100140252A TWI463621B (en) 2011-11-04 2011-11-04 Package substrate and fabrication method thereof
TW100140252 2011-11-04

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US15/411,204 Division US10192838B2 (en) 2011-11-04 2017-01-20 Fabrication method of packaging substrate

Publications (1)

Publication Number Publication Date
US20130113095A1 true US20130113095A1 (en) 2013-05-09

Family

ID=48206642

Family Applications (2)

Application Number Title Priority Date Filing Date
US13/482,313 Abandoned US20130113095A1 (en) 2011-11-04 2012-05-29 Packaging substrate and fabrication method thereof
US15/411,204 Active US10192838B2 (en) 2011-11-04 2017-01-20 Fabrication method of packaging substrate

Family Applications After (1)

Application Number Title Priority Date Filing Date
US15/411,204 Active US10192838B2 (en) 2011-11-04 2017-01-20 Fabrication method of packaging substrate

Country Status (3)

Country Link
US (2) US20130113095A1 (en)
CN (1) CN103094243A (en)
TW (1) TWI463621B (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140203438A1 (en) * 2013-01-18 2014-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and Apparatus of Packaging of Semiconductor Devices
US20140319695A1 (en) * 2013-04-24 2014-10-30 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Stress-Reduced Conductive Joint Structures
US20210384144A1 (en) * 2016-09-12 2021-12-09 Samsung Electronics Co., Ltd. Semiconductor device and semiconductor package
US11302661B2 (en) 2019-12-26 2022-04-12 Samsung Electronics Co., Ltd. Package substrate including segment grooves arranged in a radial direction of a redistribution pad and semiconductor package including the same
CN118676110A (en) * 2024-08-23 2024-09-20 甬矽半导体(宁波)有限公司 Substrate wiring structure and preparation method thereof

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10163828B2 (en) * 2013-11-18 2018-12-25 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and fabricating method thereof
US10008461B2 (en) 2015-06-05 2018-06-26 Micron Technology, Inc. Semiconductor structure having a patterned surface structure and semiconductor chips including such structures
TWI669793B (en) * 2016-04-27 2019-08-21 矽品精密工業股份有限公司 Substrate structure

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6323542B1 (en) * 1997-01-17 2001-11-27 Seiko Epson Corporation Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument
US20080230877A1 (en) * 2007-03-19 2008-09-25 Samsung Electronics Co., Ltd. Semiconductor package having wire redistribution layer and method of fabricating the same
US20090015285A1 (en) * 2007-07-11 2009-01-15 International Business Machines Corporation Test structures for electrically detecting back end of the line failures and methods of making and using the same
US20090057892A1 (en) * 2007-09-04 2009-03-05 Takatoshi Osumi Electrode structure in semiconductor device and related technology

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5937320A (en) 1998-04-08 1999-08-10 International Business Machines Corporation Barrier layers for electroplated SnPb eutectic solder joints
TWI268564B (en) * 2005-04-11 2006-12-11 Siliconware Precision Industries Co Ltd Semiconductor device and fabrication method thereof
TWI288447B (en) * 2005-04-12 2007-10-11 Siliconware Precision Industries Co Ltd Conductive bump structure for semiconductor device and fabrication method thereof
CN100580897C (en) * 2007-02-05 2010-01-13 百慕达南茂科技股份有限公司 Method for manufacturing flat top protrusion block structure

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6323542B1 (en) * 1997-01-17 2001-11-27 Seiko Epson Corporation Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument
US20080230877A1 (en) * 2007-03-19 2008-09-25 Samsung Electronics Co., Ltd. Semiconductor package having wire redistribution layer and method of fabricating the same
US20090015285A1 (en) * 2007-07-11 2009-01-15 International Business Machines Corporation Test structures for electrically detecting back end of the line failures and methods of making and using the same
US20090057892A1 (en) * 2007-09-04 2009-03-05 Takatoshi Osumi Electrode structure in semiconductor device and related technology

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140203438A1 (en) * 2013-01-18 2014-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and Apparatus of Packaging of Semiconductor Devices
US9349665B2 (en) * 2013-01-18 2016-05-24 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of packaging of semiconductor devices
US20140319695A1 (en) * 2013-04-24 2014-10-30 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Stress-Reduced Conductive Joint Structures
US9349700B2 (en) * 2013-04-24 2016-05-24 Stats Chippac, Ltd. Semiconductor device and method of forming stress-reduced conductive joint structures
US20210384144A1 (en) * 2016-09-12 2021-12-09 Samsung Electronics Co., Ltd. Semiconductor device and semiconductor package
US11791286B2 (en) * 2016-09-12 2023-10-17 Samsung Electronics Co., Ltd. Semiconductor device and semiconductor package
US11302661B2 (en) 2019-12-26 2022-04-12 Samsung Electronics Co., Ltd. Package substrate including segment grooves arranged in a radial direction of a redistribution pad and semiconductor package including the same
US11756908B2 (en) 2019-12-26 2023-09-12 Samsung Electronics Co., Ltd. Package substrate including a redistribution pad extending from a redistribution layer and including segmenting grooves along a redial direction thereof and semiconductor package including the same
US12176308B2 (en) 2019-12-26 2024-12-24 Samsung Electronics Co., Ltd. Package substrate and semiconductor package including the same
CN118676110A (en) * 2024-08-23 2024-09-20 甬矽半导体(宁波)有限公司 Substrate wiring structure and preparation method thereof

Also Published As

Publication number Publication date
TW201320269A (en) 2013-05-16
TWI463621B (en) 2014-12-01
US20170133337A1 (en) 2017-05-11
CN103094243A (en) 2013-05-08
US10192838B2 (en) 2019-01-29

Similar Documents

Publication Publication Date Title
US10192838B2 (en) Fabrication method of packaging substrate
US9515038B2 (en) Electrical connection for chip scale packaging
US9741659B2 (en) Electrical connections for chip scale packaging
TWI467715B (en) Improved wafer level chip scale packaging
US9293403B2 (en) Semiconductor package with improved redistribution layer design and fabricating method thereof
EP2229694B1 (en) Semiconductor chip under-bump metallization structure and manufacturing method thereof
US8211789B2 (en) Manufacturing method of a bump structure having a reinforcement member
US20090045511A1 (en) Integrated circuit including parylene material layer
US20180135185A1 (en) Fabrication method of substrate having electrical interconnection structures
US9941248B2 (en) Package structures, pop devices and methods of forming the same
US8895357B2 (en) Integrated circuit and method of manufacturing the same
US20120280384A1 (en) Semiconductor structure and fabrication method thereof
US20130256871A1 (en) Semiconductor chip device with fragmented solder structure pads
US8294266B2 (en) Conductor bump method and apparatus
US11335659B2 (en) Semiconductor chip with patterned underbump metallization and polymer film
JP5262277B2 (en) Semiconductor device and substrate bonding method
US20120261812A1 (en) Semiconductor chip with patterned underbump metallization
TW202010027A (en) Chip structure
JP2008091774A (en) Semiconductor device
JP2007095894A (en) Semiconductor device and method of manufacturing same
JP2005159004A (en) Semiconductor device and manufacturing method thereof

Legal Events

Date Code Title Description
AS Assignment

Owner name: SILICONWARE PRECISION INDUSTRIES CO., LTD., TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHUANG, CHIEN-LUNG;WU, PO-YI;LEE, MENG-TSUNG;AND OTHERS;REEL/FRAME:028280/0959

Effective date: 20111104

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION

点击 这是indexloc提供的php浏览器服务，不要输入任何密码和下载