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US20130020687A1 - Power module package and method for manufacturing the same - Google Patents

Power module package and method for manufacturing the same Download PDF

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Publication number
US20130020687A1
US20130020687A1 US13/301,616 US201113301616A US2013020687A1 US 20130020687 A1 US20130020687 A1 US 20130020687A1 US 201113301616 A US201113301616 A US 201113301616A US 2013020687 A1 US2013020687 A1 US 2013020687A1
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United States
Prior art keywords
lead frames
ceramic coating
power module
lead frame
module package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US13/301,616
Inventor
Kwang Soo Kim
Young Ki Lee
Seog Moon Choi
Jin Suk SON
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electro Mechanics Co Ltd
Original Assignee
Samsung Electro Mechanics Co Ltd
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Filing date
Publication date
Application filed by Samsung Electro Mechanics Co Ltd filed Critical Samsung Electro Mechanics Co Ltd
Assigned to SAMSUNG ELECTRO-MECHANICS CO. LTD reassignment SAMSUNG ELECTRO-MECHANICS CO. LTD ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SON, JIN SUK, CHOI, SEOG MOON, KIM, KWANG SOO, LEE, YOUNG KI
Publication of US20130020687A1 publication Critical patent/US20130020687A1/en
Priority to US13/973,644 priority Critical patent/US9318352B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/16—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
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    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49586—Insulating layers on lead frames
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    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group subclass H10D
    • H01L25/072—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group subclass H10D the devices being arranged next to each other
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
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    • H01L2924/1305—Bipolar Junction Transistor [BJT]
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
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    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
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    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to a power module package and a method for manufacturing the same.
  • IPM intelligent power module
  • a high-capacity power device for example, a high-capacity insulated gate bipolar transistor (IGBT), or the like
  • IGBT insulated gate bipolar transistor
  • the present invention has been made in an effort to provide a power module package and a method for manufacturing the same capable of improving heat radiation characteristics by forming a ceramic coating layer in the power module package.
  • a power module package including: first and second lead frames disposed to face each other; ceramic coating layers formed on a portion of a first surface of both or one of both of the first and second lead frames; and semiconductor devices mounted on second surfaces of the first and second lead frames.
  • the ceramic coating layer may be formed by a sol-gel method.
  • the semiconductor device may include a power device and a control device, and when the ceramic coating layers are formed on both of the first and second lead frames, the second surface of the first lead frame may be mounted with the power device and the second surface of the second lead frame may be mounted with the control device.
  • the semiconductor device may include a power device and a control device, and when the ceramic coating layer is formed on the first lead frame, the second surface of the first lead frame may be mounted with the power device and the second surface of the second lead frame may be mounted with the control device.
  • the power module package may further include a thermal diffusion layer made of a metal material formed on a lower surface of the ceramic coating layer over the first and second lead frames.
  • Both or one of both of the first and second lead frames may have a down-set structure.
  • the power module package may further include: a wire electrically connecting between the semiconductor devices or between the semiconductor device and the lead frame; and a molding formed on upper portions of the first and second lead frames, between the first lead frame and the second lead frame, and on a portion of lower portions of the first and second lead frames.
  • the molding may be formed in a form that exposes the ceramic coating layer formed on the lower portions of the first and second lead frames.
  • a method for manufacturing a power module package including: preparing first and second lead frames disposed to face each other; forming ceramic coating layers on a portion of a first surface of both or one of both of the first and second lead frames; and mounting semiconductor devices on second surfaces of the first and second lead frames.
  • the ceramic coating layer may be formed by a sol-gel method.
  • the semiconductor device may include a power device and a control device, and when the ceramic coating layers are formed on both of the first and second lead frames, at the mounting of the semiconductor device, the second surface of the first lead frame may be mounted with the power device and the second surface of the second lead frame may be mounted with the control device.
  • the semiconductor device may include a power device and a control device, and when the ceramic coating layer is formed on the first lead frame, at the mounting of the semiconductor device, the second surface of the first lead frame may be mounted with the power device and the second surface of the second lead frame may be mounted with the control device.
  • the method for manufacturing a power module package may further include: after the mounting of the semiconductor device, forming a wire electrically connecting between the semiconductor devices or between the semiconductor device and the lead frame; and forming a molding so as to cover the upper portion of the semiconductor device mounted between the first and second lead frames, on a portion of lower portions of the first and second lead frames, and upper portions of the first lead frame and the second lead frame.
  • the method for manufacturing a power module package may further include: prior to forming of the molding, forming a thermal diffusion layer made of a metal material on a lower surface of the ceramic coating layer over the first and second lead frames.
  • the method may further include: after the forming of the molding, forming forms of the first and second lead frames.
  • the method for manufacturing a power module package may further include: prior to the forming of the molding, forming a form having a down-set structure on both or one of both of the first and second lead frames.
  • the molding may be formed in a form that exposes the ceramic coating layers formed on the lower portions of the first and second lead frames.
  • FIG. 1 is a diagram showing a structure of a power module package according to a first preferred embodiment of the present invention.
  • FIG. 2 is a diagram showing a structure of a power module package according to a second preferred embodiment of the present invention.
  • FIG. 3 is a diagram showing a structure of a power module package according to a third preferred embodiment of the present invention.
  • FIGS. 4 to 8 are process flow charts for explaining a method for manufacturing a power module package according to the first preferred embodiment of the present invention.
  • FIG. 9 is a diagram for explaining thermal distribution of the power module package according to the preferred embodiment of the present invention.
  • FIG. 10 is a diagram showing a structure of a power module package according to a fourth preferred embodiment of the present invention.
  • FIG. 1 is a diagram showing a structure of a power module package according to a first preferred embodiment of the present invention.
  • a power module package 100 may include first and second lead frames 111 and 113 that are disposed to face each other, ceramic coating layers 120 , 121 , and 123 that are formed on a portion of a first surface of both or one of both of the first and second lead frames 111 and 113 , and a semiconductor device 130 that is mounted on second surfaces of the first and second lead frames.
  • the ceramic coating layers 120 , 121 , and 123 may be selectively formed only in an area (a bottom of the semiconductor device of FIG. 1 ) that may generate high heat.
  • the ceramic coating layers 120 , 121 , and 123 may be formed by a sol-gel method that uses low-temperature firing.
  • coating is performed by melting an inorganic body (aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN), boron nitride (BN), or the like) in a solvent, together with additives such as a binder component.
  • Al 2 O 3 aluminum nitride
  • AlN aluminum nitride
  • BN boron nitride
  • coating is performed by melting an inorganic body (aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN), boron nitride (BN), or the like) in a solvent, together with additives such as a binder component.
  • Al 2 O 3 aluminum nitride
  • BN boron nitride
  • a shadow mask, a photo resist (PR), a dry film resist (DFR), a masking tape, or the like may be applied so as to selectively form the ceramic coating layers 120 , 121 , and 123 on the first and second lead frames 111 and 113 .
  • a spray method, a bar coating method, or a screen printing method, or the like may be applied.
  • the ceramic coating layers 120 , 121 , and 123 may be formed to have 10 ⁇ M to 1 mm, but the preferred embodiment of the present invention is not limited thereto.
  • the ceramic coating layers 120 , 121 , and 123 according to the preferred embodiment of the present invention are directly formed on the first and second lead frames 111 and 113 without an adhesive, the heat transfer efficiency may be further improved.
  • the semiconductor device 130 may include a power device 131 and a control device 133 .
  • the power device 131 may be an insulated gate bipolar transistor (IGBT), a diode, or the like, that may generate high heat and the control device 133 may include a control integrated circuit (IC), or the like, that may generate lower heat that the power device.
  • IGBT insulated gate bipolar transistor
  • IC control integrated circuit
  • the power device 131 may be mounted on the second surface of the first lead frame 111 and the control device 133 may be mounted on the second surface of the second lead frame 113 .
  • both or one of both of the first and second lead frames 111 and 113 may be a down-set structure in a bent form so as to form a step as shown in FIG. 1 .
  • the power module package 100 may further include wires 140 , 141 , and 143 that electrically connect between the semiconductor devices 131 and 133 or between semiconductor devices 131 and 133 and the lead frames 110 , 111 , and 113 .
  • the wire 143 formed between the semiconductor device and the lead frame may be formed between the other lead frame rather than the first and second lead frames equipped with the semiconductor device and the semiconductor device.
  • the power module package 100 may further include a molding 150 that is formed on the upper portions of the first and second lead frames 111 and 113 , between the first lead frame 111 and the second lead frame 113 , and on a portion of the lower portions of the first and second lead frames 111 and 113 .
  • the molding 150 may be formed in a structure in which the ceramic coating layers 120 , 121 , and 123 formed on the lower portions of the first and second lead frames 111 and 113 are exposed.
  • FIG. 9 is a diagram thermal distribution of the power module package adopting the ceramic coating layer of the present invention and a general ceramic substrate.
  • FIG. 9A is a diagram showing thermal distribution around a mounting area (A of FIG. 9A ) of the semiconductor device of the power module package to which the ceramic coating layer having a thickness of 100 ⁇ m is applied
  • FIG. 9B is a diagram showing the thermal distribution around the mounting area (B of FIG. 9B ) of the semiconductor device of the power module package to which the ceramic substrate having a thickness of 1000 ⁇ m is applied.
  • the ceramic coating layers 120 , 121 , and 123 according to the preferred embodiment of the present invention has higher heat conductivity than the power module package adopting the general ceramic substrate, thereby rapidly emitting heat from the semiconductor device 130 having a large calorific value to the outside.
  • the general power module package cannot simultaneously manufacture the ceramic substrate and the lead frame using a high-temperature firing method, the ceramic substrate is manufactured and then, the ceramic substrate is bonded to the lead frame using an adhesive, such that the additional material or process may be required and the heat resistance may be increased.
  • the power module package according to the preferred embodiment of the present invention has a structure in which the ceramic coating layer is directly formed on the lead frame without using an adhesive, thereby further improving the heat radiation characteristics and uses the coating method, thereby reducing the thickness of the power module package.
  • the ceramic coating layers 120 , 121 , and 123 are formed on a surface contacting only the first surfaces of the first and second lead frames 111 and 113 by way of example.
  • the ceramic coating layers 120 and 125 may also be formed on the first surface and a spaced area between the first and second lead frames 111 and 113 .
  • the ceramic coating layers 120 and 125 are also formed on the spaced area between the first and second lead frames 111 and 113 .
  • FIG. 2 is a diagram showing a structure of a power module package according to a second preferred embodiment of the present invention.
  • the power module package 100 may include first and second lead frames 110 , 111 , and 160 that are disposed to face each other, a ceramic coating layer 121 that is formed on a portion of a first surface of both or one of both of the first and second lead frames 110 , 111 , and 160 , and the semiconductor device 130 that is mounted on second surfaces of the first and second lead frames 110 , 111 , and 160 .
  • the ceramic coating layer 121 may be formed by the sol-gel method that uses the low-temperature firing.
  • the semiconductor device 130 may include the power device 131 and the control device 133 .
  • the first lead frame 111 is formed with the ceramic coating layer 121
  • the second surface of the first lead frame 111 is mounted with the power device 131
  • the second surface of the second lead frame 160 may be mounted with the control device 133 .
  • the ceramic coating layer 121 is formed on the lower surface of the power device 131 having a larger calorific value than that of the control device 133 , which may result in more efficiently emitting heat generated from the power device 131 .
  • the ceramic coating layer 121 is not formed on the lower portion of the control device 133 having a smaller calorific value than the power device 131 , which may result in simplifying the process of manufacturing the power module package and saving the manufacturing costs thereof.
  • FIG. 3 is a diagram showing a structure of a power module package according to a third preferred embodiment of the present invention.
  • the power module package 100 may include first and second lead frames 110 , 111 , and 113 that are disposed to face each other, ceramic coating layers 120 , 121 , and 123 that are formed on a portion of a first surface of both or one of both of the first and second lead frames 110 , 111 , and 113 , and the semiconductor device 130 that is mounted on second surfaces of the first and second lead frames.
  • the ceramic coating layer 121 may be formed by the sol-gel method that uses the low-temperature firing.
  • the power module package 100 may further include a thermal diffusion layer 170 made of a metal material formed on the lower surfaces of the ceramic coating layers 120 , 121 , and 123 over the first and second lead frames 110 , 111 , and 113 .
  • the structure in which the thermal diffusion layer 170 made of a metal material having high heat conductivity is directly bonded to the lower surfaces of the ceramic coating layers 120 , 121 , and 123 having high heat conductivity may improve heat radiation characteristics in a horizontal direction as well as a vertical direction that is a thickness direction of the power module package 100 by the thermal diffusion layer 170 .
  • FIGS. 4 to 8 are process flow charts for explaining a method for manufacturing a power module package according to the first preferred embodiment of the present invention, which will be described with reference to FIGS. 2 and 3 .
  • the first and second lead frames 110 , 111 , and 113 that are disposed to face each other is prepared.
  • the ceramic coating layers 120 , 121 , and 123 are formed on a portion of the first surface of both or one of both of the first and second lead frames 110 , 111 , and 113 .
  • the ceramic coating layers 120 , 121 , and 123 may be formed in an area that corresponds to the lower surface of the area mounted with the semiconductor the device 130 in the first surface that is the lower surface of the lead frame, that is, only in a portion other than an area bent at the time of forming a form.
  • the manufacturing costs of the power module package can be saved by forming the selective ceramic coating layer using less ceramic material that is expensive.
  • the ceramic coating layer is selectively formed only in a required area in the power module package and thus, a degree of freedom in design of the power module package may be improved.
  • the ceramic coating layer is thinly formed by a coating process rather than a plate shape and thus, the thickness and size of the power module package may be reduced.
  • the heat radiation characteristics may be further improved due to the structure in which the ceramic coating layer is directly formed on the lead frame without the adhesive.
  • the ceramic coating layers 120 , 121 , and 123 may be formed by the sol-gel method that uses the low-temperature firing.
  • the coating is performed by melting an inorganic body (aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN), boron nitride (BN), or the like) in a solvent, together with additives such as a binder component.
  • an inorganic body aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN), boron nitride (BN), or the like
  • AlN aluminum nitride
  • BN boron nitride
  • the ceramic coating layers are completed through the firing that uses a baking process at low temperature (200 to 300° C.) to remove the solvent component and the additives such as the binder component.
  • a shadow mask, a photo resist (PR), a dry film resist (DFR), a masking tape, or the like may be applied so as to selectively form the ceramic coating layers 120 , 121 , and 123 on the first and second lead frames 111 and 113 .
  • a spray method, a bar coating method, or a screen printing method, or the like may be applied.
  • the ceramic coating layers 120 , 121 , and 123 may be formed to have 10 ⁇ m to 1 mm, but the preferred embodiment of the present invention is not limited thereto.
  • the second surfaces of the first and second lead frames 110 , 111 , and 113 are mounted with the semiconductor device 130 .
  • the semiconductor device may include the power device 131 and the control device 133 .
  • the second surface of the first lead frame 111 may be mounted with the power device 131 and the second surface of the second lead frame 113 may be mounted with the control device 133 , at the time of mounting the semiconductor device.
  • the power device 131 that may generate high heat and the control device 133 that may generate relatively low heat are separately mounted on the first and second lead frames 111 and 113 , respectively, thereby minimizing an effect of heat generated from the power device 131 on the control device 133 .
  • the second surface of the first lead frame 111 may be, mounted with the power device 131 and the second surface of the second lead frame 113 may be mounted with the control device 133 , at the time of mounting the semiconductor device.
  • the ceramic coating layer 121 is formed on only the lower surface of the first lead frame 111 that is the mounting area of the power device 131 that may generate high heat, heat generated from the power device 131 may be efficiently emitted while simplifying the entire process, including the ceramic coating process and the manufacturing costs and the process may be reduced.
  • the wires 140 , 141 , and 143 that are electrically connect between the semiconductor devices 131 and 133 or between the semiconductor device 130 and the lead frame may be formed.
  • the wire 143 formed between the semiconductor device and the lead frame may be formed between the other lead frame rather than the first and second lead frames equipped with the semiconductor device and the semiconductor device.
  • the reason is that the short phenomenon may be generated when the first and second lead frames are electrically connected to the semiconductor device by the wire since the insulating layer is not formed on the second surfaces of the first and second lead frames 111 and 113 .
  • the form of the first and second lead frames 111 and 113 may be formed.
  • a form having the down-set structure may be formed on both or one of both of the first and second lead frames 111 and 113 .
  • the form of the first and second lead frames 111 and 113 may be formed after the molding forming process of FIG. 8 .
  • the molding 150 may be formed to cover the upper portions of the semiconductor device 130 , 131 , and 133 that are mounted between the first lead frame 111 and the second lead frame 113 , a portion of the lower portions of the first and second lead frames 111 and 113 , and the upper portions of the first and second lead frames 111 and 113 .
  • the molding 150 may be formed in a form that exposes the ceramic coating layers 120 , 121 , and 123 formed on the lower portions of the first and second lead frames 111 and 113 .
  • the thermal diffusion layer 170 made of a metal material may be formed on the lower surfaces of the ceramic coating layers 120 , 121 , and 123 over the first and second lead frames 110 , 111 , and 113 .
  • the lower surface of the thermal diffusion layer 170 is formed in the exposed form at the time of forming the molding 150 (see FIG. 3 ), thereby more efficiently emitting heat.
  • the power module package and the method for manufacturing the same according to the present invention can selectively form the ceramic coating layer on the lead frame to shorten the heat emitting path of the semiconductor devices that have a large calorific value and use the ceramic material having the high heat conductivity to improve the heat radiation characteristics.
  • the preferred embodiments of the present invention can use the ceramic coating layer to remove the separate heat radiation substrate, thereby simplifying the process of manufacturing the power module package and saving the manufacturing costs thereof, while reducing the thickness and size of the power module package.

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Abstract

Disclosed herein are a power module package and a method for manufacturing the same. The power module package includes first and second lead frames disposed to face each other; ceramic coating layers formed on a portion of a first surface of both or one of both of the first and second lead frames; and semiconductor devices mounted on second surfaces of the first and second lead frames.

Description

    CROSS REFERENCE TO RELATED APPLICATION
  • This application claims the benefit of Korean Patent Application No. 10-2011-0072105, filed on Jul. 20, 2011, entitled “Power Module Package and Method for Manufacturing the Same”, which is hereby incorporated by reference in its entirety into this application.
    • BACKGROUND OF THE INVENTION
  • 1. Technical Field
  • The present invention relates to a power module package and a method for manufacturing the same.
  • 2. Description of the Related Art
  • With the increase in energy consumption around the world, an efficient use of restricted energy has been attracting much attention. Therefore, a use of an inverter adopting an intelligent power module (IPM) for efficiently converting energy in the existing home and industrial appliances has accelerated.
  • With the increase in the use of the power module, a demand in a market for high-integration, high-capacity, and small-sized products has increased. As a result, a solution for a problem of heat generation from electronic parts has emerged as an important issue.
  • In particular, when using a high-capacity power device (for example, a high-capacity insulated gate bipolar transistor (IGBT), or the like), heat generated from a high heat generation power device affects a control device that is relatively vulnerable to heat, thereby degrading the entire performance of a module and long-term reliability.
  • As a result, a need exists for a high heat radiation package structure capable of solving the heat generation problem so as to increase efficiency of a power module and secure high reliability.
    • SUMMARY OF THE INVENTION
  • The present invention has been made in an effort to provide a power module package and a method for manufacturing the same capable of improving heat radiation characteristics by forming a ceramic coating layer in the power module package.
  • According to a preferred embodiment of the present invention, there is provided a power module package, including: first and second lead frames disposed to face each other; ceramic coating layers formed on a portion of a first surface of both or one of both of the first and second lead frames; and semiconductor devices mounted on second surfaces of the first and second lead frames.
  • The ceramic coating layer may be formed by a sol-gel method.
  • The semiconductor device may include a power device and a control device, and when the ceramic coating layers are formed on both of the first and second lead frames, the second surface of the first lead frame may be mounted with the power device and the second surface of the second lead frame may be mounted with the control device.
  • The semiconductor device may include a power device and a control device, and when the ceramic coating layer is formed on the first lead frame, the second surface of the first lead frame may be mounted with the power device and the second surface of the second lead frame may be mounted with the control device.
  • The power module package may further include a thermal diffusion layer made of a metal material formed on a lower surface of the ceramic coating layer over the first and second lead frames.
  • Both or one of both of the first and second lead frames may have a down-set structure.
  • The power module package may further include: a wire electrically connecting between the semiconductor devices or between the semiconductor device and the lead frame; and a molding formed on upper portions of the first and second lead frames, between the first lead frame and the second lead frame, and on a portion of lower portions of the first and second lead frames.
  • The molding may be formed in a form that exposes the ceramic coating layer formed on the lower portions of the first and second lead frames.
  • According to another preferred embodiment of the present invention, there is provided a method for manufacturing a power module package, including: preparing first and second lead frames disposed to face each other; forming ceramic coating layers on a portion of a first surface of both or one of both of the first and second lead frames; and mounting semiconductor devices on second surfaces of the first and second lead frames.
  • At the forming of the ceramic coating layer, the ceramic coating layer may be formed by a sol-gel method.
  • The semiconductor device may include a power device and a control device, and when the ceramic coating layers are formed on both of the first and second lead frames, at the mounting of the semiconductor device, the second surface of the first lead frame may be mounted with the power device and the second surface of the second lead frame may be mounted with the control device.
  • The semiconductor device may include a power device and a control device, and when the ceramic coating layer is formed on the first lead frame, at the mounting of the semiconductor device, the second surface of the first lead frame may be mounted with the power device and the second surface of the second lead frame may be mounted with the control device.
  • The method for manufacturing a power module package may further include: after the mounting of the semiconductor device, forming a wire electrically connecting between the semiconductor devices or between the semiconductor device and the lead frame; and forming a molding so as to cover the upper portion of the semiconductor device mounted between the first and second lead frames, on a portion of lower portions of the first and second lead frames, and upper portions of the first lead frame and the second lead frame.
  • The method for manufacturing a power module package may further include: prior to forming of the molding, forming a thermal diffusion layer made of a metal material on a lower surface of the ceramic coating layer over the first and second lead frames.
  • The method may further include: after the forming of the molding, forming forms of the first and second lead frames.
  • The method for manufacturing a power module package may further include: prior to the forming of the molding, forming a form having a down-set structure on both or one of both of the first and second lead frames.
  • At the forming of the molding, the molding may be formed in a form that exposes the ceramic coating layers formed on the lower portions of the first and second lead frames.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The patent or application file contains at least one drawing executed in color. Copies of this patent or patent application publication with color drawing(s) will be provided by the Office upon request and payment of the necessary fee.
  • FIG. 1 is a diagram showing a structure of a power module package according to a first preferred embodiment of the present invention.
  • FIG. 2 is a diagram showing a structure of a power module package according to a second preferred embodiment of the present invention.
  • FIG. 3 is a diagram showing a structure of a power module package according to a third preferred embodiment of the present invention.
  • FIGS. 4 to 8 are process flow charts for explaining a method for manufacturing a power module package according to the first preferred embodiment of the present invention.
  • FIG. 9 is a diagram for explaining thermal distribution of the power module package according to the preferred embodiment of the present invention.
  • FIG. 10 is a diagram showing a structure of a power module package according to a fourth preferred embodiment of the present invention.
    •  DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • Various objects, and advantages of the invention will become apparent from the following description of embodiments with reference to the accompanying drawings.
  • The terms and words used in the present specification and claims should not be interpreted as being limited to typical meanings or dictionary definitions, but should be interpreted as having meanings and concepts relevant to the technical scope of the present invention based on the rule according to which an inventor can appropriately define the concept of the term to describe most appropriately the best method he or she knows for carrying out the invention.
  • The above and other objects, features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. In the specification, in adding reference numerals to components throughout the drawings, it is to be noted that like reference numerals designate like components even though components are shown in different drawings. Further, when it is determined that the detailed description of the known art related to the present invention may obscure the gist of the present invention, the detailed description thereof will be omitted. Terms used in the specification, ‘first’, ‘second’, etc. can be used to describe various components, but the components are not to be construed as being limited to the terms.
  • Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
  • Power Module Package-First Preferred Embodiment
  • FIG. 1 is a diagram showing a structure of a power module package according to a first preferred embodiment of the present invention.
  • As shown in FIG. 1, a power module package 100 may include first and second lead frames 111 and 113 that are disposed to face each other, ceramic coating layers 120, 121, and 123 that are formed on a portion of a first surface of both or one of both of the first and second lead frames 111 and 113, and a semiconductor device 130 that is mounted on second surfaces of the first and second lead frames.
  • In this configuration, the ceramic coating layers 120, 121, and 123 may be selectively formed only in an area (a bottom of the semiconductor device of FIG. 1) that may generate high heat.
  • In addition, the ceramic coating layers 120, 121, and 123 may be formed by a sol-gel method that uses low-temperature firing.
  • In more detail, coating is performed by melting an inorganic body (aluminum oxide (Al2O3), aluminum nitride (AlN), boron nitride (BN), or the like) in a solvent, together with additives such as a binder component. After the coating is performed, the ceramic coating layers are completed by firing, which uses a baking process at low temperature (200 to 300° C.) to remove the solvent component and the additives such as the binder component.
  • In this case, a shadow mask, a photo resist (PR), a dry film resist (DFR), a masking tape, or the like, may be applied so as to selectively form the ceramic coating layers 120, 121, and 123 on the first and second lead frames 111 and 113. In addition, a spray method, a bar coating method, or a screen printing method, or the like, may be applied.
  • Meanwhile, the ceramic coating layers 120, 121, and 123 may be formed to have 10 μM to 1 mm, but the preferred embodiment of the present invention is not limited thereto.
  • In addition, since the ceramic coating layers 120, 121, and 123 according to the preferred embodiment of the present invention are directly formed on the first and second lead frames 111 and 113 without an adhesive, the heat transfer efficiency may be further improved.
  • Meanwhile, the semiconductor device 130 may include a power device 131 and a control device 133. For example, the power device 131 may be an insulated gate bipolar transistor (IGBT), a diode, or the like, that may generate high heat and the control device 133 may include a control integrated circuit (IC), or the like, that may generate lower heat that the power device.
  • As shown in FIG. 1, when the ceramic coating layers 120, 121, and 123 may be formed on both of the first and second lead frames 111 and 113, the power device 131 may be mounted on the second surface of the first lead frame 111 and the control device 133 may be mounted on the second surface of the second lead frame 113.
  • In addition, both or one of both of the first and second lead frames 111 and 113 may be a down-set structure in a bent form so as to form a step as shown in FIG. 1.
  • In addition, the power module package 100 may further include wires 140, 141, and 143 that electrically connect between the semiconductor devices 131 and 133 or between semiconductor devices 131 and 133 and the lead frames 110, 111, and 113.
  • In this configuration, the wire 143 formed between the semiconductor device and the lead frame may be formed between the other lead frame rather than the first and second lead frames equipped with the semiconductor device and the semiconductor device.
  • This is to previously prevent a short phenomenon generated when the first and second lead frames are electrically connected to the semiconductor device by the wire since the insulating layer is not formed on the second surfaces of the first and second lead frames 111 and 113.
  • In addition, the power module package 100 may further include a molding 150 that is formed on the upper portions of the first and second lead frames 111 and 113, between the first lead frame 111 and the second lead frame 113, and on a portion of the lower portions of the first and second lead frames 111 and 113.
  • In this configuration, the molding 150 may be formed in a structure in which the ceramic coating layers 120, 121, and 123 formed on the lower portions of the first and second lead frames 111 and 113 are exposed.
  • This is to prevent the degradation in the heat radiation characteristics due to the molding material having the lower heat conductivity than the ceramic material of the ceramic coating layer. Due to the structure, the heat radiation characteristics of the power module package according to the preferred embodiment of the present invention may be further improved.
  • FIG. 9 is a diagram thermal distribution of the power module package adopting the ceramic coating layer of the present invention and a general ceramic substrate.
  • In more detail, FIG. 9A is a diagram showing thermal distribution around a mounting area (A of FIG. 9A) of the semiconductor device of the power module package to which the ceramic coating layer having a thickness of 100 μm is applied and FIG. 9B is a diagram showing the thermal distribution around the mounting area (B of FIG. 9B) of the semiconductor device of the power module package to which the ceramic substrate having a thickness of 1000 μm is applied.
  • As shown in FIG. 9, as compared with area B (having a value of 8.305e+01, 7.821e+01 in FIG. 9) showing a state in which heat is concentrated since the thermal conductivity around the mounting area of the semiconductor device is not smooth, it can be confirmed that area A (having a value of 6.370e+01, 5.886e+01 in FIG. 9) shows a state in which heat around the mounting area of the semiconductor device is barely concentrated.
  • As described above, the ceramic coating layers 120, 121, and 123 according to the preferred embodiment of the present invention has higher heat conductivity than the power module package adopting the general ceramic substrate, thereby rapidly emitting heat from the semiconductor device 130 having a large calorific value to the outside.
  • Meanwhile, the general power module package cannot simultaneously manufacture the ceramic substrate and the lead frame using a high-temperature firing method, the ceramic substrate is manufactured and then, the ceramic substrate is bonded to the lead frame using an adhesive, such that the additional material or process may be required and the heat resistance may be increased.
  • However, the power module package according to the preferred embodiment of the present invention has a structure in which the ceramic coating layer is directly formed on the lead frame without using an adhesive, thereby further improving the heat radiation characteristics and uses the coating method, thereby reducing the thickness of the power module package.
  • As shown in FIG. 1, in the present embodiment, the ceramic coating layers 120, 121, and 123 are formed on a surface contacting only the first surfaces of the first and second lead frames 111 and 113 by way of example. However, as shown in FIG. 10, the ceramic coating layers 120 and 125 may also be formed on the first surface and a spaced area between the first and second lead frames 111 and 113.
  • In other words, as shown in FIG. 10, the ceramic coating layers 120 and 125 are also formed on the spaced area between the first and second lead frames 111 and 113.
  • Power Module Package-Second Preferred Embodiment
  • FIG. 2 is a diagram showing a structure of a power module package according to a second preferred embodiment of the present invention.
  • However, among components of the second preferred embodiment, a description of the same components as the components of the first preferred embodiment will be omitted, and only the components different therefrom will be described.
  • As shown in FIG. 2, the power module package 100 may include first and second lead frames 110, 111, and 160 that are disposed to face each other, a ceramic coating layer 121 that is formed on a portion of a first surface of both or one of both of the first and second lead frames 110, 111, and 160, and the semiconductor device 130 that is mounted on second surfaces of the first and second lead frames 110, 111, and 160.
  • In this configuration, the ceramic coating layer 121 may be formed by the sol-gel method that uses the low-temperature firing.
  • In addition, the semiconductor device 130 may include the power device 131 and the control device 133. When the first lead frame 111 is formed with the ceramic coating layer 121, the second surface of the first lead frame 111 is mounted with the power device 131 and the second surface of the second lead frame 160 may be mounted with the control device 133.
  • In this case, the ceramic coating layer 121 is formed on the lower surface of the power device 131 having a larger calorific value than that of the control device 133, which may result in more efficiently emitting heat generated from the power device 131.
  • In addition, the ceramic coating layer 121 is not formed on the lower portion of the control device 133 having a smaller calorific value than the power device 131, which may result in simplifying the process of manufacturing the power module package and saving the manufacturing costs thereof.
  • Power Module Package-Third Preferred Embodiment
  • FIG. 3 is a diagram showing a structure of a power module package according to a third preferred embodiment of the present invention.
  • However, among components of the third preferred embodiment, a description of the same components as the components of the first preferred embodiment will be omitted, and only the components different therefrom will be described.
  • As shown in FIG. 3, the power module package 100 may include first and second lead frames 110, 111, and 113 that are disposed to face each other, ceramic coating layers 120, 121, and 123 that are formed on a portion of a first surface of both or one of both of the first and second lead frames 110, 111, and 113, and the semiconductor device 130 that is mounted on second surfaces of the first and second lead frames.
  • In this configuration, the ceramic coating layer 121 may be formed by the sol-gel method that uses the low-temperature firing.
  • In addition, the power module package 100 may further include a thermal diffusion layer 170 made of a metal material formed on the lower surfaces of the ceramic coating layers 120, 121, and 123 over the first and second lead frames 110, 111, and 113.
  • As described above, the structure in which the thermal diffusion layer 170 made of a metal material having high heat conductivity is directly bonded to the lower surfaces of the ceramic coating layers 120, 121, and 123 having high heat conductivity may improve heat radiation characteristics in a horizontal direction as well as a vertical direction that is a thickness direction of the power module package 100 by the thermal diffusion layer 170.
  • Method for Manufacturing Power Module Package
  • FIGS. 4 to 8 are process flow charts for explaining a method for manufacturing a power module package according to the first preferred embodiment of the present invention, which will be described with reference to FIGS. 2 and 3.
  • First, as shown in FIG. 4, the first and second lead frames 110, 111, and 113 that are disposed to face each other is prepared.
  • Next, as shown in FIG. 5, the ceramic coating layers 120, 121, and 123 are formed on a portion of the first surface of both or one of both of the first and second lead frames 110, 111, and 113.
  • In this configuration, the ceramic coating layers 120, 121, and 123 may be formed in an area that corresponds to the lower surface of the area mounted with the semiconductor the device 130 in the first surface that is the lower surface of the lead frame, that is, only in a portion other than an area bent at the time of forming a form.
  • The manufacturing costs of the power module package can be saved by forming the selective ceramic coating layer using less ceramic material that is expensive.
  • In addition, the ceramic coating layer is selectively formed only in a required area in the power module package and thus, a degree of freedom in design of the power module package may be improved.
  • In addition, the ceramic coating layer is thinly formed by a coating process rather than a plate shape and thus, the thickness and size of the power module package may be reduced.
  • In addition, the heat radiation characteristics may be further improved due to the structure in which the ceramic coating layer is directly formed on the lead frame without the adhesive.
  • Meanwhile, the ceramic coating layers 120, 121, and 123 may be formed by the sol-gel method that uses the low-temperature firing.
  • In more detail, the coating is performed by melting an inorganic body (aluminum oxide (Al2O3), aluminum nitride (AlN), boron nitride (BN), or the like) in a solvent, together with additives such as a binder component. After the coating is performed, the ceramic coating layers are completed through the firing that uses a baking process at low temperature (200 to 300° C.) to remove the solvent component and the additives such as the binder component.
  • In this case, a shadow mask, a photo resist (PR), a dry film resist (DFR), a masking tape, or the like, may be applied so as to selectively form the ceramic coating layers 120, 121, and 123 on the first and second lead frames 111 and 113. In addition, a spray method, a bar coating method, or a screen printing method, or the like, may be applied.
  • Meanwhile, the ceramic coating layers 120, 121, and 123 may be formed to have 10 μm to 1 mm, but the preferred embodiment of the present invention is not limited thereto.
  • As shown in FIG. 6, the second surfaces of the first and second lead frames 110, 111, and 113 are mounted with the semiconductor device 130.
  • In this case, the semiconductor device may include the power device 131 and the control device 133.
  • As shown in FIG. 6, when the ceramic coating layers 120, 121, and 123 are formed on both of the first and second lead frames 111 and 113, the second surface of the first lead frame 111 may be mounted with the power device 131 and the second surface of the second lead frame 113 may be mounted with the control device 133, at the time of mounting the semiconductor device.
  • In this case, the power device 131 that may generate high heat and the control device 133 that may generate relatively low heat are separately mounted on the first and second lead frames 111 and 113, respectively, thereby minimizing an effect of heat generated from the power device 131 on the control device 133.
  • In addition, as shown in FIG. 2, when the ceramic coating layer 121 is formed on the first lead frame 111, the second surface of the first lead frame 111 may be, mounted with the power device 131 and the second surface of the second lead frame 113 may be mounted with the control device 133, at the time of mounting the semiconductor device.
  • In this configuration, since the ceramic coating layer 121 is formed on only the lower surface of the first lead frame 111 that is the mounting area of the power device 131 that may generate high heat, heat generated from the power device 131 may be efficiently emitted while simplifying the entire process, including the ceramic coating process and the manufacturing costs and the process may be reduced.
  • Next, the wires 140, 141, and 143 that are electrically connect between the semiconductor devices 131 and 133 or between the semiconductor device 130 and the lead frame may be formed.
  • In this configuration, the wire 143 formed between the semiconductor device and the lead frame may be formed between the other lead frame rather than the first and second lead frames equipped with the semiconductor device and the semiconductor device.
  • The reason is that the short phenomenon may be generated when the first and second lead frames are electrically connected to the semiconductor device by the wire since the insulating layer is not formed on the second surfaces of the first and second lead frames 111 and 113.
  • Next, as shown in FIG. 7, the form of the first and second lead frames 111 and 113 may be formed.
  • In this case, a form having the down-set structure may be formed on both or one of both of the first and second lead frames 111 and 113.
  • When the down-set structure is not applied to the first and second lead frames 111 and 113, the form of the first and second lead frames 111 and 113 may be formed after the molding forming process of FIG. 8.
  • Next, as shown in FIG. 8, the molding 150 may be formed to cover the upper portions of the semiconductor device 130, 131, and 133 that are mounted between the first lead frame 111 and the second lead frame 113, a portion of the lower portions of the first and second lead frames 111 and 113, and the upper portions of the first and second lead frames 111 and 113.
  • In this case, the molding 150 may be formed in a form that exposes the ceramic coating layers 120, 121, and 123 formed on the lower portions of the first and second lead frames 111 and 113.
  • Meanwhile, as shown in FIG. 3, prior to forming the molding, the thermal diffusion layer 170 made of a metal material may be formed on the lower surfaces of the ceramic coating layers 120, 121, and 123 over the first and second lead frames 110, 111, and 113.
  • When the thermal diffusion layer 170 is formed, the lower surface of the thermal diffusion layer 170 is formed in the exposed form at the time of forming the molding 150 (see FIG. 3), thereby more efficiently emitting heat.
  • As set forth above, the power module package and the method for manufacturing the same according to the present invention can selectively form the ceramic coating layer on the lead frame to shorten the heat emitting path of the semiconductor devices that have a large calorific value and use the ceramic material having the high heat conductivity to improve the heat radiation characteristics.
  • In addition, the preferred embodiments of the present invention can use the ceramic coating layer to remove the separate heat radiation substrate, thereby simplifying the process of manufacturing the power module package and saving the manufacturing costs thereof, while reducing the thickness and size of the power module package.
  • Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, they are for specifically explaining the present invention and thus a power module package and a method for manufacturing the same according to the present invention are not limited thereto, but those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.
  • Accordingly, such modifications, additions and substitutions should also be understood to fall within the scope of the present invention.

Claims (17)

1. A power module package, comprising:
first and second lead frames disposed to face each other;
ceramic coating layers formed on a portion of a first surface of both or one of both of the first and second lead frames; and
semiconductor devices mounted on second surfaces of the first and second lead fumes.
2. The power module package as set forth in claim 1, wherein the ceramic coating layer is formed by a sol-gel method.
3. The power module package as set forth in claim 1, wherein the semiconductor device includes a power device and a control device, and
when the ceramic coating layers are formed on both of the first and second lead frames, the second surface of the first lead frame is mounted with the power device and the second surface of the second lead frame is mounted with the control device.
4. The power module package as set forth in claim 1, wherein the semiconductor device includes a power device and a control device, and
when the ceramic coating layer is formed on the first lead frame, the second surface of the first lead frame is mounted with the power device and the second surface of the second lead frame is mounted with the control device.
5. The power module package as set forth in claim 1, further comprising a thermal diffusion layer made of a metal material formed on a lower surface of the ceramic coating layer over the first and second lead frames.
6. The power module package as set forth in claim 1, wherein both or one of both of the first and second lead frames has a down-set structure.
7. The power module package as set forth in claim 1, further comprising:
a wire electrically connecting between the semiconductor devices or between the semiconductor device and the lead frame; and
a molding formed on upper portions of the first and second lead frames, between the first lead frame and the second lead frame, and on a portion of lower portions of the first and second lead frames.
8. The power module package as set forth in claim 7, wherein the molding is formed in a form that exposes the ceramic coating layer formed on the lower portions of the first and second lead frames.
9. A method for manufacturing a power module package, comprising:
preparing first and second lead frames disposed to face each other;
forming ceramic coating layers on a portion of a first surface of both or one of both of the first and second lead frames; and
mounting semiconductor devices on second surfaces of the first and second lead frames.
10. The method as set forth in claim 9, wherein at the forming of the ceramic coating layer, the ceramic coating layer is formed by a sol-gel method.
11. The method as set forth in claim 9, wherein the semiconductor device includes a power device and a control device, and
when the ceramic coating layers are formed on both of the first and second lead frames, at the mounting of the semiconductor device, the second surface of the first lead frame is mounted with the power device and the second surface of the second lead frame is mounted with the control device.
12. The method as set forth in claim 9, wherein the semiconductor device includes a power device and a control device, and
when the ceramic coating layer is formed on the first lead frame, at the mounting of the semiconductor device, the second surface of the first lead frame is mounted with the power device and the second surface of the second lead frame is mounted with the control device.
13. The method as set forth in claim 9, further comprising:
after the mounting of the semiconductor device, forming a wire electrically connecting between the semiconductor devices or between the semiconductor device and the lead frame; and
forming a molding so as to cover an upper portion of the semiconductor device mounted between the first and second lead frames, on a portion of lower portions of the first and second lead frames, and on upper portions of the first lead frame and the second lead frame.
14. The method as set forth in claim 13, further comprising, prior to forming of the molding, forming a thermal diffusion layer made of a metal material on a lower surface of the ceramic coating layer over the first and second lead frames.
15. The method as set forth in claim 13, further comprising, after the forming of the molding, forming forms of the first and second lead frames.
16. The method as set forth in claim 13, further comprising, prior to the forming of the molding, forming a form having a down-set structure on both or one of both of the first and second lead frames.
17. The method as set forth in claim 13, wherein at the forming of the molding, the molding is formed in a form that exposes the ceramic coating layers formed on the lower portions of the first and second lead frames.
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