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US20120319198A1 - Semiconductor device and fabrication method thereof - Google Patents

Semiconductor device and fabrication method thereof Download PDF

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Publication number
US20120319198A1
US20120319198A1 US13/161,503 US201113161503A US2012319198A1 US 20120319198 A1 US20120319198 A1 US 20120319198A1 US 201113161503 A US201113161503 A US 201113161503A US 2012319198 A1 US2012319198 A1 US 2012319198A1
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Prior art keywords
metal layer
dielectric layer
layer
semiconductor device
shape profile
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US13/161,503
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Chin-Cheng Chien
Chun-Yuan Wu
Chih-Chien Liu
Chin-Fu Lin
Teng-Chun Tsai
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to US13/161,503 priority Critical patent/US20120319198A1/en
Assigned to UNITED MICROELECTRONICS CORP. reassignment UNITED MICROELECTRONICS CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHIEN, CHIN-CHENG, LIN, CHIN-FU, LIU, CHIH-CHIEN, TSAI, TENG-CHUN, WU, CHUN-YUAN
Publication of US20120319198A1 publication Critical patent/US20120319198A1/en
Priority to US14/949,896 priority patent/US10141193B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform
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    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/518—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their lengths or sectional shapes
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H—ELECTRICITY
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    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/671—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor having lateral variation in doping or structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 

Definitions

  • the present invention relates generally to a semiconductor device and fabrication method thereof, and more specifically, to a fabricating method of etching a high-k dielectric layer having a U-shape profile and the semiconductor device fabricated thereby.
  • Poly-silicon is conventionally used as a gate electrode in semiconductor devices, such as the metal-oxide-semiconductor (MOS).
  • MOS metal-oxide-semiconductor
  • the conventional poly-silicon gate has faced problems such as inferior performance due to boron penetration and unavoidable depletion effect, which increases equivalent thickness of the gate dielectric layer, reduces gate capacitance, and worsens a driving force of the devices. Therefore, work function metals that are suitable for use as the high-K gate dielectric layer are used to replace the conventional poly-silicon gate to be the control electrode.
  • CMOS complementary metal-oxide semiconductor
  • one of the dual work function metal gates is used in an NMOS device and the other one is alternatively used in a PMOS device.
  • CMOS complementary metal-oxide semiconductor
  • compatibility and process control for the dual metal gate are more complicated, meanwhile thickness and composition controls for materials used in the dual metal gate method are more precise.
  • the conventional dual metal gate methods are categorized into gate first processes and gate last processes. In a conventional dual metal gate method applied with the gate first process, the anneal process for forming the source/drain ultra-shallow junction, and the silicide process are performed after forming the metal gate.
  • Vfb flat band voltage
  • the structure formed by a gate-last process (more specifically to being formed by a gate-last for high-k last process) would have a high-k dielectric layer having a U-shape profile 110 , a work function metal layer having a U-shape profile 120 , and further comprises a plurality of barrier layers 130 formed between each layer as shown in FIG. 1 .
  • These multiple layers having a U-shape profile would lead to a protruding structure 150 at the top portion of the trench 140 , therefore reducing the opening of the trench 140 .
  • the sequential formed a filling metal layer (not shown), aluminum for example, will be difficult to be filled into the trench 140 . Otherwise, the fringe capacitance of the semiconductor device 100 increases because of the high-k dielectric layer having a U-shape profile 110 , therefore reducing the electrical performance of the semiconductor device.
  • the present invention provides a semiconductor device and fabrication method thereof to solve the said problems of the filling difficulty of the metal layer and the increasing fringe capacitance of the semiconductor device.
  • the present invention provides a semiconductor device including a substrate, an inter layer dielectric layer, a trench, and a high-k dielectric layer having a U-shape profile.
  • the inter layer dielectric layer is located on the substrate.
  • the trench is located in the inter layer dielectric layer.
  • the high-k dielectric layer having a U-shape profile is located in the trench, wherein the high-k dielectric layer having a U-shape profile exposes an upper portion of the sidewalls of the trench.
  • the present invention provides a fabricating method of the semiconductor device comprising the following.
  • An inter layer dielectric layer is formed on a substrate.
  • a trench is formed in the inter layer dielectric layer.
  • a high-k dielectric layer having a U-shape profile is formed in the trench.
  • the high-k dielectric layer is recessed to expose an upper portion of the sidewalls of the trench.
  • the present invention provides a fabricating method of the semiconductor device comprising the following.
  • An interface layer dielectric layer is formed on a substrate.
  • a trench is formed in the inter layer dielectric layer.
  • a high-k dielectric layer having a U-shape profile is formed in the trench.
  • a work function metal layer having a U-shape profile is formed on the high-k dielectric layer having a U-shape profile.
  • a filling material is filled into the trench. The filling material is etched back to expose the two ends of the work function metal layer and the two ends of the high-k dielectric layer. The two ends of the high-k dielectric layer are reduced to transform it to a metal layer. The two ends of the work function metal layer and the metal layer are removed. The filling material is removed.
  • the present invention provides a semiconductor device and fabrication method thereof, which reduces a portion of the two ends of the U-shaped cross-sectional profile of the high-k dielectric layer having a U-shape profile to transform it to a metal layer by using a filling material as a mask, after the high-k dielectric layer having a U-shape profile is formed. Then, removing the metal layer by itself, or removing the metal layer and a portion of the two ends of the U-shaped cross-sectional profile of the work function metal layer formed on the high-k dielectric layer having a U-shape profile in one step.
  • the filling difficulty about filling the sequential formed material layers, such as a barrier layer, a filling metal layer etc., into the trench would not happen because there are not too many material layers having a U-shape profile being deposited in the top portion of the gat recess.
  • the semiconductor device fabricated by the methods of the present invention has a lower fringe capacitance because the methods of the present invention remove at least a portion of the two ends of a U-shape profile of the high-k dielectric layer having a U-shape profile.
  • FIG. 1 schematically depicts a cross-sectional view of a conventional semiconductor device.
  • FIG. 2 schematically depicts a cross-sectional view of a semiconductor device according to one preferred embodiment of the present invention.
  • FIG. 3A schematically depicts a cross-sectional view of a fabricating method of the semiconductor device of FIG. 2 .
  • FIG. 3B schematically depicts a cross-sectional view of a fabricating method of the semiconductor device of FIG. 2 .
  • FIG. 3 B′ schematically depicts a cross-sectional view of a fabricating method of the semiconductor device of FIG. 2 .
  • FIG. 3C schematically depicts a cross-sectional view of a fabricating method of the semiconductor device of FIG. 2 .
  • FIG. 3D schematically depicts a cross-sectional view of a fabricating method of the semiconductor device of FIG. 2 .
  • FIG. 3 D′ schematically depicts a cross-sectional view of a fabricating method of the semiconductor device of FIG. 2 .
  • FIG. 3E schematically depicts a cross-sectional view of a fabricating method of the semiconductor device of FIG. 2 .
  • FIG. 3F schematically depicts a cross-sectional view of a fabricating method of the semiconductor device of FIG. 2 .
  • FIG. 4A schematically depicts across-sectional view of another fabricating method of the semiconductor device of FIG. 2 .
  • FIG. 4B schematically depicts across-sectional view of another fabricating method of the semiconductor device of FIG. 2 .
  • FIG. 4C schematically depicts across-sectional view of another fabricating method of the semiconductor device of FIG. 2 .
  • FIG. 2 schematically depicts a cross-sectional view of a semiconductor device according to one preferred embodiment of the present invention.
  • the semiconductor device 200 includes a substrate 210 , an inter layer dielectric layer 220 , a trench 240 and a high-k dielectric layer having a U-shape profile 230 .
  • An inter layer dielectric 220 is located on the substrate 210 .
  • the trench 240 is located in the inter layer dielectric layer 220 .
  • the high-k dielectric layer having a U-shape profile 230 is located within the trench 240 and exposes an upper portion 240 a of the sidewalls of the trench 240 .
  • the trench 240 may be formed by the method of the following.
  • a gate structure (not shown) is formed on the substrate 210 , wherein the gate structure includes a gate dielectric layer and a sacrificed gate located on the gate dielectric layer.
  • the forming method of the gate structure is known in the art and so is not described herein.
  • An inter layer dielectric 220 which may include a spacer 220 a is formed beside the gate structure.
  • An etching process is performed to remove the gate structure and form the trench 240 .
  • the substrate 210 may be a semiconductor substrate such as a silicon substrate, a silicon containing substrate and a silicon-on-insulator (SOI) substrate.
  • the spacer 220 a may be a single layer or a multilayer structure composed of silicon nitride or silicon oxide.
  • the high-k dielectric layer having a U-shape profile 230 may be a metal containing dielectric layer, such as hafnium oxide, zirconium oxide, but is not limited thereto.
  • the high-k dielectric layer having a U-shape cross-sectional U-shape profile 230 may be a group selected from hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO 4 ), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), tantalum oxide (Ta 2 O 5 ), yttrium oxide (Y 2 O 3 ), zirconium oxide (ZrO 2 ), strontium titanate oxide, (SrTiO 3 ), zirconium silicon oxide (ZrSiO 4 ), hafnium zirconium oxide (HfZrO 4 ), strontium bismuth tantalite (SrBi 2 Ta 2 O 9 , SBT), lead zirconate titanate (PbZr x Ti 1-x O 3 , PZT) or barium strontium titanate (Ba x Sr 1-x
  • the high-k dielectric layer having a U-shape profile 230 is a metal containing dielectric layer and the high-k dielectric layer having a U-shape profile 230 includes a metal layer 232 located on the two ends of the U-shaped cross-sectional profile of the high-k dielectric layer having a U-shape profile 230 , wherein the metal layer 232 is the reduction of the high-k dielectric layer having a U-shape profile 230 .
  • the high-k dielectric layer having a U-shape profile 230 is a chemical compound of the metal layer 232 .
  • the semiconductor device 200 further includes a gate metal layer 250 located on the high-k dielectric layer having a U-shape profile 230 , wherein the gate metal layer 250 includes a work function metal layer 252 and a filling metal layer 254 located on the work function metal layer 252 .
  • the work function metal layer 252 is also a U-shape profile structure located on the high-k dielectric layer having a U-shape profile 230 .
  • the two ends of the U-shaped cross-sectional profile of the work function metal layer 252 are trimmed with the two ends of the U-shaped cross-sectional profile of the high-k dielectric layer having a U-shape profile 230 , but it is not limited thereto.
  • the height of the two ends of the U-shaped cross-sectional profile of the work function metal layer 252 is not restricted by the height of high-k dielectric layer having a U-shape profile 230 .
  • the work function metal layer 252 may be a titanium aluminum (TiAl) layer, a titanium nitride metal layer, or other material layers, which depends on the characteristic of the semiconductor device 200 .
  • the work function metal layer 252 is a titanium aluminum (TiAl) metal layer while the semiconductor device 200 is a NMOS transistor; the work function metal layer 252 is a titanium nitride metal layer while the semiconductor device 200 is a PMOS transistor.
  • the filling metal layer 254 may be composed by metals such as aluminum, but it is not limited thereto.
  • an interface layer may be further included between the substrate 210 and the high-k dielectric layer having a U-shape profile 230 , for being a buffer layer of the substrate 210 and the high-k dielectric layer having a U-shape profile 230 .
  • the interface layer may be composed of silicon dioxide, but it is not limited thereto.
  • the semiconductor device 200 may further include a barrier layer (not shown) located on the high-k dielectric layer having a U-shape profile 230 .
  • a barrier layer (not shown) further comprised, is respectively formed between the high-k dielectric layer having a U-shape profile 230 and the work function metal layer 252 and between the work function metal layer 252 and the filling metal layer 254 , to avoid pollution between each material layer caused by diffusion.
  • the barrier layer may be a titanium nitride metal layer, a tantalum nitride metal layer or a multi-layer structure composed of a titanium nitride metal layer and a tantalum nitride metal layer, but it is not limited thereto.
  • a lightly doped source/drain region (not shown) or a source/drain region 260 may be automatically aligned and defined by using the spacer 220 a as a mask.
  • the high-k dielectric layer having a U-shape profile 230 and the work function metal layer 252 are U-shape profile structures. They expose the upper portion 240 a of the sidewalls of the trench 240 . Therefore, the semiconductor device 200 of the present invention has fewer material layers deposited on the top of the sidewalls of the trench 240 , hence avoiding the problem of the protruding structure of the prior art, which leads to the filling difficulty about filling the material layers, such as the filling metal layer, into the trench 240 .
  • the high-k dielectric layer having a U-shape profile 230 of the present invention exposes the upper portion 240 a of the sidewalls of the trench 240 . Thereby, the semiconductor device 200 of the present invention has a smaller fringe capacitance so as to improve the performance of the semiconductor device 200 .
  • FIG. 3A-3F schematically depict a cross-sectional view of a fabricating method of the semiconductor device of FIG. 2 .
  • a substrate 210 is provided.
  • An inter layer dielectric layer 220 which may include a spacer 220 a , is formed on the substrate 210 .
  • a trench 240 is formed in the inter layer dielectric layer 220 .
  • a high-k dielectric layer having a U-shape profile 230 is formed within the trench 240 .
  • a barrier layer (not shown) is selectively formed on the high-k dielectric layer having a U-shape profile 230 .
  • the barrier layer may include a titanium nitride metal layer, a tantalum nitride metal layer or a multi-layer structure composed of a titanium nitride metal layer and a tantalum nitride metal layer, to prevent the high-k dielectric layer having a U-shape profile 230 from being damaged in the following processes.
  • a filling material 270 such as a photoresist material, a bottom anti-reflection coating (BARC), organic dielectric layer (ODL) or a light absorbing Si-content polymer, (DUO), is filled into the trench 240 . Then, the filling material 270 is etched back to expose the two ends of the U-shaped cross-sectional profile 230 a of the high-k dielectric layer having a U-shape profile 230 , wherein the filling material 270 may be etched back by dry etching method, wet etching method etc.
  • BARC bottom anti-reflection coating
  • ODL organic dielectric layer
  • DAO light absorbing Si-content polymer
  • an etching process such as a dry etching process or a wet etching process, is directly performed to remove the exposed two ends of the U-shaped cross-sectional profile 230 a of the high-k dielectric layer having a U-shape profile 230 .
  • the exposed two ends of the U-shaped cross-sectional profile 230 a are reduced to transform as a metal layer 232 , wherein the reduction may include a hydrogen containing reducing process or a hydrogen plasma containing reducing process.
  • the reduction elements can not penetrate through the filling material 270 to reduce the bottom 230 b of the high-k dielectric layer having a U-shape profile.
  • the remaining filling material 270 is removed after a portion of the metal layer 232 is removed, thereby forming the high-k dielectric layer having a U-shape profile 230 exposing the upper portion 240 a of the sidewalls of the trench 240 .
  • a work function metal layer, a barrier layer, a filling metal layer etc. may be sequentially filled into the trench 240 to form a transistor structure (as shown in FIG. 3 D′).
  • the top of the sidewalls of the trench 240 does not contain the high-k dielectric layer having a U-shape profile 230 , thereby avoiding the filling difficulty of the work function metal layer, the barrier layer, the filling metal layer, etc.
  • the semiconductor device 200 of the present invention has a smaller fringe capacitance than the semiconductor device 100 of the prior art.
  • the sequentially filled work function metal layer (not shown) (also has a U-shape profile structure) is selectively etched back after the high-k dielectric layer having a U-shape profile 230 exposing the upper portion 240 of the sidewalls of the trench 240 is formed, to remove a portion of the two ends of the U-shape profile of the work function metal layer for exposing the upper portion 240 a of the sidewalls of the trench 240 again.
  • the two ends of the U-shaped cross-sectional profile of the work function metal layer 252 are trimmed with the two ends of the U-shaped cross-sectional profile 230 a .
  • FIG. 3E after finishing the step of FIG. 3C (reducing the exposed two ends of the U-shaped cross-sectional profile 230 a to transform to a metal layer 232 ), the steps of FIG. 3E-3F can be operated instead of FIG. 3D .
  • the filling material 270 is removed.
  • a work function metal layer 252 is deposited. As shown in FIG. 3E , after reducing the exposed two ends of the U-shaped cross-sectional profile 230 a to transform to a metal layer 232 , the filling material 270 is removed. Then, a work function metal layer 252 is deposited. As shown in FIG.
  • a filling material 270 ′ is filled and etched to expose the two ends of the U-shaped cross-sectional profile of the work function metal layer 252 , and then the exposed two ends of the U-shaped cross-sectional profile of the work function metal layer 252 and the metal layer 232 are sequentially removed by using the filling material 270 ′ as a mask. Finally, the remaining filling material 270 ′ is removed.
  • a barrier layer (not shown) is selectively formed to avoid the work function metal layer 252 from being damaged as the filling material 270 ′ is removed.
  • the spirit of the present invention is to transform the two ends of the U-shaped cross-sectional profile 230 a to a metal layer 232 by the filling material paired with the reduction process, and then removing at least a portion of the metal layer 232 to expose the upper portion 240 a of the sidewalls of the trench 240 . Therefore, all of methods for achieving the purpose can be seen as in the scope of the present invention. There is another fabricating method disclosed below.
  • FIG. 4A-4C schematically depict a cross-sectional view of another fabricating method of the semiconductor device of FIG. 2 .
  • a substrate 210 is provided, an inter layer dielectric layer 220 , which may include a spacer 220 a , is formed on the substrate 210 .
  • a trench 240 is formed in the inter layer dielectric layer 220 , wherein the fabricating methods of these are common with FIG. 3A and are known in the prior art and so are not described herein.
  • a high-k dielectric layer having a U-shape profile 230 is formed in the trench 240 .
  • a work function metal layer having a U-shape profile 252 is formed on the high-k dielectric layer having a U-shape profile 230 .
  • a barrier layer (not shown) is selectively formed between the high-k dielectric layer having a U-shape profile 230 and the work function metal layer having a U-shape profile 252 to prevent the two material layers from polluting each other.
  • a barrier layer (not shown) may be further formed on the work function metal layer having a U-shape profile 252 to prevent the work function metal layer having a U-shape profile 252 from being damaged in sequential processes.
  • an interface layer (not shown) may be included between the substrate 210 and the high-k dielectric layer having a U-shape profile 230 for being a buffer layer of the substrate 210 and the high-k dielectric layer having a U-shape profile 230 .
  • the filling material 270 is filled, and then the filling material 270 is etched back to expose the two ends of the U-shaped cross-sectional profile 252 a of the work function metal layer having a U-shape profile 252 and the two ends of the U-shaped cross-sectional profile 230 a of the high-k dielectric layer having a U-shape profile 230 located beneath it.
  • the U-shaped cross-sectional profile 230 a is reduced to transform it to a metal layer 232 , wherein the reduction process may include a hydrogen containing reduction process or a hydrogen plasma containing reduction process.
  • the U-shaped cross-sectional profile 230 a can be directly reduced without removing the work function metal layer 252 because the thickness of the work function metal layer having a U-shape profile 252 is thin enough, but the reduction process can not reduce the bottom 230 b of the high-k dielectric layer having a U-shape profile because the reduction elements can not penetrate the filling material 270 .
  • the fabricating methods of the semiconductor device depicted in FIG. 3A-3F and FIG. 4A-4C can include a gate-last process, more specifically to a gate-last for high-K last process.
  • the fabricating methods paired with gate last process are cases of the present invention, but it is not limited thereto.
  • the method of reducing and removing the sidewalls of the material layers by using the filling material in the present invention is also suited for other semiconductor processes.
  • the diagrams depicted in FIG. 3A-3F and FIG. 4A-4C are embodiments of forming a single MOS transistor, but the fabricating method of the semiconductor device of the present invention can be also used in forming CMOS transistors.
  • the fabricating method of the semiconductor device is applied to a CMOS transistor, except for respectively reducing the two ends of the U-shape profile of the high-k dielectric layer having a U-shape profile of a PMOS transistor and an NOMS transistor located on the two sides of the COMS transistor, and respectively removing the two ends of the U-shape profile of high-k dielectric layer having a U-shape profile and the work function metal layer, the two ends of a U-shape profile of high-k dielectric layer having a U-shape profile and the work function metal layer of the PMOS transistor and the NMOS transistor located on the two sides of the COMS transistor can also be reduced and removed at the same time.
  • the present invention provides a semiconductor device and fabrication method thereof, which includes: reducing the two ends of the U-shape profile of the high-k dielectric layer having a U-shape profile to transform it to a metal layer by using a photoresist filling material, a bottom anti-reflection coating (BARC) or a light absorbing oxide (DUO) as a mask after the high-k dielectric layer having a U-shape profile is formed or the work function metal layer is formed. Then, at least a portion of the metal layer is removed by itself, or at least a portion of the metal layer and a portion of the two ends of the U-shape profile of the work function metal layer are removed in the same step.
  • a photoresist filling material a bottom anti-reflection coating (BARC) or a light absorbing oxide (DUO)
  • BARC bottom anti-reflection coating
  • DAO light absorbing oxide
  • the filling difficulty of filling the sequential material layers such as the barrier layer, the filling metal layer etc. into the trench would not happen because there are not too many material layers having a U-shape profile being deposited on the top of the trench.
  • the semiconductor device fabricated by the methods of the present invention has a lower fringe capacitance because the methods of the present invention removes at least a portion of the two ends of a U-shape profile of the high-k dielectric layer having a U-shape profile.

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Abstract

A semiconductor device including a substrate, a spacer and a high-k dielectric layer having a U-shape profile is provided. The spacer located on the substrate surrounds and defines a trench. The high-k dielectric layer having a U-shape profile is located in the trench, and the high-k dielectric layer having a U-shape profile exposes an upper portion of the sidewalls of the trench.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates generally to a semiconductor device and fabrication method thereof, and more specifically, to a fabricating method of etching a high-k dielectric layer having a U-shape profile and the semiconductor device fabricated thereby.
  • 2. Description of the Prior Art
  • Poly-silicon is conventionally used as a gate electrode in semiconductor devices, such as the metal-oxide-semiconductor (MOS). However, with a trend toward scaling down the size of semiconductor devices, the conventional poly-silicon gate has faced problems such as inferior performance due to boron penetration and unavoidable depletion effect, which increases equivalent thickness of the gate dielectric layer, reduces gate capacitance, and worsens a driving force of the devices. Therefore, work function metals that are suitable for use as the high-K gate dielectric layer are used to replace the conventional poly-silicon gate to be the control electrode.
  • In a complementary metal-oxide semiconductor (CMOS) device, one of the dual work function metal gates is used in an NMOS device and the other one is alternatively used in a PMOS device. It is well known that compatibility and process control for the dual metal gate are more complicated, meanwhile thickness and composition controls for materials used in the dual metal gate method are more precise. The conventional dual metal gate methods are categorized into gate first processes and gate last processes. In a conventional dual metal gate method applied with the gate first process, the anneal process for forming the source/drain ultra-shallow junction, and the silicide process are performed after forming the metal gate. After performing the anneal process having such strict heat budget, it is found that a flat band voltage (Vfb) does not increase or decrease linearly with decreasing EOT of the high-K gate dielectric layer. Instead, a roll-off issue is observed. Therefore, the gate last process is developed to improve the Vfb roll-off issue and avoid generating leakage current due to re-crystallization of the high-K gate dielectric layer occurring in high-temperature processes, and to widen material choices for the high-K gate dielectric layer and the metal gate in the gate first process.
  • In the conventional gate last process, a sacrifice gate or a replacement gate is provided and followed by performing processes used to construct a normal MOS transistor. Then, the sacrifice/replacement gate is removed to form a trench. Consequently, the structure formed by a gate-last process (more specifically to being formed by a gate-last for high-k last process) would have a high-k dielectric layer having a U-shape profile 110, a work function metal layer having a U-shape profile 120, and further comprises a plurality of barrier layers 130 formed between each layer as shown in FIG. 1. These multiple layers having a U-shape profile would lead to a protruding structure 150 at the top portion of the trench 140, therefore reducing the opening of the trench 140. As the size of the semiconductor device shrinks, the sequential formed a filling metal layer (not shown), aluminum for example, will be difficult to be filled into the trench 140. Otherwise, the fringe capacitance of the semiconductor device 100 increases because of the high-k dielectric layer having a U-shape profile 110, therefore reducing the electrical performance of the semiconductor device.
    • SUMMARY OF THE INVENTION
  • The present invention provides a semiconductor device and fabrication method thereof to solve the said problems of the filling difficulty of the metal layer and the increasing fringe capacitance of the semiconductor device.
  • The present invention provides a semiconductor device including a substrate, an inter layer dielectric layer, a trench, and a high-k dielectric layer having a U-shape profile. The inter layer dielectric layer is located on the substrate. The trench is located in the inter layer dielectric layer. The high-k dielectric layer having a U-shape profile is located in the trench, wherein the high-k dielectric layer having a U-shape profile exposes an upper portion of the sidewalls of the trench.
  • The present invention provides a fabricating method of the semiconductor device comprising the following. An inter layer dielectric layer is formed on a substrate. A trench is formed in the inter layer dielectric layer. A high-k dielectric layer having a U-shape profile is formed in the trench. The high-k dielectric layer is recessed to expose an upper portion of the sidewalls of the trench.
  • The present invention provides a fabricating method of the semiconductor device comprising the following. An interface layer dielectric layer is formed on a substrate. A trench is formed in the inter layer dielectric layer. A high-k dielectric layer having a U-shape profile is formed in the trench. A work function metal layer having a U-shape profile is formed on the high-k dielectric layer having a U-shape profile. A filling material is filled into the trench. The filling material is etched back to expose the two ends of the work function metal layer and the two ends of the high-k dielectric layer. The two ends of the high-k dielectric layer are reduced to transform it to a metal layer. The two ends of the work function metal layer and the metal layer are removed. The filling material is removed.
  • According to the above, the present invention provides a semiconductor device and fabrication method thereof, which reduces a portion of the two ends of the U-shaped cross-sectional profile of the high-k dielectric layer having a U-shape profile to transform it to a metal layer by using a filling material as a mask, after the high-k dielectric layer having a U-shape profile is formed. Then, removing the metal layer by itself, or removing the metal layer and a portion of the two ends of the U-shaped cross-sectional profile of the work function metal layer formed on the high-k dielectric layer having a U-shape profile in one step. In this way, the filling difficulty about filling the sequential formed material layers, such as a barrier layer, a filling metal layer etc., into the trench would not happen because there are not too many material layers having a U-shape profile being deposited in the top portion of the gat recess. Besides, the semiconductor device fabricated by the methods of the present invention has a lower fringe capacitance because the methods of the present invention remove at least a portion of the two ends of a U-shape profile of the high-k dielectric layer having a U-shape profile.
  • These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 schematically depicts a cross-sectional view of a conventional semiconductor device.
  • FIG. 2 schematically depicts a cross-sectional view of a semiconductor device according to one preferred embodiment of the present invention.
  • FIG. 3A schematically depicts a cross-sectional view of a fabricating method of the semiconductor device of FIG. 2.
  • FIG. 3B schematically depicts a cross-sectional view of a fabricating method of the semiconductor device of FIG. 2.
  • FIG. 3B′ schematically depicts a cross-sectional view of a fabricating method of the semiconductor device of FIG. 2.
  • FIG. 3C schematically depicts a cross-sectional view of a fabricating method of the semiconductor device of FIG. 2.
  • FIG. 3D schematically depicts a cross-sectional view of a fabricating method of the semiconductor device of FIG. 2.
  • FIG. 3D′ schematically depicts a cross-sectional view of a fabricating method of the semiconductor device of FIG. 2.
  • FIG. 3E schematically depicts a cross-sectional view of a fabricating method of the semiconductor device of FIG. 2.
  • FIG. 3F schematically depicts a cross-sectional view of a fabricating method of the semiconductor device of FIG. 2.
  • FIG. 4A schematically depicts across-sectional view of another fabricating method of the semiconductor device of FIG. 2.
  • FIG. 4B schematically depicts across-sectional view of another fabricating method of the semiconductor device of FIG. 2.
  • FIG. 4C schematically depicts across-sectional view of another fabricating method of the semiconductor device of FIG. 2.
    •  DETAILED DESCRIPTION
  • FIG. 2 schematically depicts a cross-sectional view of a semiconductor device according to one preferred embodiment of the present invention. As shown in FIG. 2, the semiconductor device 200 includes a substrate 210, an inter layer dielectric layer 220, a trench 240 and a high-k dielectric layer having a U-shape profile 230. An inter layer dielectric 220 is located on the substrate 210. The trench 240 is located in the inter layer dielectric layer 220. The high-k dielectric layer having a U-shape profile 230 is located within the trench 240 and exposes an upper portion 240 a of the sidewalls of the trench 240. Moreover, the trench 240 may be formed by the method of the following. A gate structure (not shown) is formed on the substrate 210, wherein the gate structure includes a gate dielectric layer and a sacrificed gate located on the gate dielectric layer. The forming method of the gate structure is known in the art and so is not described herein. An inter layer dielectric 220, which may include a spacer 220 a is formed beside the gate structure. An etching process is performed to remove the gate structure and form the trench 240.
  • The substrate 210 may be a semiconductor substrate such as a silicon substrate, a silicon containing substrate and a silicon-on-insulator (SOI) substrate. The spacer 220 a may be a single layer or a multilayer structure composed of silicon nitride or silicon oxide. The high-k dielectric layer having a U-shape profile 230 may be a metal containing dielectric layer, such as hafnium oxide, zirconium oxide, but is not limited thereto. Furthermore, the high-k dielectric layer having a U-shape cross-sectional U-shape profile 230 may be a group selected from hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide, (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), strontium bismuth tantalite (SrBi2Ta2O9, SBT), lead zirconate titanate (PbZrxTi1-xO3, PZT) or barium strontium titanate (BaxSr1-xTiO3, BST).
  • In this embodiment, the high-k dielectric layer having a U-shape profile 230 is a metal containing dielectric layer and the high-k dielectric layer having a U-shape profile 230 includes a metal layer 232 located on the two ends of the U-shaped cross-sectional profile of the high-k dielectric layer having a U-shape profile 230, wherein the metal layer 232 is the reduction of the high-k dielectric layer having a U-shape profile 230. In other words, the high-k dielectric layer having a U-shape profile 230 is a chemical compound of the metal layer 232.
  • Furthermore, the semiconductor device 200 further includes a gate metal layer 250 located on the high-k dielectric layer having a U-shape profile 230, wherein the gate metal layer 250 includes a work function metal layer 252 and a filling metal layer 254 located on the work function metal layer 252. The work function metal layer 252 is also a U-shape profile structure located on the high-k dielectric layer having a U-shape profile 230. In a preferred embodiment, the two ends of the U-shaped cross-sectional profile of the work function metal layer 252 are trimmed with the two ends of the U-shaped cross-sectional profile of the high-k dielectric layer having a U-shape profile 230, but it is not limited thereto. In another embodiment, the height of the two ends of the U-shaped cross-sectional profile of the work function metal layer 252 is not restricted by the height of high-k dielectric layer having a U-shape profile 230. The work function metal layer 252 may be a titanium aluminum (TiAl) layer, a titanium nitride metal layer, or other material layers, which depends on the characteristic of the semiconductor device 200. For example, the work function metal layer 252 is a titanium aluminum (TiAl) metal layer while the semiconductor device 200 is a NMOS transistor; the work function metal layer 252 is a titanium nitride metal layer while the semiconductor device 200 is a PMOS transistor. The filling metal layer 254 may be composed by metals such as aluminum, but it is not limited thereto.
  • Otherwise, an interface layer (not shown) may be further included between the substrate 210 and the high-k dielectric layer having a U-shape profile 230, for being a buffer layer of the substrate 210 and the high-k dielectric layer having a U-shape profile 230. The interface layer may be composed of silicon dioxide, but it is not limited thereto. The semiconductor device 200 may further include a barrier layer (not shown) located on the high-k dielectric layer having a U-shape profile 230. For instance, a barrier layer (not shown) further comprised, is respectively formed between the high-k dielectric layer having a U-shape profile 230 and the work function metal layer 252 and between the work function metal layer 252 and the filling metal layer 254, to avoid pollution between each material layer caused by diffusion. In one case, the barrier layer (not shown) may be a titanium nitride metal layer, a tantalum nitride metal layer or a multi-layer structure composed of a titanium nitride metal layer and a tantalum nitride metal layer, but it is not limited thereto. Besides, a lightly doped source/drain region (not shown) or a source/drain region 260 may be automatically aligned and defined by using the spacer 220 a as a mask.
  • Above of all, the high-k dielectric layer having a U-shape profile 230 and the work function metal layer 252 are U-shape profile structures. They expose the upper portion 240 a of the sidewalls of the trench 240. Therefore, the semiconductor device 200 of the present invention has fewer material layers deposited on the top of the sidewalls of the trench 240, hence avoiding the problem of the protruding structure of the prior art, which leads to the filling difficulty about filling the material layers, such as the filling metal layer, into the trench 240. Besides, the high-k dielectric layer having a U-shape profile 230 of the present invention exposes the upper portion 240 a of the sidewalls of the trench 240. Thereby, the semiconductor device 200 of the present invention has a smaller fringe capacitance so as to improve the performance of the semiconductor device 200.
  • FIG. 3A-3F schematically depict a cross-sectional view of a fabricating method of the semiconductor device of FIG. 2. As shown in FIG. 3A, a substrate 210 is provided. An inter layer dielectric layer 220, which may include a spacer 220 a, is formed on the substrate 210. A trench 240 is formed in the inter layer dielectric layer 220. A high-k dielectric layer having a U-shape profile 230 is formed within the trench 240. A barrier layer (not shown) is selectively formed on the high-k dielectric layer having a U-shape profile 230. The barrier layer may include a titanium nitride metal layer, a tantalum nitride metal layer or a multi-layer structure composed of a titanium nitride metal layer and a tantalum nitride metal layer, to prevent the high-k dielectric layer having a U-shape profile 230 from being damaged in the following processes.
  • As shown in FIG. 3B, a filling material 270, such as a photoresist material, a bottom anti-reflection coating (BARC), organic dielectric layer (ODL) or a light absorbing Si-content polymer, (DUO), is filled into the trench 240. Then, the filling material 270 is etched back to expose the two ends of the U-shaped cross-sectional profile 230 a of the high-k dielectric layer having a U-shape profile 230, wherein the filling material 270 may be etched back by dry etching method, wet etching method etc.
  • As shown in FIG. 3B′, an etching process, such as a dry etching process or a wet etching process, is directly performed to remove the exposed two ends of the U-shaped cross-sectional profile 230 a of the high-k dielectric layer having a U-shape profile 230.
  • Or as shown in FIG. 3C, the exposed two ends of the U-shaped cross-sectional profile 230 a are reduced to transform as a metal layer 232, wherein the reduction may include a hydrogen containing reducing process or a hydrogen plasma containing reducing process. The reduction elements can not penetrate through the filling material 270 to reduce the bottom 230 b of the high-k dielectric layer having a U-shape profile.
  • As shown in FIG. 3D, the remaining filling material 270 is removed after a portion of the metal layer 232 is removed, thereby forming the high-k dielectric layer having a U-shape profile 230 exposing the upper portion 240 a of the sidewalls of the trench 240. In this time, there is still a portion of the metal layer 232 remaining. Then, a work function metal layer, a barrier layer, a filling metal layer etc. may be sequentially filled into the trench 240 to form a transistor structure (as shown in FIG. 3D′). In this way, the top of the sidewalls of the trench 240 does not contain the high-k dielectric layer having a U-shape profile 230, thereby avoiding the filling difficulty of the work function metal layer, the barrier layer, the filling metal layer, etc. Besides, the semiconductor device 200 of the present invention has a smaller fringe capacitance than the semiconductor device 100 of the prior art.
  • The sequentially filled work function metal layer (not shown) (also has a U-shape profile structure) is selectively etched back after the high-k dielectric layer having a U-shape profile 230 exposing the upper portion 240 of the sidewalls of the trench 240 is formed, to remove a portion of the two ends of the U-shape profile of the work function metal layer for exposing the upper portion 240 a of the sidewalls of the trench 240 again. In a preferred embodiment, the two ends of the U-shaped cross-sectional profile of the work function metal layer 252 are trimmed with the two ends of the U-shaped cross-sectional profile 230 a. As a result, the filling metal layer formed after the work function metal layer is more easily filled into the trench 240, thereby the size of the semiconductor device 200 can be shrank.
  • Otherwise, after finishing the step of FIG. 3C (reducing the exposed two ends of the U-shaped cross-sectional profile 230 a to transform to a metal layer 232), the steps of FIG. 3E-3F can be operated instead of FIG. 3D. As shown in FIG. 3E, after reducing the exposed two ends of the U-shaped cross-sectional profile 230 a to transform to a metal layer 232, the filling material 270 is removed. Then, a work function metal layer 252 is deposited. As shown in FIG. 3F, a filling material 270′ is filled and etched to expose the two ends of the U-shaped cross-sectional profile of the work function metal layer 252, and then the exposed two ends of the U-shaped cross-sectional profile of the work function metal layer 252 and the metal layer 232 are sequentially removed by using the filling material 270′ as a mask. Finally, the remaining filling material 270′ is removed. In a preferred embodiment, after the work function metal layer 252 is deposited, a barrier layer (not shown) is selectively formed to avoid the work function metal layer 252 from being damaged as the filling material 270′ is removed.
  • The spirit of the present invention is to transform the two ends of the U-shaped cross-sectional profile 230 a to a metal layer 232 by the filling material paired with the reduction process, and then removing at least a portion of the metal layer 232 to expose the upper portion 240 a of the sidewalls of the trench 240. Therefore, all of methods for achieving the purpose can be seen as in the scope of the present invention. There is another fabricating method disclosed below.
  • FIG. 4A-4C schematically depict a cross-sectional view of another fabricating method of the semiconductor device of FIG. 2. As shown in FIG. 4A, a substrate 210 is provided, an inter layer dielectric layer 220, which may include a spacer 220 a, is formed on the substrate 210. A trench 240 is formed in the inter layer dielectric layer 220, wherein the fabricating methods of these are common with FIG. 3A and are known in the prior art and so are not described herein. A high-k dielectric layer having a U-shape profile 230 is formed in the trench 240. A work function metal layer having a U-shape profile 252 is formed on the high-k dielectric layer having a U-shape profile 230. In a preferred embodiment, a barrier layer (not shown) is selectively formed between the high-k dielectric layer having a U-shape profile 230 and the work function metal layer having a U-shape profile 252 to prevent the two material layers from polluting each other. Furthermore, a barrier layer (not shown) may be further formed on the work function metal layer having a U-shape profile 252 to prevent the work function metal layer having a U-shape profile 252 from being damaged in sequential processes. Besides, an interface layer (not shown) may be included between the substrate 210 and the high-k dielectric layer having a U-shape profile 230 for being a buffer layer of the substrate 210 and the high-k dielectric layer having a U-shape profile 230.
  • As shown in FIG. 4B, the filling material 270 is filled, and then the filling material 270 is etched back to expose the two ends of the U-shaped cross-sectional profile 252 a of the work function metal layer having a U-shape profile 252 and the two ends of the U-shaped cross-sectional profile 230 a of the high-k dielectric layer having a U-shape profile 230 located beneath it. The U-shaped cross-sectional profile 230 a is reduced to transform it to a metal layer 232, wherein the reduction process may include a hydrogen containing reduction process or a hydrogen plasma containing reduction process. The U-shaped cross-sectional profile 230 a can be directly reduced without removing the work function metal layer 252 because the thickness of the work function metal layer having a U-shape profile 252 is thin enough, but the reduction process can not reduce the bottom 230 b of the high-k dielectric layer having a U-shape profile because the reduction elements can not penetrate the filling material 270.
  • AS shown in FIG. 4C, at least a portion of the two ends of the U-shaped cross-sectional profile 252 a and the metal layer 232 are removed. Then, the filling material 270 is removed. Moreover, a barrier layer (not shown) and a filling metal layer may be formed to fill the trench 240, thereby the semiconductor device 200 of FIG. 2 is finished.
  • Furthermore, the fabricating methods of the semiconductor device depicted in FIG. 3A-3F and FIG. 4A-4C can include a gate-last process, more specifically to a gate-last for high-K last process. However, the fabricating methods paired with gate last process are cases of the present invention, but it is not limited thereto. The method of reducing and removing the sidewalls of the material layers by using the filling material in the present invention is also suited for other semiconductor processes.
  • Otherwise, the diagrams depicted in FIG. 3A-3F and FIG. 4A-4C are embodiments of forming a single MOS transistor, but the fabricating method of the semiconductor device of the present invention can be also used in forming CMOS transistors. As the fabricating method of the semiconductor device is applied to a CMOS transistor, except for respectively reducing the two ends of the U-shape profile of the high-k dielectric layer having a U-shape profile of a PMOS transistor and an NOMS transistor located on the two sides of the COMS transistor, and respectively removing the two ends of the U-shape profile of high-k dielectric layer having a U-shape profile and the work function metal layer, the two ends of a U-shape profile of high-k dielectric layer having a U-shape profile and the work function metal layer of the PMOS transistor and the NMOS transistor located on the two sides of the COMS transistor can also be reduced and removed at the same time.
  • According to the above, the present invention provides a semiconductor device and fabrication method thereof, which includes: reducing the two ends of the U-shape profile of the high-k dielectric layer having a U-shape profile to transform it to a metal layer by using a photoresist filling material, a bottom anti-reflection coating (BARC) or a light absorbing oxide (DUO) as a mask after the high-k dielectric layer having a U-shape profile is formed or the work function metal layer is formed. Then, at least a portion of the metal layer is removed by itself, or at least a portion of the metal layer and a portion of the two ends of the U-shape profile of the work function metal layer are removed in the same step. In this way, the filling difficulty of filling the sequential material layers such as the barrier layer, the filling metal layer etc. into the trench would not happen because there are not too many material layers having a U-shape profile being deposited on the top of the trench. Besides, the semiconductor device fabricated by the methods of the present invention has a lower fringe capacitance because the methods of the present invention removes at least a portion of the two ends of a U-shape profile of the high-k dielectric layer having a U-shape profile.
  • Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.

Claims (20)

1. A semiconductor device, comprising:
a substrate;
an inter layer dielectric layer located on the substrate;
a trench located in the inter layer dielectric layer; and
a high-k dielectric layer having a U-shape profile located within the trench, wherein the high-k dielectric layer exposes an upper portion of the sidewalls of the trench.
2. The semiconductor device according to claim 1, wherein the high-k dielectric layer having a U-shape profile comprises a metal containing dielectric layer.
3. The semiconductor device according to claim 2, wherein the high-k dielectric layer having a U-shape profile comprises a metal layer located on the two ends of the U-shaped cross-sectional profile of the high-k dielectric layer having a U-shape profile.
4. The semiconductor device according to claim 3, wherein the metal containing dielectric layer is a chemical compound of the metal layer.
5. The semiconductor device according to claim 1, further comprising a work function metal layer located on the high-k dielectric layer having a U-shape profile.
6. The semiconductor device according to claim 5, wherein the two ends of the work function metal layer are trimmed with the two ends of the high-k dielectric layer having a U-shape profile.
7. A fabricating method of a semiconductor device, comprising:
forming a inter layer dielectric layer on a substrate;
forming a trench in the inter layer dielectric layer;
forming a high-k dielectric layer having a U-shape profile in the trench; and
recessing the high-k dielectric layer to expose an upper portion of the sidewalls of the trench.
8. The fabricating method of the semiconductor device according to claim 7, wherein recessing the high-k dielectric layer, further comprising:
filling a filling material in the trench; and
etching back the filling material to expose the two ends of the U-shape profile of the high-k dielectric layer.
9. The fabricating method of the semiconductor device according to claim 8, after etching back the filling material, further comprising:
transferring the two ends of the U-shape profile to transform it to a metal layer, wherein the transferring step is a reduction.
10. The fabricating method of the semiconductor device according to claim 9, after transferring the two ends of the U-shape profile to transform it to the metal layer, further comprising:
removing at least a portion of the metal layer.
11. The fabricating method of the semiconductor device according to claim 7, after forming a high-k dielectric layer having a U-shape profile in the trench, further comprising:
forming a barrier layer on the high-k dielectric layer.
12. The fabricating method of the semiconductor device according to claim 8, wherein the filling material comprises a photoresist material, a bottom anti-reflection coating (BARC) or a light absorbing Si-content polymer (DUO).
13. The fabricating method of the semiconductor device according to claim 9,
after transferring the two ends of the U-shape profile to transform it to the metal layer, further comprising:
removing a portion of the metal layer; and
removing the filling material.
14. The fabricating method of the semiconductor device according to claim 13, after removing the filling material, further comprising:
forming a work function metal layer on the high-k dielectric layer having a U-shape profile.
15. The fabricating method of the semiconductor device according to claim 13, after transferring the two ends of the U-shape profile to transform it to the metal layer, further comprising:
forming a work function metal layer on the high-k dielectric layer having a U-shape profile; and
removing a portion of the work function metal layer to expose the metal layer.
16. The fabricating method of the semiconductor device according to claim 15, wherein removing a portion of the work function metal layer to expose the metal layer and removing the metal layer are finished in the same removing process.
17. A fabricating method of the semiconductor device, comprising:
forming a inter layer dielectric layer on a substrate;
forming a trench in the inter layer dielectric layer;
forming a high-k dielectric layer having a U-shape profile in the trench;
forming a work function metal layer having a U-shape profile on the high-k dielectric layer having a U-shape profile;
filling a filling material into the trench;
etching back the filling material to expose the two ends of the work function metal layer and the two ends of the high-k dielectric layer;
reducing the two ends of the high-k dielectric layer to transform it to a metal layer;
removing the two ends of the work function metal layer and the metal layer; and
removing the filling material.
18. The fabricating method of the semiconductor device according to claim 17, wherein the work function metal layer having a U-shaped cross-sectional profile comprises a titanium nitride metal layer.
19. The fabricating method of the semiconductor device according to claim 17, wherein the work function metal layer having a U-shaped cross-sectional profile comprises an titanium aluminum (TiAl) metal layer and a titanium nitride metal layer.
20. The fabricating method of the semiconductor device according to claim 17, after removing the filling material, further comprising:
forming a filling metal layer on the work function metal layer having a U-shaped cross-sectional profile.
US13/161,503 2011-06-16 2011-06-16 Semiconductor device and fabrication method thereof Abandoned US20120319198A1 (en)

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Application Number Priority Date Filing Date Title
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