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US20120187453A1 - Insulating layers on different semiconductor materials - Google Patents

Insulating layers on different semiconductor materials Download PDF

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Publication number
US20120187453A1
US20120187453A1 US13/431,537 US201213431537A US2012187453A1 US 20120187453 A1 US20120187453 A1 US 20120187453A1 US 201213431537 A US201213431537 A US 201213431537A US 2012187453 A1 US2012187453 A1 US 2012187453A1
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silicon
layer
gate stack
silicon germanium
germanium layer
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US13/431,537
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Joseph F. Shepard, Jr.
Siddarth A. Krishnan
Rishikesh Krishnan
Michael P. Chudzik
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International Business Machines Corp
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International Business Machines Corp
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02323—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen
    • H01L21/02326—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen into a nitride layer, e.g. changing SiN to SiON
    • H—ELECTRICITY
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    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28211—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer
    • H—ELECTRICITY
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28255—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor belonging to Group IV and not being elemental silicon, e.g. Ge, SiGe, SiGeC
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0181—Manufacturing their gate insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0278—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline channels on wafers after forming insulating device isolations

Definitions

  • the present invention relates to methods of creating insulating layers for semiconductor device structures, and particularly for field effect transistor structures formed on a same substrate.
  • the present invention relates also to semiconductor structures created during the methods.
  • High performance logic device structures often include embedded SiGe channels in the pFETs while the nFETs are constructed on conventional single crystal substrates.
  • To construct multiple gate oxides (so called double gate architectures) on embedded SiGe channels and on Si channels requires that the gate insulators/dielectrics be deposited, for example, by means of chemical vapor deposition (CVD).
  • CVD techniques are used in order to construct devices with comparable physical thicknesses. If the double gate oxides are constructed by means of thermal oxidation (in a manner consistent with non-SiGe channel technologies), then the differing oxidation rates of the SiGe and Si will result in devices with different characteristics (Tiny, Vt, Ion/Ioff etc.). These different characteristics are often problematic.
  • HTOs high temperature oxides
  • SiH4 or Si2H6 with N2O, O2 or H2O at reduced pressures such as 200 Torr and temperatures between 600° C. and 800° C.
  • HTO layers are of lower quality when compared to SiO 2 films (layers) produced by means of thermal oxidation of single crystal substrates.
  • the lower film quality is manifested in higher trap densities (in the bulk of the film and the interface) which often leads to reduced reliability metrics, e.g. Vbd, TDDB, NBTI, etc.
  • This reduced reliability therefore, generally precludes the use of HTOs in high performance CMOS transistor applications.
  • the present invention is directed to processes for (methods of) creating high quality SiO 2 films and interfaces in high performance CMOS technologies which use SiGe (or some other semiconducting material such as SiC, GaAs, etc.) which results in differing oxidation rates on the n-FET region and p-FET region and, thereby, precludes the use of conventional thermal oxidation to create the FET devices.
  • SiGe or some other semiconducting material such as SiC, GaAs, etc.
  • inventive processes described through embodiments herein are based on the deposition of a thin layer of a sacrificial material, e.g., Si3N4.
  • the thin layer is deposited in a continuous film ranging from a single monolayer to any desired thickness.
  • the continuous film of the sacrificial material preferably is conformal with the underlying materials.
  • the sacrificial material is then oxidized to a thickness which consumes (preferably, completely) the sacrificial film but does not oxidize more than ten (10) angstroms into the underlying SiGe material.
  • the composition of the finished (oxidized in this case) material is not dictated by the transport of, the ratio of, or the purity of process gasses, but rather by: 1) the availability of Si in the starting material, and 2) the presence of a suitable oxidant.
  • films and interfaces created according to embodiments of the present invention will be of a higher quality than CVD deposited oxides (e.g., HTOs) and may be employed in integration arrangements requiring multiple gate oxides disposed on channels constructed of dissimilar materials.
  • CVD deposited oxides e.g., HTOs
  • a method of creating insulating layers on different semiconductor materials includes: providing a substrate having disposed thereon a first material and a second material, the second material having a chemical composition different from the first material; non-epitaxially depositing a continuous sacrificial layer of approximately constant thickness onto the first material and the second material; and then converting the sacrificial layer into a layer consisting essentially of SiO 2 without oxidizing more than ten (10) angstroms into the second material. More preferably, the sacrificial layer is converted entirely into SiO 2 without oxidizing any of the second material.
  • FIG. 1 is a cross-sectional block diagram showing step one of a preferred embodiment of the present invention.
  • FIG. 2 is a cross-sectional block diagram showing step two of the preferred embodiment.
  • FIG. 3 is a cross-sectional block diagram showing step three of the preferred embodiment.
  • FIG. 4 is a cross-sectional block diagram showing step four of the preferred embodiment.
  • FIG. 5 is a cross-sectional block diagram showing final gate structures after performing additional steps according to an additional preferred embodiment of the invention.
  • FIG. 6 is a cross-sectional block diagram showing a completed nFET and a completed pFET after performing additional steps (spacer formation, source and drain implants, silicide formation) on the embodiment shown in FIG. 5 .
  • FIG. 7 is a diagram showing characterization of the conversion of MLD Si3N4 to Si02 via radical oxygen.
  • FIGS. 1-4 , and FIG. 7 there is shown a preferred embodiment of the steps according to the present invention.
  • FIG. 1 shows a starting condition or step for the preferred embodiment.
  • a semiconductor (e.g., bulk silicon) substrate 10 having a first region such as a P-FET region 11 and a second region such as an N-FET region 12 .
  • a silicon germanium channel region 13 is formed at the P-FET region and a silicon channel region 14 is formed at the N-FET region.
  • the regions 13 , 14 are formed by conventional CMOS manufacturing process techniques. For example, region 14 is created by dry etching the starting substrate 10 to form the N-FET region.
  • Region 13 is created via an epitaxial growth of a silicon germanium film with a desired Ge concentration (typically 20%). Of course, other suitable Ge concentrations may be used.
  • the chemical composition of the region 14 includes or preferably consists essentially of Si, while the chemical composition of the region 13 includes or preferably consists essentially of SiGe.
  • FIG. 2 a continuous, sacrificial film 15 is deposited on both the Si and the SiGe channel regions 14 , 13 after conventional shallow trench isolation (STI) formation.
  • FIG. 2 shows the deposition of a thin molecular layer deposited (MLD) silicon nitride film having approximately ( ⁇ 10%) equal and constant thicknesses on both the nFET and pFET channel regions 14 , 13 .
  • the film 15 is conformal with the regions 14 , 13 .
  • Typical thicknesses of the film 15 range from about 10 angstroms to about 50 angstroms.
  • the MLD silicon nitride film 15 is “sacrificial” in the sense that the film 15 will be converted into a high quality SiO 2 having excellent reliability and interfacial qualities.
  • This Si3N4 film 15 is deposited, for example, using the following tool model “iRAD” commercially available from Tokyo Electron Limited (TEL).
  • the embodiment disclosed herein uses MLD Si3N4 but can be performed well with other sacrificial materials which can be deposited sufficiently thin and continuous, and which can be converted to SiO 2 via known thermal or plasma techniques.
  • sacrificial materials include, for example, amorphous silicon, polycrystalline silicon, or silicon carbide.
  • Such other sacrificial materials can be deposited using tools such as tool model “SinGen” commercially available from Applied Materials, Inc. (AMAT).
  • the thermal or plasma techniques can be performed using tools such as tool model “Radiance” or “DPN” commercially available from Applied Materials, Inc. (AMAT).
  • FIG. 3 shows the beginning of the conversion of the sacrificial film 15 from Si3N4 into a SiO 2 layer 16 .
  • the sacrificial material 15 is oxidized in an appropriate environment. Dry oxidation, wet oxidation, or radical oxidation ( FIG. 7 ) may be used to consume the sacrificial material 15 .
  • Oxidation/conversion in this embodiment is by means of radical oxidation (and can be accomplished using conventional plasma based tooling or in other conventional rapid thermal tooling which generates O* in sufficient quantities). The conversion takes place in a top down fashion with [O] replacing [N] in the dielectric film 15 .
  • Radical Oxidation can be realized in the appropriate tool according to the characterization diagram shown in FIG. 7 . Realizing Radical Oxidation according to the present invention would be well understood by those skilled in the art in view of the present specification and drawing figures.
  • FIG. 4 there is shown a cross section of the final gate oxide layer 17 .
  • the sacrificial material can be essentially or even completely converted to SiO 2 .
  • the thickness T of the oxide layer 17 is approximately 2 . 4 times the thickness of the sacrificial layer 15 , in the preferred embodiment.
  • oxidizing occurs no more than ten (10) angstroms into the SiGe channel material 13 (i.e. in the direction of the Thickness T) and into the Si channel material 14 . Even more preferably, none of the SiGe channel material is oxidized.
  • FIG. 4 shows the completed SiO 2 gate dielectric.
  • the final dielectric layer 17 is of a much higher quality relative to the HTO materials.
  • Advantages of SiO 2 films generated in this manner are 1) better reliability, 2) higher quality SiO 2 /channel interfaces (lower Dit levels), and 3) a reduction in the total number of process steps needed to construct the gate dielectric (e.g. elimination of the DPN/PNA post treatment).
  • DPN is Decoupled Plasma Nitridation.
  • PNA Post Nitridation Anneal.
  • DPN and PNA steps are well known in the semiconductor manufacturing process art.
  • FIG. 5 final gate stack structures each showing the converted SiO 2 dielectric capped with high-k/metal gate stack and polysilicon are illustrated.
  • the illustration is just after conventional “post gate etch,” i.e. PC etch, and before conventional spacer, source/drain, and silicide formation.
  • the gate materials HFO 2 or HfSiOX, LaZ03, TiN, Polysilicon
  • the gate materials HfOZ or HfSiOX, TiN, Polysilicon for the P-FET are deposited using conventional deposition techniques.
  • FIG. 6 shows a completed nFET and a completed pFET according to a further preferred embodiment of the invention with the gate stacks known in FIG. 5 , and conventional spacers, source/drain regions and silicide caps.
  • FIG. 7 shows low energy e-beam microprobe data used to characterize the [N] and [O] content of a sacrificial MLD film as a function of radical oxidation time.
  • the data was used to illustrate the excellent process control of the conversion process and to develop a simple empirical model which can be used by those skilled in the art to design deposited SiO 2 gate dielectrics with different final thicknesses.
  • Example Tools and Parameters for the preferred embodiment of the present invention in a 32 nm Technology Mode include, for example:
  • MLD Si3N4 deposition is performed at 500 C.
  • Silicon Nitride films are deposited by exposing wafers to alternating flows of dichlorosilane (DCS) and ammonia plus RF power. Typical conditions are 1 slm of DCS and 5 slm of NH3 with 100 W of RF power.
  • the thickness of the layer 15 is determined by controlling, e.g., the number of cycles (i.e. number of thin films deposited).
  • Applied Materials, Inc. tool trade name “ISSG”) is performed at 900 C, at pressure of 7 T, and with a H2 concentration of 5% (500 sccm H2 in 9.5 slm 02).
  • the thickness T of the layer 17 is determined by controlling temperature, H2 concentration and/or process time. All these controls would be well understood by those skilled in the art, in view of the present specification and drawing figures.

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Abstract

A semiconductor structure is provided that includes a substrate having disposed thereon a silicon layer and a silicon germanium layer. An insulator is disposed between the silicon layer and the silicon germanium layer. An optional silicon nitride film is disposed conformally on the silicon layer and the silicon germanium layer, and a SiO2layer disposed on the optional silicon nitride film or on the silicon layer and the silicon germanium layer, when the optional silicon nitride film is not present.

Description

    RELATED APPLICATIONS
  • This application is a divisional of U.S. Ser. No. 12/685,332, filed Jan. 11, 2010, the entire contents of which are incorporated herein by reference.
    • FIELD OF THE INVENTION
  • The present invention relates to methods of creating insulating layers for semiconductor device structures, and particularly for field effect transistor structures formed on a same substrate. The present invention relates also to semiconductor structures created during the methods.
    • BACKGROUND OF THE INVENTION
  • High performance logic device structures often include embedded SiGe channels in the pFETs while the nFETs are constructed on conventional single crystal substrates. To construct multiple gate oxides (so called double gate architectures) on embedded SiGe channels and on Si channels requires that the gate insulators/dielectrics be deposited, for example, by means of chemical vapor deposition (CVD). CVD techniques are used in order to construct devices with comparable physical thicknesses. If the double gate oxides are constructed by means of thermal oxidation (in a manner consistent with non-SiGe channel technologies), then the differing oxidation rates of the SiGe and Si will result in devices with different characteristics (Tiny, Vt, Ion/Ioff etc.). These different characteristics are often problematic.
  • In most cases, the CVD oxides deposited on SiGe channels are so called “high temperature oxides” or HTOs. HTOs can be deposited in either single wafer or batch furnace type tools. HTOs are typically produced through a reaction of SiH4 or Si2H6 with N2O, O2 or H2O at reduced pressures such as 200 Torr and temperatures between 600° C. and 800° C.
  • It is often reported that HTO layers are of lower quality when compared to SiO2 films (layers) produced by means of thermal oxidation of single crystal substrates. The lower film quality is manifested in higher trap densities (in the bulk of the film and the interface) which often leads to reduced reliability metrics, e.g. Vbd, TDDB, NBTI, etc. This reduced reliability, therefore, generally precludes the use of HTOs in high performance CMOS transistor applications.
    • SUMMARY OF THE INVENTION
  • The present invention is directed to processes for (methods of) creating high quality SiO2 films and interfaces in high performance CMOS technologies which use SiGe (or some other semiconducting material such as SiC, GaAs, etc.) which results in differing oxidation rates on the n-FET region and p-FET region and, thereby, precludes the use of conventional thermal oxidation to create the FET devices.
  • The inventive processes described through embodiments herein are based on the deposition of a thin layer of a sacrificial material, e.g., Si3N4. The thin layer is deposited in a continuous film ranging from a single monolayer to any desired thickness. In the embodiments, the continuous film of the sacrificial material preferably is conformal with the underlying materials. The sacrificial material is then oxidized to a thickness which consumes (preferably, completely) the sacrificial film but does not oxidize more than ten (10) angstroms into the underlying SiGe material. Because the gate dielectric is created by means of the thermal oxidation of the sacrificial material, the composition of the finished (oxidized in this case) material is not dictated by the transport of, the ratio of, or the purity of process gasses, but rather by: 1) the availability of Si in the starting material, and 2) the presence of a suitable oxidant.
  • The inventors believe films and interfaces created according to embodiments of the present invention will be of a higher quality than CVD deposited oxides (e.g., HTOs) and may be employed in integration arrangements requiring multiple gate oxides disposed on channels constructed of dissimilar materials.
  • According to a preferred embodiment of the present invention, a method of creating insulating layers on different semiconductor materials includes: providing a substrate having disposed thereon a first material and a second material, the second material having a chemical composition different from the first material; non-epitaxially depositing a continuous sacrificial layer of approximately constant thickness onto the first material and the second material; and then converting the sacrificial layer into a layer consisting essentially of SiO2 without oxidizing more than ten (10) angstroms into the second material. More preferably, the sacrificial layer is converted entirely into SiO2 without oxidizing any of the second material.
  • It is a principal object of the present invention to provide a method of creating oxides having at least approximately (±10%) equal or equal thicknesses on different semiconductor materials.
  • It is a further object of the present invention to provide such a method that is highly compatible with conventional methods/processes for producing nFETs and pFETs on a same substrate.
  • Further and still other objects of the present invention will become more readily apparent when the following description is taken in conjunction with the drawing figures.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a cross-sectional block diagram showing step one of a preferred embodiment of the present invention.
  • FIG. 2 is a cross-sectional block diagram showing step two of the preferred embodiment.
  • FIG. 3 is a cross-sectional block diagram showing step three of the preferred embodiment.
  • FIG. 4 is a cross-sectional block diagram showing step four of the preferred embodiment.
  • FIG. 5 is a cross-sectional block diagram showing final gate structures after performing additional steps according to an additional preferred embodiment of the invention.
  • FIG. 6 is a cross-sectional block diagram showing a completed nFET and a completed pFET after performing additional steps (spacer formation, source and drain implants, silicide formation) on the embodiment shown in FIG. 5.
  • FIG. 7 is a diagram showing characterization of the conversion of MLD Si3N4 to Si02 via radical oxygen.
    •  DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS AND BEST MODE
  • Turning now to FIGS. 1-4, and FIG. 7, there is shown a preferred embodiment of the steps according to the present invention.
  • FIG. 1 shows a starting condition or step for the preferred embodiment. There is provided a semiconductor (e.g., bulk silicon) substrate 10 having a first region such as a P-FET region 11 and a second region such as an N-FET region 12. A silicon germanium channel region 13 is formed at the P-FET region and a silicon channel region 14 is formed at the N-FET region. The regions 13, 14 are formed by conventional CMOS manufacturing process techniques. For example, region 14 is created by dry etching the starting substrate 10 to form the N-FET region. Region 13 is created via an epitaxial growth of a silicon germanium film with a desired Ge concentration (typically 20%). Of course, other suitable Ge concentrations may be used.
  • In the preferred embodiment, the chemical composition of the region 14, for example, includes or preferably consists essentially of Si, while the chemical composition of the region 13 includes or preferably consists essentially of SiGe.
  • In FIG. 2, a continuous, sacrificial film 15 is deposited on both the Si and the SiGe channel regions 14, 13 after conventional shallow trench isolation (STI) formation. FIG. 2 shows the deposition of a thin molecular layer deposited (MLD) silicon nitride film having approximately (±10%) equal and constant thicknesses on both the nFET and pFET channel regions 14, 13. Preferably, the film 15 is conformal with the regions 14, 13. Typical thicknesses of the film 15 range from about 10 angstroms to about 50 angstroms. The MLD silicon nitride film 15 is “sacrificial” in the sense that the film 15 will be converted into a high quality SiO2 having excellent reliability and interfacial qualities. This Si3N4 film 15 is deposited, for example, using the following tool model “iRAD” commercially available from Tokyo Electron Limited (TEL).
  • The embodiment disclosed herein uses MLD Si3N4 but can be performed well with other sacrificial materials which can be deposited sufficiently thin and continuous, and which can be converted to SiO2 via known thermal or plasma techniques. Such sacrificial materials include, for example, amorphous silicon, polycrystalline silicon, or silicon carbide. Such other sacrificial materials can be deposited using tools such as tool model “SinGen” commercially available from Applied Materials, Inc. (AMAT). Also, the thermal or plasma techniques can be performed using tools such as tool model “Radiance” or “DPN” commercially available from Applied Materials, Inc. (AMAT). Those skilled in the art can readily effect the deposition, thermal and/or plasma techniques in view of the present specification and drawing figures.
  • FIG. 3 shows the beginning of the conversion of the sacrificial film 15 from Si3N4 into a SiO2 layer 16. In FIG. 3, the sacrificial material 15 is oxidized in an appropriate environment. Dry oxidation, wet oxidation, or radical oxidation (FIG. 7) may be used to consume the sacrificial material 15. Oxidation/conversion in this embodiment is by means of radical oxidation (and can be accomplished using conventional plasma based tooling or in other conventional rapid thermal tooling which generates O* in sufficient quantities). The conversion takes place in a top down fashion with [O] replacing [N] in the dielectric film 15. Radical Oxidation can be realized in the appropriate tool according to the characterization diagram shown in FIG. 7. Realizing Radical Oxidation according to the present invention would be well understood by those skilled in the art in view of the present specification and drawing figures.
  • In FIG. 4, there is shown a cross section of the final gate oxide layer 17. The sacrificial material can be essentially or even completely converted to SiO2. The thickness T of the oxide layer 17 is approximately 2.4 times the thickness of the sacrificial layer 15, in the preferred embodiment. During the converting step according to the preferred embodiment, oxidizing occurs no more than ten (10) angstroms into the SiGe channel material 13 (i.e. in the direction of the Thickness T) and into the Si channel material 14. Even more preferably, none of the SiGe channel material is oxidized. FIG. 4 shows the completed SiO2 gate dielectric. Because the SiO2 film is generated via the thermal oxidation of the pre-existing sacrificial film 15, the final dielectric layer 17 is of a much higher quality relative to the HTO materials. Advantages of SiO2 films generated in this manner (relative to conventional HTO+DPN+PNA) are 1) better reliability, 2) higher quality SiO2/channel interfaces (lower Dit levels), and 3) a reduction in the total number of process steps needed to construct the gate dielectric (e.g. elimination of the DPN/PNA post treatment).
  • DPN is Decoupled Plasma Nitridation.
  • PNA is Post Nitridation Anneal.
  • DPN and PNA steps are well known in the semiconductor manufacturing process art.
  • In FIG. 5, final gate stack structures each showing the converted SiO2 dielectric capped with high-k/metal gate stack and polysilicon are illustrated. The illustration is just after conventional “post gate etch,” i.e. PC etch, and before conventional spacer, source/drain, and silicide formation. The gate materials (HFO2 or HfSiOX, LaZ03, TiN, Polysilicon) for the N-FET and the gate materials (HfOZ or HfSiOX, TiN, Polysilicon for the P-FET) are deposited using conventional deposition techniques.
  • FIG. 6 shows a completed nFET and a completed pFET according to a further preferred embodiment of the invention with the gate stacks known in FIG. 5, and conventional spacers, source/drain regions and silicide caps.
  • For discussions of various conventional/known techniques for creating a nFET and a pFET on a same substrate, see for example:
      • U.S. Pat. No. 7,057,216B2 incorporated by reference in its entirety herein;
      • U.S. Pat. No. 5,547,894 incorporated by reference in its entirety herein;
      • Fundamentals of Semiconductor Processing Technologies, by Badih El-Korch (Kluwer Academic Publishers, 1997), and
      • VLSI Technology, by S. M. SZE (McGraw Hill, 1988, ISBN 0-07-062 735-5).
  • Finally, FIG. 7 (left plot) shows low energy e-beam microprobe data used to characterize the [N] and [O] content of a sacrificial MLD film as a function of radical oxidation time. The data was used to illustrate the excellent process control of the conversion process and to develop a simple empirical model which can be used by those skilled in the art to design deposited SiO2 gate dielectrics with different final thicknesses.
  • Example Tools and Parameters for the preferred embodiment of the present invention in a 32 nm Technology Mode include, for example:
  • MLD Si3N4 deposition is performed at 500 C. Silicon Nitride films are deposited by exposing wafers to alternating flows of dichlorosilane (DCS) and ammonia plus RF power. Typical conditions are 1 slm of DCS and 5 slm of NH3 with 100 W of RF power. The thickness of the layer 15 is determined by controlling, e.g., the number of cycles (i.e. number of thin films deposited).
  • Radical oxidation (Applied Materials, Inc. tool trade name “ISSG”) is performed at 900 C, at pressure of 7 T, and with a H2 concentration of 5% (500 sccm H2 in 9.5 slm 02). The thickness T of the layer 17 is determined by controlling temperature, H2 concentration and/or process time. All these controls would be well understood by those skilled in the art, in view of the present specification and drawing figures.
  • While the invention has been described in terms of embodiments, those skilled in the art will recognize that the invention can be practiced with modifications and in the spirit and scope of the appended claims. For example, the invention can be readily applicable to SOI or other substrates.

Claims (20)

1. A semiconductor structure, comprising:
a substrate having disposed thereon a silicon layer and a silicon germanium layer;
an insulator disposed between the silicon layer and the silicon germanium layer;
a silicon nitride film disposed conformally on the silicon layer and the silicon germanium layer; and
a SiO2 layer disposed on the silicon nitride film.
2. The structure as claimed in claim 1 wherein the silicon germanium layer has a Ge concentration of approximately 20%.
3. The structure of claim 1 wherein said insulator has an upper most surface that is coplanar within an uppermost surface of each of said silicon layer and said silicon germanium layer.
4. The structure of claim 1 wherein said insulator has one vertical sidewall in direct physical contact with a vertical sidewall of said silicon layer and another vertical sidewall in direct physical contact with a vertical sidewall of said silicon germanium layer.
5. The structure of claim 1 wherein said substrate comprises bulk silicon.
6. The structure of claim 1 wherein said silicon germanium layer is present at a p-FET region of the substrate, and the silicon layer is present at an n-FET region of said substrate.
7. The structure of claim 1 wherein said silicon germanium layer consists essentially of silicon and germanium, and said silicon layer consists essentially of silicon.
8. The structure of claim 1 wherein said SiO2layer has a thickness that is greater than a thickness of said silicon nitride film.
9. The structure of claim 1 wherein an n-FET gate stack is present on a portion of said SiO2 layer that is located atop said silicon layer, and wherein a p-FET gate stack is present atop another portion of said SiO2layer that is located atop said silicon germanium layer, said n-FET gate stack is comprised of different materials that said p-FET gate stack.
10. The structure of claim 9 wherein said n-FET gate stack comprises, from bottom to top, HfO2 or HfSiOx, La2O3, TiN and polysilicon.
11. The structure of claim 10 wherein said n-FET gate stack comprises, from bottom to top, HfO2 or HfSiOx, TiN and polysilicon.
12. A semiconductor structure, comprising:
a substrate having disposed thereon a silicon layer and a silicon germanium layer;
an insulator disposed between the silicon layer and the silicon germanium layer; and
a SiO2layer disposed on the silicon layer and the silicon germanium layer.
13. The structure as claimed in claim 12 wherein the silicon germanium layer has a Ge concentration of approximately 20%.
14. The structure of claim 12 wherein said insulator has an upper most surface that is coplanar within an uppermost surface of each of said silicon layer and said silicon germanium layer.
15. The structure of claim 12 wherein said insulator has one vertical sidewall in direct physical contact with a vertical sidewall of said silicon layer and another vertical sidewall in direct physical contact with a vertical sidewall of said silicon germanium layer.
16. The structure of claim 12 wherein said substrate comprises bulk silicon.
17. The structure of claim 12 wherein said silicon germanium layer is present at a p-FET region of the substrate, and the silicon layer is present at an n-FET region of said substrate.
18. The structure of claim 12 wherein said silicon germanium layer consists essentially of silicon and germanium, and said silicon layer consists essentially of silicon.
19. The structure of claim 12 wherein an n-FET gate stack is present on a portion of said SiO2 layer that is located atop said silicon layer, and wherein a p-FET gate stack is present atop another portion of said SiO2layer that is located atop said silicon germanium layer, said n-FET gate stack is comprised of different materials that said p-FET gate stack.
20. The structure of claim 9 wherein said n-FET gate stack comprises, from bottom to top, HfO2 or HfSiOx, La2O3, TiN and polysilicon, and said n-FET gate stack comprises, from bottom to top, HfO2 or HfSiOx, TiN and polysilicon.
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