US20120105759A1

US20120105759A1 - Liquid crystal display and method for manufacturing the same

Info

Publication number: US20120105759A1
Application number: US13/044,143
Authority: US
Inventors: Ju-Yong Park; Ji-young Jeong; Jae-ho Lee; Eung-Gyu Lee
Original assignee: Individual
Current assignee: Samsung Display Co Ltd
Priority date: 2010-10-28
Filing date: 2011-03-09
Publication date: 2012-05-03
Also published as: KR101731398B1; US20130278879A1; KR20120044778A; US9329438B2

Abstract

The present invention relates to a liquid crystal display and a method for manufacturing the same. The liquid crystal display includes: a first substrate and a second substrate; a liquid crystal layer positioned between the first substrate and the second substrate; a spacer formed on the second substrate; and an opposite portion of the first substrate, the opposite portion positioned to correspond to the spacer, the opposite portion has an opposite region including an opposite surface facing the first surface, and a groove generally forming an outer boundary of the opposite region, and an area of the opposite region is larger than an area of the first surface.

Description

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to, and the benefit of, Korean Patent Application No. 10-2010-0106264 filed in the Korean Intellectual Property Office on Oct. 28, 2010, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

(a) Field of the Invention
Embodiments of the present invention relate generally to flat panel displays. More specifically, embodiments of the present invention relate to a liquid crystal display and a method for manufacturing the same.
(b) Description of the Related Art
Liquid crystal displays are one flat panel display technology that has found wide acceptance. Typical liquid crystal displays include two sheets of display panels on which electric field generating electrodes, such as pixel electrodes and common electrodes, are formed. A liquid crystal layer is inserted between the display panels. Liquid crystal displays generate an electric field in the liquid crystal layer by applying a voltage to the electric field generating electrode, determining the directions of the liquid crystal molecules via the resulting electric field, and displaying an image by controlling polarization of incident light.
A predetermined cell gap is preferably maintained between the two display panels, and for this, active spacers can be used. Bead spacers and column spacers can be used as the active spacer.
Bead spacers are advantageous in that they can be produced by a simple process and are thus relatively easy to manufacture. However, bead spacers often float within liquid crystal, and thus move with the liquid crystal during injection. If the bead spacers are moved sufficiently far, they may press against an alignment layer, causing undesirable light leakage. Alternatively (though somewhat rarely), the column spacers may instead be formed by photolithography, such that they are fixed at desired positions. However, these column spacers have smaller elastic strength as well as smear characteristics, such that the panel may be stained due to collapse of the column spacers or the lower layer when large pressure is applied to the liquid crystal display.
Everyday use, accidental impacts, and simple atmospheric pressure can result in forces applied to liquid crystal displays. These forces can be vertical loads, or two- or three-dimensional loads with both vertical and horizontal components.
When a sufficiently large vertical (i.e., normal to the face of the display screen) load is applied, the column spacers may be plastically deformed, and may fail to recover their original shape after the load is removed. This may result in permanent depressions in the display, where the liquid crystal layer is thinner than in other areas, in turn resulting in local luminance differences.
When a three-dimensional load is applied, the column spacers may slide, moving to an active region. When this happens, the alignment layer of the active region may be damaged and/or stained.
Further, when a three-dimensional load is applied, the column spacers may fail to return to the initial positions and cell gaps may be changed by the movement of the column spacers, even if the alignment layer is not damaged. Stains may be seen in the panel, as regions with different cell gaps display different luminances.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention, and thus may contain information not in the prior art.

SUMMARY OF THE INVENTION

Embodiments of the present invention provide a liquid crystal display including spacers that can more effectively prevent a stain phenomenon due to external loading.
An exemplary embodiment of the present invention provides a liquid crystal display including: a first substrate and a second substrate; a liquid crystal layer positioned between the first substrate and the second substrate; a spacer formed on the second substrate; and an opposite portion positioned to correspond to the spacer, in which the spacer has a first surface facing the first substrate, the opposite portion has an opposite region including an opposite surface facing the first surface, and a groove generally forming an outer boundary of the opposite region, and the area of the opposite region is larger than that of the first surface.
A width of the groove may be smaller than that of the first surface.
The spacer may be formed in a non-display area.
The groove may be formed to surround the opposite region.
The opposite region may be shaped as any one of a circle, an ellipse, and a polygon.
The first surface may be shaped as any one of a circle, an ellipse, and a polygon.
The diameter or the width of the opposite region may be from about 5 to about 40 um.
The depth of the groove may be from about 0.01 to about 3 um.
The groove may include a first groove and a second groove, the first and second grooves having differing depths.
The first groove may be positioned closer to the opposite region than the second groove, and the depth of the second groove may be larger than that of the first groove.
The difference between the depth of the first groove and the depth of the second groove may be from about 0.01 to about 3 um.
The first substrate may be a thin film transistor substrate and the second substrate may be a color filter substrate.
The liquid crystal display may further include: a gate line and a data line disposed on the first substrate; a thin film transistor connected to the gate line and the data line; and a passivation layer formed on the thin film transistor, in which the groove may be formed in the passivation layer.
The liquid crystal display may further include a color filter formed on the second substrate, in which the spacer may be formed on the color filter.
The spacer may be formed to at least partially overlap the thin film transistor.
The spacer may be formed to at least partially overlap at least one of the data line and the gate line.
The liquid crystal display may further include a metal layer formed on the first substrate, and an insulating layer at least partially covering the metal layer, in which the groove may be formed on the metal layer and a step may be formed over the groove on the insulating layer.
The metal layer may be a gate conductor or a data conductor. The spacer may be a main spacer formed to contact the first substrate, or a sub-spacer disposed at a predetermined distance from the first substrate.
Another exemplary embodiment of the present invention provides a method of manufacturing a liquid crystal display which includes: forming a spacer on a second substrate; forming an opposite portion on a first substrate, the opposite portion positioned to correspond to the spacer; and inserting a liquid crystal layer between the first substrate and the second substrate, in which the spacer has a first surface facing the first substrate, the opposite portion has an opposite region having an opposite surface being in contact with the first surface, the forming of an opposite portion includes forming a groove generally along an outer boundary of the opposite region, and an area of the opposite region is larger than that of the first surface.
A width of the groove may be smaller than that of the first surface.
The groove may be formed to surround the opposite region.
The forming of the opposite portion may further include: forming a gate line and a data line on the first substrate; forming a thin film transistor connected to the gate line and the data line; forming a passivation layer on the thin film transistor; and forming the opposite portion on the passivation layer.
The forming of the spacer may further include: forming a light blocking member and a color filter on the second substrate; and forming the spacer on the light blocking member and the color filter.
The spacer may be formed to at least partially overlap the thin film transistor.
The spacer may be formed to at least partially overlap at least one of the gate line and the data line.
Yet another exemplary embodiment of the present invention provides a liquid crystal display including: a first insulation substrate; a gate line formed on the first insulation substrate; a data line formed on the first insulation substrate and intersecting the gate line; a thin film transistor electrically connected to the gate line and the data line; a passivation layer at least partially covering the gate line, the data line, and the thin film transistor, the passivation layer having a contact hole exposing a portion of the thin film transistor, and a groove pattern formed therein, the groove pattern having a depth less than or equal to a depth of the contact hole; a pixel electrode electrically connected to the portion of the thin film transistor which is exposed by the contact hole; a second insulation substrate facing the first insulation substrate; a spacer formed on the second insulation substrate and maintaining a distance between the first insulation substrate and the second insulation substrate; and a liquid crystal layer positioned between the first insulation substrate and the second insulation substrate, in which the spacer is positioned within the groove pattern.
The groove pattern may at least partially surround the thin film transistor.
The groove pattern may be formed on at least one of the gate line and the data line.
The spacer may contact the first insulation substrate.
Still another exemplary embodiment of the present invention provides a liquid crystal display including: a first insulation substrate; a metal layer formed on the first insulation substrate and having a groove; an insulating layer at least partially covering the metal layer; a second insulation substrate facing the first insulation substrate; a spacer formed on the second insulation substrate and maintaining a distance between the first insulation substrate and the second insulation substrate; and a liquid crystal layer positioned between the first insulation substrate and the second insulation substrate. The spacer at least partially overlaps the metal layer and is positioned adjacent to the groove. A step is formed over the groove on the insulating layer.
The metal layer may be a gate conductor or a data conductor.
It is possible to provide a liquid crystal display including a spacer that can prevent a stain phenomenon due to externally-applied loads.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a liquid crystal display according to an exemplary embodiment of the present invention and FIG. 2 is a top plan view of a lower panel of the liquid crystal display shown in FIG. 1.

FIG. 3 is a cross-sectional view of a liquid crystal display according to another exemplary embodiment of the present invention.

FIG. 4 is a cross-sectional view of a liquid crystal display according to another exemplary embodiment of the present invention.

FIG. 5 and FIG. 6 are top plan views of a lower panel of a liquid crystal display according to another exemplary embodiment of the present invention.

FIG. 7 is a top plan view showing a liquid crystal display according to another exemplary embodiment of the present invention,

FIG. 8 is a cross-sectional view of the liquid crystal display of FIG. 7, taken along the line VIII-VIII, and

FIG. 9 is a cross-sectional view of the liquid crystal display, taken along the line IX-IX.

FIG. 10 and FIG. 11 are cross-sectional views of exemplary embodiments different from those shown in FIG. 8 and FIG. 9, respectively.

FIG. 12 is a top plan view showing another example of the portion where a sub-spacer 320S is formed in the liquid crystal display of FIG. 7 and

FIG. 13 is a cross-sectional view of the liquid crystal display of FIG. 12, taken along the line XIII-XIII.

FIG. 14 to FIG. 16 are cross-sectional views of an embodiment different from that of FIG. 13.

FIG. 17 and FIG. 18 are top plan views showing a liquid crystal display according to another exemplary embodiment of the present invention.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The present invention will be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.
In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like reference numerals designate like elements throughout the specification. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.
FIG. 1 is a cross-sectional view of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is a plan view of the upper face of a lower panel of the liquid crystal display shown in FIG. 1. Referring to FIG. 1 and FIG. 2, a liquid crystal display includes a lower panel 100, an upper panel 200, and a liquid crystal layer 3 disposed between the panels.
A spacer 320 is formed on the upper panel 200. The spacer 320 has a first surface 321 facing the lower panel 100.
An opposite portion 103 of the lower panel 100 is positioned to correspond to the spacer 320. The opposite portion 103 has an opposite region 102 formed generally flat, and a groove 101 formed proximate to the opposite region 102. The groove 101 can generally define the outer boundary of the opposite region 102. The opposite region 102 has an opposite surface 104 facing the first surface 321 of the spacer 320. The groove 101 is formed to surround the opposite region 102.
The width W2 of the opposite region 102 is larger than the width (e.g., diameter) W1 of the first surface 321. That is, the area of the opposite region 102 is larger than the area of the first surface 321. The area of the opposite region 102 may be formed in the range of about 5 um to about 40 um.
When a vertical load is applied to the liquid crystal display, the entire first surface 321 of the spacer 320 can contact the opposite region 102. Since the opposite region 102 is flat, stress is distributed relatively evenly over the entire first surface 321. Therefore, strain of the spacer 320 due to vertical loads is minimized, in turn reducing defects due to vertical loads.
When a three-dimensional load is applied to the liquid crystal display, the upper panel 200 can slide, and the spacer 320 can move into the groove 101. In this position, the first surface 321 of the spacer 320 is positioned on both the opposite area 102 and the groove 101, such that the contact area between the first surface 321 of the spacer 320 and the opposite region 102 of the opposite portion 103 is reduced. Due to the reduction in contact area by the groove 101, more loads are applied to the spacer 320 and the spacer 320 fails to further slide. Thus, the groove 101 has a locking effect, effectively trapping the spacer 320 and preventing the spacer 320 and upper panel 200 from sliding further. The spacer 320 is kept from moving onto the active region by the locking effect of the groove 101, thus preventing damage to the alignment layer.
Simulations were conducted to determine the amount that spacers 320 of embodiments of the invention slide upon application of a two- or three-dimensional force. It has been found that, when a three-dimensional load is applied, embodiments of the invention reduce sliding by about 50% or more. In a simulation, when the groove is formed adjacent to the opposite region, as in an exemplary embodiment of the present invention, it was possible to improve sliding of the spacers by about 60% as compared with the case where a groove is not formed.
That is, it is possible to obtain the effect of preventing sliding even without increasing the number of spacers, by forming a groove adjacent to the opposite region. Since it is not necessary to increase the number of spacers, it is possible to prevent the aperture ratio from reducing.
The width W3 of the groove 101 may be smaller than the width W1 of the first surface 321. In this case, the spacer 320 cannot move entirely into the groove 101, thus preventing excessive change in the spacer's height. Therefore, a change in a cell gap is prevented, reducing or eliminating edge stains. The depth h of the groove 101 may be formed in the range of approximately 0.01 um to approximately 3 um. For example, the width W3 and the depth h of the groove 101 may be about 0.2 um and about 0.4 um, respectively.
When the first surface 321 is a circle, W1 is its diameter. When the opposite region 102 is a square, W2 is the length of one side of the opposite region 102. W3 is the width of the groove 101. The diameter W1 of the first surface 321 is smaller than the length W2 of one side of the opposite region 102, and the width W3 of the groove 101 is smaller than the diameter W1 of the first surface 321.
The shapes of the first surface 321 and the opposite region 102 shown in FIG. 2 are just examples. The first surface 321 may have various shapes, such as a circle, an ellipse, or a polygon, and the opposite region 102 may also have various shapes, such as a circle, an ellipse, or a polygon.
FIG. 3 is a cross-sectional view of a liquid crystal display according to another exemplary embodiment of the present invention. FIG. 3 is the same as FIG. 1, except for the structure of the groove 101.
Referring to FIG. 3, the groove 101 includes a first groove 101 a and a second groove 101 b, which have differing depths. The first groove 101 a is formed closer to the opposite region 102 than the second groove 101 b. The depth h2 of the second groove 101 b is formed larger than the depth h1 of the first groove 101 a. The difference between the depth h1 of the first groove 101 a and the depth h2 of the second groove 101 b may be in the range of about 0.01 to about 3 um.
The width W3, that is the sum of the width W3 a of the first groove 101 a and the width W3 b of the second groove 101 b, may be formed smaller than the width of the first surface 321 of the spacer 320.
It is possible to adjust the sliding amount of the spacer, using the double groove structure as shown in FIG. 3.
In the figures described above, the spacer formed on the upper panel is illustrated as a main spacer that is in contact with the lower panel. However, the liquid crystal display according to an exemplary embodiment of the present invention may also be applied to a sub-spacer.
FIG. 4 is a cross-sectional view of a liquid crystal display according to another exemplary embodiment of the present invention. FIG. 4 is the same as FIG. 1, except that the spacer 320 is a sub-spacer.
Referring to FIG. 4, the spacer 320 is disposed at a predetermined distance d apart from the lower panel 100. An opposite portion 103 corresponding to the spacer 320 is formed on the lower panel 100. The opposite portion 103 has an opposite region 102 formed generally flat, and a groove 101 formed adjacent to the opposite region 102.
As described above, the liquid crystal display according to an exemplary embodiment of the present invention can be applied to a main spacer and/or a sub-spacer.
FIG. 5 and FIG. 6 are top plan views of a lower plate of a liquid crystal display according to another exemplary embodiment of the present invention. FIG. 5 and FIG. 6 are the same as FIG. 2, except for the structure of the groove 101.
Referring to FIG. 5, the groove 101 is formed adjacent to the opposite region 102, and includes grooves 101 c formed above and under the opposite region 102, as well as grooves 101 d formed at the left and right of the opposite region 102. In FIG. 2, the groove 101 is a single continuous groove formed to completely surround the opposite region 102, while in FIG. 5, the groove 101 is formed in segments with gaps inbetween, so as to surround portions of the opposite region 102.
Referring to FIG. 6, the groove 101 includes a plurality of grooves 101 e and 101 f that are separated from each other. One groove 101 is formed in FIG. 2, whereas a plurality of grooves 101 e and 101 f are formed in FIG. 6. Each of the grooves may have a different depth, as can the areas inbetween.
FIG. 7 is a top plan view showing a liquid crystal display according to another exemplary embodiment of the present invention, FIG. 8 is a cross-sectional view taken along the line VIII-VIII of FIG. 7, and FIG. 9 is a cross-sectional view of the liquid crystal display, taken along the line IX-IX of FIG. 7.
Referring to FIG. 7 to FIG. 9, the liquid crystal display includes thin film transistor array panels 100 facing each other, a common electrode panel 200, and a liquid crystal layer 3 formed therebetween.
A thin film transistor array panel 100 is described first.
The thin film transistor array panel 100 includes a first substrate 110 that is an insulation substrate, gate lines 121 and data lines 171 that intersect each other to define pixel regions on the first substrate 110, thin film transistors (TFT) connected to the gate lines 121 and the data lines 171, pixel electrodes 191 connected with the thin film transistors (TFT) in the pixel regions, and storage electrodes 131 formed at the lower portions of the data lines 171 and the edges of the pixel regions.
A gate conductor, including the gate lines 121 and the storage electrodes 131, is formed on the first substrate 110.
The gate lines 121 are formed generally along one direction on the first substrate 110, and gate electrodes 124 protrude from the gate lines 121.
Two gate lines 121 are formed between the pixels PX1-PX5 and PX6-PX10. Therefore, the gate lines 121 are formed above and under one pixel. The pixels PX2, PX3, PX7, and PX8 are connected to the upper portion of the gate line 121, and the pixels PX1, PX4, PX5, PX6, PX9, and PX10 are connected to the lower portion of the gate line 121.
The storage electrode 131 is composed of a first portion 131 a overlapping the data line 171, and a second portion 131 b connected to the first portion 131 a and surrounding the edge of the pixel region.
A gate insulating layer 140 made of a material such as silicon nitride (SiNx) or silicon oxide (SiO₂) is formed on the gate line 121 and the storage electrode 131.
A semiconductor stripe 151 can be made of amorphous or crystalline silicon, and is formed on the gate insulating layer 140. The semiconductor stripe 151 has a protrusion 154 extending to the gate electrode 124. An ohmic contact stripe 161 can be made of a material such as n+ hydrogenated amorphous silicon doped with silicide or n-type impurity at high concentration, and is formed on the semiconductor stripe 151. A pair of ohmic contacts 163 and 165 is formed on the protrusion 154. The ohmic contact 163 is connected to the ohmic contact stripe 161.
A data conductor includes a plurality of data lines 171, a plurality of drain electrodes 175, and a plurality of source electrodes 173, and is formed on the ohmic contacts 161, 163, and 165.
The data lines 171 transmit data signals, and are formed to intersect the gate lines 121. Source electrodes 173 are formed to extend from the data lines 171 in the same direction as the gate lines 121, and protrude upward from the gate electrodes 124. In this configuration, the source electrodes 173 extend left and right from the data lines 171, in generally the same direction as the gate lines 121. The source electrode 173 extending leftward from the data line 171 protrudes upward from the gate electrode 124 of the upper gate line 121, while the source electrode 173 extending rightward protrudes upward from the gate electrode 124 of the lower gate line 121. Thus, the pixels PX2 and PX9 are connected to the source electrodes 173 that extend left and right from the data line 171, respectively.
Drain electrodes 175 are formed above the gate electrodes 124, at a predetermined distance from their corresponding source electrodes 173.
The thin film transistor TFT is composed of the gate electrode 124, the protrusion 154 of the semiconductor stripe 151, the source electrode 173, and the drain electrode 175.
The semiconductor stripe 151, which includes the protrusion 154, has substantially the same plane shape as the data conductors 171, 173, and 175 and the ohmic contacts 161, 163, and 165 under the data conductors, except for the channel region between the source electrode 173 and the drain electrode 175. That is, the semiconductor stripe 151, including the protrusion 154, has portions that are not covered by the data conductors 171, 173, and 175 and are exposed, in addition to the portions exposed between source electrodes 173 and the drain electrodes 175.
A passivation layer 180 is formed on the gate insulating layer 140, the data conductors 171, 173, and 175 and the exposed portion of the protrusion 154.
The passivation layer 180 provides a generally flat surface and acts as an insulating layer. A groove 180M and 180S pattern and a plurality of contact holes 185 exposing the drain electrode 175 are formed on the passivation layer 180. The depth of the groove 180M and 180S pattern may be smaller than or about the same as the depth of the contact holes 185. The grooves 180M and 180S shown in FIG. 8 and FIG. 9 do not expose the data conductors 173 and 175 or the gate insulting layer 140. The grooves 180M and 180S may be formed by additionally and selectively etching the passivation layer 180, such as by dry etching.
A pixel electrode 191 is formed on the passivation layer 180. The pixel electrode 191 is connected to the drain electrode 175 of the thin film transistor (TFT) through the contact hole 185 formed on the passivation layer 180, and receives data voltages from the drain electrode 175.
A common electrode panel 200 is described hereafter.
The common electrode panel 200 includes a second substrate 210 that is an insulation substrate, and a light blocking member 220, called a black matrix, on the second substrate 210. The light blocking member 220 is provided to prevent light leakage, and may be formed and positioned to cover the gate line 121, the data line 171, the thin film transistor (TFT), and the storage electrode 131. However, in other embodiments, the light blocking member 220 may instead be formed on the thin film transistor array panel 100.
A color filter 230 is formed on the light blocking member 220 and the second substrate 210 of the pixel. The color filter 230 is provided to implement the colors of the liquid crystal display. For example, the color filter 230 may be implemented as a repeating layout of red, green, and blue color filters 230.
A column spacer 320 is formed on the color filter 230. The spacer 320 includes a main spacer 320M overlapping the thin film transistor, and a sub-spacer 320S overlapping the source electrode 173.
A common electrode 270 is formed on the spacer 320 and the color filter 230.
A first alignment layer 11 and a second alignment layer 12 are formed on each of the inner sides of the first thin film transistor array panel 100 and the common electrode panel 200 respectively.
A liquid crystal layer 3 includes a plurality of liquid crystal molecules (not shown), and is interposed between the thin film transistor array panel 100 and the common electrode panel 200. The liquid crystal molecules in the liquid crystal layer 3 are rearranged by using an electric field generated by the common electrode 270 and the pixel electrode 191, and collectively, the layer 3 and electrodes 191, 270 implement a number of liquid crystal capacitors.
The storage electrode 131 and the pixel electrode 191 overlapping the storage electrode 131 implement a storage capacitor that assists the liquid crystal capacitor.
An opposite portion corresponding to the spacer 320 is formed at the passivation layer 180. The opposite portion includes a flat opposite region and grooves 180M and 180S formed adjacent to the opposite region. The opposite region of the opposite portion is formed larger than the area of a first surface where the spacer 320 faces the thin film transistor array panel 100. Further, the widths of the grooves 180M and 180S are smaller than the width of the first surface of the spacer 320.
Although FIG. 7 to FIG. 9 show a main spacer 320M that overlaps the thin film transistor (TFT) and a sub-spacer 320S that overlaps the data line 171, the type and position of the spacer are not limited thereto. The spacers may be formed in any area, such as a non-display area or a peripheral area of the pixel electrode. In general, the non-display area corresponds to the light blocking member 220. The spacer may be formed to overlap the thin film transistor, the data line, and/or the gate line in the non-display area.
Further, the spacer may be a main spacer or a sub-spacer, regardless of the position to be formed.
The above embodiments described grooves formed in a generally flat passivation layer. However, the invention is not limited to such configurations, and attention now turns to other embodiments.
FIG. 10 and FIG. 11 are cross-sectional views according to exemplary embodiments that are different from those shown in FIG. 8 and FIG. 9, respectively. The same constituent elements as those in the exemplary embodiments shown in FIG. 8 and FIG. 9 are given the same reference numerals, and repetitive description is omitted.
Referring to FIG. 10 and FIG. 11, grooves 180M′ and 180S′ are formed in a passivation layer 180, and expose data conductors 173 and 175, or a gate insulating layer 140. The grooves 180M′ and 180S′ may be formed by etching the passivation layer 180, such as by dry etching. The grooves 180M′ and 180S′ can be formed by the same process as that for forming a contact hole 185, such that a separate process may not be needed.
Although FIG. 11 shows a groove 180S′ that is formed only in the passivation layer 180 and that exposes the gate insulating layer 140, the groove 180S′ may alternatively be formed in both the passivation layer 180 and the gate insulating layer 140 so as to expose substrate 110 or gate conductor 121.
FIG. 12 is a top plan view showing a configuration in which sub-spacer 320S is formed in the liquid crystal display of FIG. 7 and FIG. 13 is a cross-sectional view of the liquid crystal display of FIG. 12, taken along the line XIII-XIII. The same constituent elements as those of the exemplary embodiment shown in FIG. 9 are given the same reference numerals, and any repetitive description is omitted.
Referring to FIG. 12, the surface of the sub-spacer 320S that faces the thin film transistor array panel 100 is formed generally in an ellipse. The source electrode 173 is formed between two gate lines 121, and includes an expansion region 173 a corresponding to (e.g., under) the sub-spacer 320S. Grooves H are formed adjacent to the opposite regions that face the sub-spacers 320S.
Referring to FIG. 13, the passivation layer 180 does not provide a generally flat surface, unlike FIG. 9. A groove H1 formed on the lower panel 100 is formed by forming a groove 180S1 on the passivation layer 180. The groove 180S1 does not extend all the way through the passivation layer 180, and thus does not expose the data conductor 173 a under the groove 180S1. The groove 180S1 can be formed by additionally and selectively etching the passivation layer 180, such as by dry etching.
FIG. 14 to FIG. 16 are cross-sectional views according to exemplary embodiments different from those shown in FIG. 13. The same constituent elements as those of the embodiment shown in FIG. 13 are given the same reference numerals, and any repetitive description is omitted.
Referring to FIG. 14, a groove H2 is formed by forming a groove 180S2 on the passivation layer 180. The groove 180S2 exposes the data conductor 173 a, unlike in FIG. 13. The groove 180S2 can be formed by the same process as that for forming a contact hole (see reference numeral 185 of FIG. 10), such that a separate process may not be required.
Referring to FIG. 15, a groove H3 is formed by forming a groove 173H1 on the data conductor 173 a. The groove 173H1 does not extend through the data conductor 173 a, and thus does not expose the ohmic contact 161. The groove 173H1 forms a step or channel-like depression on the passivation layer 180 and the alignment layer 11, such that the groove H3 is formed. The groove 173H1 may be formed by additionally and selectively etching the data conductor 173 a, such as by wet etching.
Referring to FIG. 16, the groove H4 is formed by forming a groove 173H2 on the data conductor 173 a. The groove 173H2 exposes the ohmic contact 161, unlike in the embodiment of FIG. 15. Even though the groove 173H2 is formed to expose the ohmic contact 161, referring to FIG. 12, the source electrode 173 includes expanding region 173 a, such that the source electrode 173 is not disconnected.
Although FIG. 16 shows a groove 173H2 that is formed only through the data conductor 173 a to expose the ohmic contact 161, the groove 173H2 may alternatively be formed through both the data conductor 173 a and the ohmic contact 161, so as to expose the semiconductor stripe 151.
As described above, the groove for preventing the spacer from sliding may be formed at the passivation layer or the data conductor. Additionally, the groove may be formed not only on the data conductor, but also on a metal layer, such as the gate conductor. The groove formed on the passivation layer or the metal layer may extend only partially through these layers, or may extend completely through, so as to expose another layer formed under the passivation layer or the metal layer.
FIG. 17 and FIG. 18 are top plan views showing a liquid crystal display according to another exemplary embodiment of the present invention.
The liquid crystal display shown in FIG. 17 includes a spacer overlapping a thin film transistor (TFT), and a spacer overlapping a gate line. The liquid crystal display shown in FIG. 18 includes a spacer overlapping a gate line.
Therefore, it is possible to provide a liquid crystal display including a spacer that can prevent a stain phenomenon that occurs due to externally-applied loads.
It is possible to more uniformly distribute the vertical load upon the spacer, and to minimize strain of the spacer, by flattening the spacer face closest to its opposing substrate. Further, it is possible to prevent the spacer from sliding due to external loads, by forming a groove in the opposing substrate and proximate to the spacer.
While this invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

DESCRIPTION OF SYMBOLS

- 3: Liquid crystal layer
- 100: Lower panel
- 110, 210: Substrate
- 121, 124: Gate line, Gate electrode
- 140: Gate insulating layer
- 171, 173, 175: Data line, Source electrode, Drain electrode
- 180: Passivation layer
- 191: Pixel electrode
- 200: Upper panel
- 220: Light blocking member
- 230: Color filter
- 270: Common electrode
- 320: Spacer

Claims

1. A liquid crystal display comprising:

a first substrate and a second substrate;

a liquid crystal layer positioned between the first substrate and the second substrate;

a spacer formed on the second substrate; and

an opposite portion of the first substrate, the opposite portion positioned to correspond to the spacer,

wherein the spacer has a first surface facing the first substrate,

wherein the opposite portion has an opposite region including an opposite surface facing the first surface, and a groove generally forming an outer boundary of the opposite region, and

wherein an area of the opposite region is larger than the area of the first surface.

2. The liquid crystal display of claim 1, wherein:

a width of the groove is smaller than a width of the first surface.

3. The liquid crystal display of claim 2, wherein:

the spacer is formed in a non-display area.

4. The liquid crystal display of claim 3, wherein:

the groove is formed to surround the opposite region.

5. The liquid crystal display of claim 4, wherein:

the opposite region is shaped as one of a circle, an ellipse, and a polygon.

6. The liquid crystal display of claim 5, wherein:

the first surface is shaped as one of a circle, an ellipse, and a polygon.

7. The liquid crystal display of claim 6, wherein:

the diameter or the width of the opposite region is from about 5 to about 40 um.

8. The liquid crystal display of claim 7, wherein:

the depth of the groove is from about 0.01 to about 3 um.

9. The liquid crystal display of claim 1, wherein:

the groove includes a first groove and a second groove, the first and second grooves having differing depths.

10. The liquid crystal display of claim 9, wherein:

the first groove is positioned closer to the opposite region than the second groove and

the depth of the second groove is larger than the depth of the first groove.

11. The liquid crystal display of claim 10, wherein:

the difference between the depth of the first groove and the depth of the second groove is from about 0.01 to about 3 um.

12. The liquid crystal display of claim 1, wherein:

the first substrate is a thin film transistor substrate and the second substrate is a color filter substrate.

13. The liquid crystal display of claim 12, further comprising:

a gate line and a data line disposed on the first substrate;

a thin film transistor connected to the gate line and the data line; and

a passivation layer formed on the thin film transistor,

wherein the groove is formed in the passivation layer.

14. The liquid crystal display of claim 13, further comprising:

a color filter formed on the second substrate,

wherein the spacer is formed on the color filter.

15. The liquid crystal display of claim 14, wherein:

the spacer at least partially overlaps the thin film transistor.

16. The liquid crystal display of claim 14, wherein:

the spacer at least partially overlaps at least one of the data line and the gate line.

17. The liquid crystal display of claim 12, further comprising:

a metal layer formed on the first substrate, and an insulating layer at least partially covering the metal layer,

wherein the groove is formed on the metal layer, and

a step is formed over the groove on the insulating layer.

18. The liquid crystal display of claim 17, wherein:

the metal layer is a gate conductor or a data conductor.

19. The liquid crystal display of claim 1, wherein:

the spacer is a main spacer formed to contact the first substrate, or a sub-spacer disposed at a predetermined distance from the first substrate.

20. A method of manufacturing a liquid crystal display, comprising;

forming a spacer on a second substrate;

forming an opposite portion on a first substrate, the opposite portion positioned to correspond to the spacer; and

inserting a liquid crystal layer between the first substrate and the second substrate,

wherein the spacer has a first surface facing the first substrate,

wherein the opposite portion has an opposite region having an opposite surface being in contact with the first surface,

wherein the forming of an opposite portion includes forming a groove generally along an outer boundary of the opposite region, and

wherein an area of the opposite region is larger than an area of the first surface.

21. The method of claim 20, wherein:

a width of the groove is smaller than a width of the first surface.

22. The method of claim 21, wherein:

the groove is formed to surround the opposite region.

23. The method of claim 20, wherein the forming of the opposite portion further includes:

forming a gate line and a data line on the first substrate;

forming a thin film transistor connected to the gate line and the data line;

forming a passivation layer on the thin film transistor; and

forming the opposite portion on the passivation layer.

24. The method of claim 23, wherein the forming of the spacer further includes:

forming a light blocking member and a color filter on the second substrate; and

forming the spacer on the light blocking member and the color filter.

25. The method of claim 24, wherein:

the spacer is formed to at least partially overlap the thin film transistor.

26. The method of claim 24, wherein:

the spacer is formed to at least partially overlap at least one of the gate line and the data line.

27. A liquid crystal display comprising:

a first insulation substrate;

a gate line formed on the first insulation substrate;

a data line formed on the first insulation substrate and intersecting the gate line;

a thin film transistor electrically connected to the gate line and the data line;

a passivation layer at least partially covering the gate line, the data line, and the thin film transistor, the passivation layer having a contact hole exposing a portion of the thin film transistor, and a groove pattern formed therein, the groove pattern having a depth less than or equal to a depth of the contact hole;

a pixel electrode electrically connected to the portion of the thin film transistor which is exposed by the contact hole;

a second insulation substrate facing the first insulation substrate;

a spacer formed on the second insulation substrate and maintaining a distance between the first insulation substrate and the second insulation substrate; and

a liquid crystal layer positioned between the first insulation substrate and the second insulation substrate,

wherein the spacer is positioned within the groove pattern.

28. The liquid crystal display of claim 27, wherein:

the groove pattern at least partially surrounds the thin film transistor.

29. The liquid crystal display of claim 27, wherein:

the groove pattern is formed on at least one of the gate line and the data line.

30. The liquid crystal display of claim 27, wherein:

the spacer contacts the first insulation substrate.

31. A liquid crystal display comprising:

a first insulation substrate;

a metal layer formed on the first insulation substrate and having a groove;

an insulating layer at least partially covering the metal layer;

a second insulation substrate facing the first insulation substrate;

wherein the spacer at least partially overlaps the metal layer and is positioned adjacent to the groove, and

wherein a step is formed over the groove on the insulating layer.

32. The liquid crystal display of claim 31, wherein:

the metal layer is a gate conductor or a data conductor.