US20120045872A1

US20120045872A1 - Semiconductor Memory Device

Info

Publication number: US20120045872A1
Application number: US13/285,648
Authority: US
Inventors: Sang Min Hwang
Original assignee: Hynix Semiconductor Inc
Current assignee: SK Hynix Inc
Priority date: 2008-10-30
Filing date: 2011-10-31
Publication date: 2012-02-23
Also published as: KR20100048119A; US8072077B2; US20100109162A1; KR101037501B1

Abstract

Disclosed herein is a semiconductor memory device for reducing a junction resistance and increasing amount of current throughout the unit cell. A semiconductor memory device comprises plural unit cells, each coupled to contacts formed in different shape at both sides of a word line in a cell array.

Description

CROSS-REFERENCE TO RELATED APPLICATION

This is a divisional application which is based on and claims priority to U.S. application Ser. No. 12/344,708 entitled “Semiconductor Memory Device,” filed Dec. 29, 2008, which, in turn, claims the priority benefit under 35 USC §119 of Korean patent application number 10-2008-0107139, filed on Oct. 30, 2008, the entire disclosures of which are hereby incorporated by reference herein in their entirety.

BACKGROUND OF THE INVENTION

The invention relates generally to a method for fabricating a semiconductor device and, more specifically, to a technology of forming a floating body transistor used in a highly-integrated semiconductor device using a silicon-on-insulator (SOI) structure.
In many semiconductor device systems, a semiconductor memory device is configured to store data generated or processed in the device. For example, if a request from a data processor such as a central processing unit (CPU) is received, a semiconductor memory device may output data to the data processor from unit cells in the device, or the device may store data processed by the data processor to unit cells of an address transmitted with the request.
Although data storage capacity of semiconductor memory device has increased, the size of semiconductor memory device has not increased proportionally because various elements and components used for read or write operations in a semiconductor memory device have reduced in size. Accordingly, components and elements unnecessarily duplicated in the semiconductor memory device, such as transistors or wires, are combined or merged to decrease the area occupied by each component. Particularly, the reduction of the size of unit cells included in the semiconductor memory device affects improvement of the degree of integration.
As an example of a semiconductor memory device, Dynamic Random Access Memory (DRAM) is a type of volatile memory device configured to retain data while a power source is supplied. The unit cell comprises a transistor and a capacitor. In the case of the unit cell having a capacitor, after the datum “1” is delivered to the capacitor, charges that are temporarily stored in the storage node are dissipated, i.e., the amount of the charge stored therein is reduced, because of both leakage currents generated at junction of the storage nodes and inherent characteristics of the capacitor. As a result, a refresh operation is periodically required on the unit cells so that data stored in the DRAM cannot be destroyed.
In order to prevent the reduction of charge, numerous methods for increasing capacitance (Cs) of the capacitor included in the unit cell have been suggested so that more charges may be stored in the storage node. Otherwise, a capacitor having a two-dimensional structure is changed to have a three-dimensional cylindrical structure or a trench structure, thereby increasing the surface area of both electrodes of the capacitor. However, as the design rule is reduced, the plane area where a capacitor can be formed is reduced, and it is difficult to develop materials constituting an insulating film in the capacitor. As a result, the junction resistance value of the storage node (SN) and the turn-on resistance value of the transistor in the unit cell are larger, and accordingly it is difficult to perform normal read and write operations, and refresh characteristics deteriorate.
To improve the above-described shortcomings, the unit cell may comprise a transistor having a floating body. Thus, the unit cell of the semiconductor memory device does not include a capacitor used for storing data, but stores data in a floating body of the transistor included in the unit cell.
FIG. 1 is a circuit diagram illustrating a cell array of a general semiconductor memory device that includes unit cells each configured as a floating body transistor without any capacitors.
As shown, each unit cell included in the cell array includes a floating body transistor without any capacitors. In the floating body transistor, a gate is connected to one of word lines WL0 to WL3, a source is connected to one of source lines SL0 to SL3, and a drain is connected to one of bit lines BL0 and BL1. Also, the cell array further includes a dummy word line formed between the unit cells.
FIG. 2 is a cross-sectional diagram illustrating the cell array of FIG. 1 formed over a semiconductor substrate.
As shown, the cell array is formed over a SOI substrate that includes a bottom silicon layer 201, a buried insulating film 202 and a top silicon layer 203. In the top silicon layer 203, a portion except for the silicon active region 210 is etched, and buried with a device isolation film 211. A first gate pattern that includes a first gate spacer 203 and a first gate electrode 204 is formed over the center of the silicon active region 210, a second gate pattern that include a second gate spacer 213 and a second gate electrodes 214 are located over the device isolation film 211. Herein, the first gate electrode 204 located over the silicon active region 210 corresponds to one of the word lines WL0 to WL3 shown in FIG. 1, and the second gate electrode 214 positioned over the device isolation film 211 corresponds to the dummy word line WL shown in FIG. 1.
A contact plug 205 is formed at both sides of the gate pattern located over the silicon active region 210. One side is connected to a bit line 209 through a bit line contact 208, and the other side is connected to a source line 207 through a source line contact 206. The bit line 209 and the source line 207 are formed at a different level and at an intersection with each other.
FIGS. 3 to 6 c are diagrams illustrating the cell array shown in FIG. 2.
Referring to FIG. 3, the island-shaped silicon active regions 210 are arranged over the SOI substrate in row and column directions. The neighboring silicon active regions 210 arranged in the row direction share the first gate electrode 204 as the word line WL. Between the neighboring silicon active regions 210 arranged in the column direction, the second gate electrode 214 over the device isolation film is formed as the dummy word line WL.
Referring to FIG. 4 a, a contact plug mask 224 covers a space between the neighboring silicon active regions 210 arranged in the row direction to form a contact plug. A conductive material is deposited over the silicon active region 210 exposed between the first and second gate electrodes 204 and 214. Referring to FIG. 4 b, formations of the gate electrode 204 and the contact plug 205 over the silicon active region 210 are understandable to people skilled in the art.
As shown in FIG. 5 a, the conductive material deposited over the silicon active region 210 remains as the contact plug 205. A source line contact 206 is formed over one of the two contact plugs 205 located over the silicon active region 210. Referring to FIG. 5 b, the source line contact 206 is formed over one of the two contact plugs 205.
Referring to FIG. 6 a, the bit line contact 208 is formed over the other of the two contact plugs 205. A source line is formed over the source line contact 206 in a word line (WL) direction. The bit line 209 is formed in the column direction of the silicon active region 210. Particularly, FIG. 6 b shows when the source line 206 is formed over the source line contact 206, and FIG. 6 c shows when the bit line contact 208 is formed over the contact plug 205.
In the case of the unit cell including the above-described floating body transistor, holes remain in the floating body out of hot carriers generated corresponding to positive voltages (V_G>0, V_D>0) through the word line and a ground voltage GND (0V) applied to the source. While the semiconductor memory device performs a read operation for outputting data stored in the unit cells, a voltage is first supplied to the word line to turn on a cell transistor and, then, whether holes remain in the floating body, i.e., which the datum stored in the floating body is “0” or “1”, is understood based on the amount and speed of current flowing from the source line to the bit line.
In the case of the unit cell of the above-described cell array, one of source/drain of the floating body transistor is connected to the source line 207 through the contact plug 205 and the source line contact 206. If a junction resistance between the source line 207 and the source line contact 206 or between the source line contact 206 and the one of source/drain is large, the amount and speed of current flowing through a channel of the floating body transistor can be determined based on the junction resistance rather than the amount of holes stored in the floating body. In this case, it is difficult to distinguish data values “0” from “1” stored in the floating body transistor, thereby degrading the operation of the semiconductor memory device.

BRIEF SUMMARY OF THE INVENTION

FIG. 1 is a circuit diagram illustrating a cell array of a general semiconductor memory device that includes unit cells each configured as a floating body transistor without any capacitors.

FIG. 2 is a cross-sectional diagram illustrating the cell array of FIG. 1 formed over a semiconductor substrate.

FIGS. 3 to 6 c are diagrams illustrating the cell array shown in FIG. 2.

FIGS. 7 a to 9 c are diagrams illustrating a cell array including a unit cell configured as a floating body transistor in a semiconductor memory device according to an embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

Various embodiments of the present invention are directed to providing a semiconductor memory device including a cell structure and a cell region layout for reducing a junction resistance and increasing amount of current throughout the unit cell in order to improve data sensing margin during read/write operations.
According to an embodiment of the present invention, a semiconductor memory device comprises plural unit cells, each coupled to contacts formed in different shape at both sides of a word line in a cell array.
Preferably, the semiconductor memory device further comprises a bit line for transferring data to the unit cell and a source line for flowing amount of current into the unit cell during a read/write operation.
Preferably, the bit line is arranged in a cross-direction of the word line and the source line is arranged in a direction of the word line.
Preferably, the contacts include a first contact having an island shape for connecting one portion of an active region in the unit cell to the bit line and a second contact having a line shape for connecting the other portion of the active region to the source line.
Preferably, the unit cells aligned in a direction of the word line hold the second contact in common.
Preferably, the first contact includes a first contact plug connected to the one portion at a level of the word line and a bit line contact for connecting the first contact plug to the bit line.
Preferably, the second contact includes a second contact plug connected to the other portion at a level of the word line and a source line contact for connecting the second contact plug to the source line.
Preferably, each unit cell separated from neighboring unit cell by an isolation layer includes a floating body transistor having a gate used as the word line and source/drain formed in an active region.
Preferably, the number of unit cells included in single active region is 1 to 2.
Preferably, the cell array further includes a dummy word line formed on the isolation layer.
According to another embodiment of the present invention, a method for manufacturing a semiconductor memory device comprises forming contacts having different shape at both sides of word lines included in a cell array, wherein the contacts are formed in every unit cell.
Preferably, the method further comprises forming the word lines crossed over plural active regions included in the cell array, wherein every one or two word lines is formed over single active region and performing ion-implantation to form source/drain in each of the plural active regions.
Preferably, the forming-contacts-having-different-shape includes forming a first contact having an island shape on the drain of the active region and forming a second contact having a line shape on the source of the active region.
Preferably, the unit cells aligned in a direction of the word line hold the second contact in common.
Preferably, the method further comprises forming a bit line on the first contact, wherein the bit line is arranged in a cross-direction of the word line and forming a source line on the second contact, wherein the source line is arranged in a direction of the word line.

DESCRIPTION OF EMBODIMENTS

A semiconductor memory device comprising a cell array that includes a unit cell including a floating body transistor is configured to reduce a resistance between a source line and one side of source/drain of the floating body transistor so that more current may flow in the floating body transistor to guarantee a stable operation. Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.
FIGS. 7 a to 9 c are diagrams illustrating a cell array including a unit cell configured as a floating body transistor in a semiconductor memory device according to an embodiment of the present invention.
Referring to FIG. 7 a, an island-shaped silicon active regions 710 are arranged over the SOI substrate in row and column directions. The neighboring silicon active regions 710 arranged in the row direction share the first gate electrode 704 as the word line WL. Between the neighboring silicon active regions 710 arranged in the column direction, the second gate electrode 714 over the device isolation film is formed as the dummy word line WL.
Contact plug masks 724 are arranged to form a contact plug. Referring to 4 a, the conventional contact plug mask 224 has an aligned line pattern between the neighboring active regions. The contact plug mask 224 exposes the top portion of the active region with the word line 704 and the dummy word line 714. The island-shaped contact plug 205 is formed in the exposed region. Unlike the conventional art, the contact plug mask 724 is formed to have not a line shape but an island shape. The contact plug mask 724 does not cover all spaces between the neighboring active regions but covers a portion from the dummy word line to the word line. As a result, a region where a source line is formed at one side of the word line can be exposed.
Referring to FIG. 7 b, a first contact plug 705 a and a second contact plug 705 b are formed in the exposed region by the contact plug mask 724, the word line 704 and the dummy word line 714. The first contact plug 705 a is formed over the active region positioned at one side of the word line so as to have an island shape. The second contact plug 705 b is configured to have a line shape that can be shared by neighboring unit cells in the word line direction. Referring to FIG. 7 c, the second contact plug 705 b arranged in the same direction of the word line 704 is shown. Since FIG. 7 c is a conceptual diagram illustrating a three-dimensional structure of the unit cell, operational components included in the semiconductor memory device are mainly explained, and an insulating film, a spacer, a device isolation film are omitted herein.
Referring to FIG. 8 a, a source line contact 706 is formed over the second contact plug 705 b. The source line contact 706 has a line shape that can be shared by the neighboring unit cells. Referring to FIGS. 8 a and 8 b, the source line contact 706 is horizontally placed between the word line 704 and the dummy word line 714, and vertically positioned over the second contact plug 705 b.
Referring to FIG. 9 a, a source line 707 is formed over the source line contact 706, and a bit line contact 708 is formed over the first contact plug 705 a. A bit line 709 is formed over the bit line contact 708 at an intersection with the word line 704.
Referring to FIG. 9 b, the source line 707 is placed over the source line contact 706. Unlike the conventional art, a plurality of unit cells that share the source line 707 can share the line-shaped source line contact 706 a and the second contact plug 705 b. As a result, the junction resistance between the source line 707 and the source line contact 706 and between the source line contact 706 and the second contact plug 705 b can be reduced. As the junction resistance is reduced, the amount of current supplied to each unit cell is increased and, then, variations of amount and speed of current flowed depending on the amount of holes stored in the floating body becomes wider, thereby increasing a data sensing margin.
FIG. 9 c shows the bit line contact 708 located over the first contact plug 705 a. The island-shaped bit line contact 708 is formed to be higher than the source line 707 for connection with the bit line 709. The bit line contact 708 is substantially similar to the conventional bit line contact 208 shown in FIG. 6 c.
As described above, the disclosed method for manufacturing a semiconductor memory device comprises forming a word line at an intersection with an active region in a cell array, and forming a different shaped contact plug at both sides of a word line. Through this method, the semiconductor memory device includes a different shaped contact plug at both sides of the word line of the cell array. Particularly, contact plugs include the first island-shaped contact plug 705 a placed over the active region 710 positioned at one side of the word line 704, and the second line-shaped contact plug 705 b shared by the neighboring unit cells located at the other side of the word line 704. Each unit cell includes a floating body transistor that has a gate used as the word line 704 and source/drain formed in the active region 710. The unit cell is isolated from the neighboring unit cell through a device isolation film. Also, one unit cell is formed in one active region 710, and the dummy word line 714 is positioned over the device isolation film in the same direction of the word line 704.
Herein, the first and the second contact plugs 705 a and 705 b are a kind of conductive patterns. There are various methods for forming any conductive pattern in a semiconductor device. For example, a method for forming a conductive pattern includes detailed processes: depositing an insulating layer over a semiconductor substrate; etching a partial portion of the insulating layer; and then filling a conductive material into an etched portion. Accordingly, contrary to a conventional art having an island-type contact plug, a pattern shape included in a mask for defining the first and second contact plugs 705 a and 705 b during the etching step is changed into a line-type. In the present invention, detailed processes for forming the first and the second contact plugs 705 a and 705 b are omitted in figures because those is well known to people skilled in the art.
In a semiconductor memory device according to an embodiment of the present invention, a contact plug and a source line contact for connecting an active region of the unit cell to a source line is formed as a line-type pattern which is hold in common by neighboring unit cells so that a junction resistance between the unit cell and the source line decreases. As a result, more amount of current can flow through the unit cell accessed during a read/write operation than a conventional semiconductor memory device, and a data sensing margin of the semiconductor memory device is increased.
The above embodiments of the present invention are illustrative and not limitative. Various alternatives and equivalents are possible. The invention is not limited by the type of deposition, etching polishing, and patterning steps describe herein. Nor is the invention limited to any specific type of semiconductor device. For example, the present invention may be implemented in a dynamic random access memory (DRAM) device or non-volatile memory device. Other additions, subtractions, or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims.

Claims

What is claimed is:

1. A method for manufacturing a semiconductor memory device, comprising:

forming contacts having different shape at both sides of word lines included in a cell array, wherein the contacts are formed in every unit cell.

2. The method according to claim 1, further comprising:

forming the word lines crossed over plural active regions included in the cell array, wherein every one or two word lines is formed over single active region; and

performing ion-implantation to form source/drain in each of the plural active regions.

3. The method according to claim 2, wherein the forming-contacts-having-different-shape includes:

forming a first contact having an island shape on the drain of the active region; and

forming a second contact having a line shape on the source of the active region.

4. The method according to claim 3, wherein the unit cells aligned in a direction of the word line hold the second contact in common.

5. The method according to claim 3, further comprising:

forming a bit line on the first contact, wherein the bit line is arranged in a cross-direction of the word line; and

forming a source line on the second contact, wherein the source line is arranged in a direction of the word line.