US20110025376A1

US20110025376A1 - System for the flexible configuration of functional modules

Info

Publication number: US20110025376A1
Application number: US12/311,856
Authority: US
Inventors: Udo Grittke; Axel Humpert; Dietmar Fruhauf; Romuald Girardey; Jurgen Becker; Katarina Paulsson; Michael Hubner
Original assignee: Endress and Hauser SE and Co KG
Current assignee: Endress and Hauser SE and Co KG
Priority date: 2006-10-17
Filing date: 2007-09-10
Publication date: 2011-02-03
Also published as: WO2008046695A1; EP2113067B1; US20110029254A1; WO2008046694A1; EP2082485A2; EP2082191A1; WO2008046696A2; US20110035576A1; WO2008046696A3; EP2113067A1; US8271773B2; EP2082191B1

Abstract

A system for the flexible configuration of function modules. The system includes the following components a plurality of logic cells in a fixedly wired FPGA/standard ASIC structure, wherein the logic cells are so configurable by means of configuration registers, that they execute basic logic functions; a switch matrix having a plurality of memory cells, via which different logical connections of the logic cells in defined complex connections are configurable by means of the configuration registers; and a control unit, which partially dynamically so configures the logic cells and the switch matrix via an internal bus and via the configuration registers by means of a configuration bit stream, that the fixedly wired FPGA/ASIC structure behaves functionally as a partially dynamically reconfigurable logic chip.

Description

The invention relates to a system for flexible configuration of function modules, especially for flexible, configuration of function modules in a field device of process automation.
In automation technology, especially in process automation technology, field devices are often applied, which serve for determining and monitoring process variables. Examples of such field devices include fill level measuring devices, flow measuring devices, analytical measuring devices, pressure and temperature measuring devices, and moisture and conductivity measuring devices. The sensors of these field devices register the corresponding process variables, e.g. fill level, flow, pH-value, substance concentration, pressure, temperature, moisture and conductivity.
Subsumed under the term ‘field devices’ are, however, also actuators, e.g. valves or pumps, via which, for example, the flow of a liquid in a pipeline or the fill level in a container is changeable. A large number of such field devices are available from members of the firm, Endress+Hauser.
As a rule, field devices in modern automation technology plants are connected via communication networks (HART multidrop, point to point connection, Profibus, Foundation Fieldbus, etc.) with a superordinated unit, which is referred to as a control system or control room. This superordinated unit serves for process control, process visualizing, process monitoring, as well as for start-up, or for servicing, of the field devices.
Necessary supplemental components for operation of fieldbus systems, i.e. components, which are directly connected to a fieldbus and which serve especially for communication with the superordinated units, are likewise frequently referred to as field devices. These supplemental components include e.g. remote I/Os, gateways, linking devices or controllers.
Known also is to integrate fieldbus systems in enterprise networks, which work on an Ethernet basis. These enterprise-internal, bus systems permit access to process, or field device, information from different areas of an enterprise. Moreover, it is state of the art to connect company networks with public networks, e.g. the Internet, for the purpose of worldwide communication.
For servicing and for start-up of field devices, corresponding operating programs are necessary. Known, in such case, are, for example, the operating program FieldCare of Endress+Hauser, the operating program AMS of Emerson and the operating program Simatic PDM of Siemens.
Serving for control and monitoring of plants having a plurality of field devices are control system applications, such as e.g. Simatic S7 of Siemens, Freelance of ABB and Delta V of Emerson.
An essential aspect of open communication systems, such as e.g. Profibus, Foundation Fieldbus or HART, is the interoperability and exchangeability of devices of different manufacturers. Thus, sensors or actuators of various manufacturers can be applied, without problem, together in a plant. Also an option is to replace a field device of one manufacturer with a functionally equal field device of another manufacturer, whereby the customer has a highest measure of freedom in the configuration of its process installation.
Field devices are becoming increasingly complex as regards their functionality. Besides pure, measured value processing, diagnostic tasks and, above all, communication tasks, which the field devices must fulfill with respect to the installed bus systems, are becoming always more complex. Still more complex are functionalities in field devices having multisensor capability. These field devices must be able to determine or to monitor, in parallel, at least two process variables. In order to meet these increasing requirements, a number of microcontrollers are often provided in parallel in a field device. The advantage in the use of microcontrollers is that, via application-specific software programs, which run in these microcontrollers, the most varied of functionalities are implementable and program changes can be put into practice relatively simply. Program controlled field devices are, therefore, flexible in high measure. This high flexibility is, however, gained with the disadvantage, that, because of the sequential progression through the programs, processing speed is slowed.
In order to increase processing speed, when it makes sense, ASICs—Application Specific Integrated Circuits—are applied in field devices. Through their application-specific configuration, these chips can process data and signals significantly faster than a software program can. ASICs are excellent especially for computationally intensive applications.
Disadvantageous in the case of the application of ASICs is that the functionality of these chips is fixedly predetermined. A subsequent changing of the functionality of these chips is not directly possible. Furthermore, the use of ASICs makes sense only in the case of relatively large piece numbers, since the developmental effort and the therewith connected costs are relatively high.
In order to avoid the drawback of fixedly predetermined functionality, WO 03/098154 proposes a configurable field device, wherein a reconfigurable logic chip in the form of an FPGA is provided. In the case of this known solution, the logic chip has at least one microcontroller, which is also referred to as an embedded controller. The logic chip is configured during system start. After the configuration is finished, the required software is loaded into the microcontroller.
The reconfigurable logic chip required in such case must have available sufficient resources, such as sufficient logic, wiring and memory resources, in order to fulfill the desired functionalities. Logic chips with many resources require much energy, and, with that energy, their use in process automation is limitless. Disadvantageous in the use of logic chips with few resources, and, thus, having smaller energy consumption, is the considerable limitation in the functionality of the corresponding field device.
In the International patent application filed simultaneously with this International application and claiming the priorities of three German patent applications: DE 10 2006 049 509.8, DE 10 2006 049 501.2, DE 10 2006 049 502.0, filed on 17 Oct. 2006, the advantages of the partial, dynamic reconfigurability of logic chips for use in fieldbus devices are described at length. In the semiconductor market, different modern technologies are known, which enable connecting the high flexibility in the design phase of FPGA architectures with the energy efficiency of final ASIC architectures. Examples of this are the technologies “HardCopy” of Altera and “EasyPath” of XILINX. With these technologies, electrical current saving, hard, or fixedly, wired architectures can be produced very rapidly and cost effectively. Due to the fixed wiring, these architectures possess, however, the disadvantage, that the suitability for reconfigurability, especially also for partial and dynamic reconfigurability, is lost.
An object of the invention is to make at least certain portions of an electronic hardware structure, which are, per se, not dynamically configurable, dynamically, or partially dynamically, configurable.
The object is achieved by a system, which has the following components: A plurality of logic cells in a fixedly wired FPGA/standard ASIC structure, wherein the logic cells, or logic blocks, are so configurable by means of configuration registers, that they execute basic logic functions; a switch matrix with a plurality of memory cells, via which different logical connections of the logic cells are configurable in defined complex connections by means of the configuration registers; and a control unit, which dynamically or partially dynamically so configures the logic cells and the switch matrix, via an internal bus and via the configuration registers, by means of a configuration bit stream, that the fixedly wired FPGA/standard ASIC structure behaves functionally as a dynamically or partially dynamically reconfigurable standard logic chip. The configuration can be referred to as static/dynamic Co Design. The invention provides an architecture, which connects all advantages of partial, dynamic reconfigurability—such as described in the above cited, parallel International patent application—with those of fixedly wired architectures. These advantages are mainly: Very short developmental times, cost reduction and energy saving. As an additional advantage, a significantly faster reconfiguration is achieved.
Preferably, the fixedly wired FPGA/standard ASIC structure is a Hardcopy FPGA, an EASY Path, a flash FPGA or an FPGA based on AntiFuse technology.
In principle, any of these known FPGA technologies can be utilized, in order to provide, from a rigid, configurable electronic architecture, an, in high measure, flexible, configurable electronic architecture. In general, it can be stated, that, according to the invention, a partially dynamically reconfigurable structure is mapped in a standard design process (e.g. Altera Structured ASIC, Xilinx Flex Path, Antifuse FPGA) virtually onto a fixedly wired FPGA/ASIC structure through utilization and integration of a flexible FPGA model.
The dynamically reconfigurable function modules are, for example, microprocessors, A/D or D/A converters with different bit resolutions, signal filters with different filter functions, modems for connection to different bus systems, different electrical current control units or different in/output units. A preferred embodiment of the solution of the invention provides, that, besides the regions of the dynamically reconfigurable function modules, at least one static region is provided, in which at least one predeterminable function module is permanently configured. The permanently configured function module can be, for example, a microprocessor of predetermined bus width.
The advantages of the solution of the invention are many and greatly exceed those, which known solutions provide:
The configuration builds on known technology and on standard processes;
variability and flexibility of configuration is, in principle, unlimited;
due to the fixedly wired architecture, high processing speed and, therewith, low processing time are achieved, so that systems embodied according to the invention work in real time;
due to the fixed wiring of the architecture, electrical current/energy consumption is low;
a further electrical current/energy saving is possible, in that always only the instantaneously required function modules are configured; and
a high integration density can be achieved.
In a preferred embodiment of the system of the invention, a logic cell is composed of an n bit look up table structure, wherein the n inputs select via a multiplexer an associated configuration register and so configure the desired basic logic function. In an example, the n inputs are two inputs A, B. The configurable basic logic function of a logic cell is, for example, an AND, an OR, a NAND, NOR, ExOR or ExNOR gate.
An advantageous further development of the system of the invention provides that each logic cell includes a flip flop and that the output signal of the flip flop is available at the output of the logic cell. Through the integration of a flip-flop, the integration of sequential logic, such as, for example, that of a finite automaton, is made possible.
As already earlier indicated, the system of the invention is preferably applied in field devices in the field of process automation. Field devices serve, such as already stated, for determining or monitoring a physical or chemical process variable. The physical or chemical process variable is, for example, pressure, fill level, flow, turbidity, concentration of a chemical substance, viscosity, density, temperature, moisture, pH-value or conductivity.
The impressive advantages of the solution of the invention are especially to be seen in its high flexibility, its small energy consumption and its providing of measurement data in real time. The solution of the invention enables, on the basis of a known ASIC—examples were already cited above—the control/evaluation unit of any field device to be configured to the extent desired. Since the different field devices of a manufacturer can, based on the solution of the invention, rely on one and the same hardware, the solution of the invention can also be implemented cost effectively, since the fixedly wired FPGAs/standard ASICs are more cost effective, the higher the piece number to be produced. Furthermore, a field device can be reconfigured at any point in time, without problem, for another use. The solution of the invention offers great advantages also in the field of multisensor capability, where a control/evaluation unit must be able to react to different sensor types in parallel or intermittently. Since it is provided, according to the invention, that always only the instantaneously required function modules are dynamically, or partially dynamically, configured, the energy supply is assured, even in the case of very complex FPGA/ASIC structures.
Although the system of the invention is discussed in the examples of embodiments always in connection with a field device, the system can also be applied in other fields, for example, in automobile or aircraft technology. As regards its opportunities for application, it is overall applicable, where fixedly wired FPGAs/standard ASICs are applied and where energy saving makes sense. Thus, use of the solution of the invention is quite justifiably to be taken into consideration even in the case of conventional PCs.

The invention. will now be explained in greater detail on the basis of the appended drawing, the figures of which show as follows:

FIG. 1 the construction of a known ASIC, which is applied, by way of example, in a pressure measuring device;

FIG. 2 a a first embodiment of the partially dynamically configurable system of the invention, which likewise is applied in a pressure measuring device;

FIG. 2 b a second embodiment of the dynamically or partially dynamically configurable system of the invention, which is applied in a pressure measuring device;

FIG. 3. A schematic drawing of an embodiment of the virtual FPGA/ASIC structure of the invention;

FIG. 4 a drawing, by way of example, of a logic cell usable in the system of the invention; and

FIG. 5 a drawing, by way of example, of a virtual switch matrix usable in the system of the invention.

FIG. 1 shows the known construction of an ASIC, which is applied, by way of example, in a pressure measuring device. Pressure measuring devices are used for different applications, for example, for absolute, relative, or pressure difference measurement, for determining the fill level of a fill substance in a container or for determining the flow of a medium through a pipeline. In the case illustrated in FIG. 1, the pressure measuring device is applied for fill level measurement. Corresponding pressure measuring devices, which can be applied in different applications, are available from the assignee.
Receiving the measurement data is the known control/evaluation unit 19, which is accommodated usually in a measurement transmitter. The control/evaluation unit 19 receives the measurement data from a pressure sensor (not separately illustrated in FIG. 1) via the analog input 24. The analog input 24 is labeled with IN. Since the ASIC is fixedly wired, the control/evaluation unit 19 with the function modules 2 is exclusively usable in the predefined, particular application. In the illustrated case, the control/evaluation unit 19 is designed for a pressure measuring device in the application, fill level measurement. The field device is subsequently exclusively applicable for a pressure measuring device, which is used for fill level measurement and which, moreover, transmits its data via a HART protocol to a superordinated control room (not particularized in FIG. 1). The corresponding data line 24 is labeled with OUT
In detail, FIG. 1 shows the following fixedly wired system:
The analog measurement data are converted by an 8 bit A/D converter 12 into digital data, wherein the accuracy of conversion depends decisively on the bit resolution of the A/D converter 12. Then, the digital data are filtered in the filter 14 of a certain type 2 and evaluated in the evaluation unit 22. The determining of the fill level value L occurs here via a functional dependence of P. Concretely, a polynomial P=f(p, T) is involved, which depends functionally on pressure p and temperature T. In the function module 23, there then occurs the calculating of the corresponding fill level value. Subsequently, the digital value is converted in the D/A converter/filter 13 into an analog, measured value and suitably filtered. Via a HART modem 15, which likewise is operated by the microcontroller 11, the measurement data and status information are transmitted, in accordance with the HART protocol, to the superordinated control room. The operating of the individual function modules 2 by the microprocessor 11 occurs via the control lines 26.
FIG. 2 a shows a first embodiment of the dynamically or partially dynamically configurable system 1 of the invention, which, by way of example, is applied in a pressure measuring device, but which, however, is usable according to the invention also for other applications.
Goal of the system 1 of the invention is to make at least certain function modules 2 of a not dynamically, or partially dynamically, hardware reconfigurable, electronic ASIC architecture flexible. This is achieved by mapping logic cells, modeled in the hardware description language VHDL, in a standard design process, onto a permanently wired FPGA/ASIC standard structure. The standard design process is, for example, Altera Structured ASIC, Xilinx FlexPath or Antifuse FPGA.
An important difference relative to the known solution illustrated in FIG. 1 is the high flexibility, which the solution of the invention offers. In such case, it is to be brought out, that certain function modules 11, 22 can still have a permanently wired structure, and that only certain function modules 2; 12, 13, 14, 15, 16, 23 are embodied partially dynamically configurably. The operating of the configurably embodied function modules 12, 13, 14, 15, 23 occurs via the configuration bit stream controlled by the control unit 8 and transmitted via the internal bus 25 to the individual function modules 2 to be operated. According to the invention, the configuration occurs in such a manner, that the fixedly wired FPGA/ASIC structure behaves functionally as a partially dynamically reconfigurable logic chip. The logic chip is preferably a standard FPGA.
Thus, any desired configuration of the individual configurable function modules 2; 12, 13, 14, 15, 16, 23 is possible with one and the same FPGA. The freedom in the selection of the different embodiments of the function modules 2 is indicated in FIG. 2 by providing different embodiments in each of the function modules 2; 12, 13, 14, 15, 16, 23. Thus, both the A/D converter 12 as well as the D/A converter 13 can have different bit resolutions of 8 bit, 12 bit, 16 bit or 21 bit. Likewise, in the function module 14, or in the function module 13, different types of filters can be configured.
Through the dynamic configuring of the function module 23, it is possible to adapt the pressure sensor, which can work in different applications, such as fill level, flow and pressure measurement, optimally to the particular application. High flexibility is, moreover, provided for the task of data transmission to a superordinated control room on data line 24 labeled with OUT. For example, HART, PA—Profibus PA—or FF—Fieldbus Foundation—can be selected, so that the data transmission to the control room can occur in accordance with the selected protocol.
FIG. 2 b shows a second embodiment of the dynamically configurable system 1 of the invention, which is usable in a pressure measuring device. Compared to the form of embodiment shown in FIG. 2 a, this embodiment differs essentially by the insertion of the function module 18 labeled ‘Switch Matrix’. This function module 18 enables connection of the dynamically reconfigurable function modules 2 with one another in suitable manner. Besides the tasks of connecting logic cells 3 and wiring resources suitably, it is, according to a further development of the system of the invention 1, thus, also possible to connect dynamically reconfigurable function modules 2; 12, 13, 14, 15, 16, 23 partially dynamically with one another and so to provide highly complex, temporary FPGA/ASIC structures.
On the basis of the next FIGS. 3, 4, and 5, the particular way in which the system of the invention 1 works is described. FIG. 3 shows a schematic drawing of an embodiment of the virtual FPGA/standard ASIC structure of the invention. This structure corresponds—roughly stated—to a virtual FPGA standard structure with a predetermined amount of resources: logic cells 3, wiring resources 6 and memory cells 10.
Concretely, FIG. 3 shows schematically a 7×5 lattice structure of logic cells 3 and the switch matrix 6 of the virtual FPGA structure 1 of the invention. The switch matrix 6 contains the suitable connections of the wiring resources. Preferably, this structure 1 and the fixedly wired function modules 2; 11, 22 are embodied on one chip. Viewed technically, the flexible regions 2; 12, 13, 14, 15, 16, 23, as well as the fixedly wired regions 2; 11, 22, are implemented with predetermined fixed resources of the employed logic chip FPGA; however, through the effecting and integration of the flexible FPGA solution, the logic cells 3, or the logic blocks, as well as the wiring resources of the switch matrix 6, are kept flexible through application of logic connections, or logic gates.
FIG. 4 shows, by way of example, the construction of a logic cell 3 selected from FIG. 3 with a two-bit look-up table structure and with flip flop 10. The two inputs A and B of the logic cell 3 select via a multiplexer 9 the configuration register 4 a. Thus, for example, in the case of the constellation A=1 and B=1, the right configuration register 4 a, which contains the logical 1, is selected and made available on the output Q_LUT. The selected logic cell 3 represents a logical AND function with two inputs. Furthermore, the signal of the clock-controlled flip flop 10 is available on the output Q_FF,. Through integration of a flip flop 10, integration of sequential logic, such as, for example, that of a finite automaton, is made possible.
In the dynamic and partial dynamically reconfigurable, virtual FPGA 1, the contents of the configuration register 4; 4 a, 4 b are controlled via the configuration interface 5 by means of the configuration bit stream generated by the control unit 11. For example, by writing the sequence 0111 into the configuration register 4 a, the logical OR function can be implemented. By the method, thus, any basic logic functions can be represented. Of course, the limitation to two inputs A, B is arbitrary and only serves to focus the described subject matter. In principle, it can be stated, that the design of the logic cells 3 is model-based and, thus, kept parameterizable. Of course, all desired gate sizes can be implemented. Moreover, also other particular logic functions are integrateable into the logic cells 3. The layout of the connections or gates occurs during the design process and is fixedly wired after the chip integration.
More complex logic functions are implemented according to the invention by means of a plurality or a composite of logic cells 3. In order that this be possible, the logic cells 3 are embodied so that they can be connected with one another. Likewise, such as in the case of known FPGA structures, this occurs in the case of the virtual FPGA structure 1 of the invention via a switch matrix 6.
FIG. 5 shows a section of FIG. 3. Thus, FIG. 5 shows, for example, the virtual switch matrix 6 applied in the system of the invention 1 for connecting a plurality of configurable, basic logic cells 3. In this schematic drawing, the wiring resources of the logic cells 3 are only partially shown; thus, to avoid cluttering the drawing, only the two, bit inputs A, B of the neighboring logic cells 3 and their flexible switching via the switch matrix 6 are presented. As in the case of the logic cells 3, also in the case of the switch matrix 6, the inputs A, B are connected with the corresponding outputs via a programmable multiplexer structure (from the perspective of the switch matrix). Through reconfiguration of the configuration register 4 b, any connecting of the inputs and outputs of the switch matrix 6 can occur, which leads to a flexible, runtime-adaptive connecting of logic cells 3. As in the configuration of the logic cells 3, also the switch matrix 6 is model based and can by parametering during the design of the virtual FPGA 1 be matched to the requirements, especially to the configurable logic cells 3. Moreover, a heterogeneous virtual wiring structure is implementable, which enables an optimized signal throughput behavior in different regions.

List of Reference Characters

1 system of the invention
2 function module
3 logic cell/logic block
4 configuration register
4 a configuration register logic cells
4 b configuration register wiring resources
5 configuration interface
6 switch matrix
7 memory cell
8 control unit
9 multiplexer
10 flip flop/memory element
11 control unit/microprocessor
12 A/D converter
13 D/A converter
14 signal filter
15 modem
16 electrical current control unit
17 in/output unit
18 function module ‘connecting’
19 prior art control/evaluation unit
24 data line
25 internal bus
26 control line

Claims

1-10. (canceled)

11. A system for flexible configuration of function modules, comprising the following components:

a plurality of logic cells in a fixedly wired FPGA/standard ASIC structure, wherein said logic cells are so configurable by means of configuration registers, that they execute basic logic functions;

a switch matrix having a plurality of memory cells, via which different logical connections of said logic cells in defined complex connections are configurable by means of said configuration registers; and

a control unit, which partially dynamically so configures said logic cells and said switch matrix via an internal bus and via said configuration registers by means of a configuration bit stream, that the fixedly wired FPGA/ASIC structure functionally behaves as a partially dynamically reconfigurable, standard logic chip.

12. The system as claimed in claim 11, wherein:

the fixedly wired FPGA/ASIC structure is a Hardcopy FPGA, a EASY Path, a flash FPGA or an FPGA based on AntiFuse technology.

13. The system as claimed in claim 11, wherein:

a logic cell of said plurality of logic cells is composed of an n bit look up table structure, wherein the n inputs—in the case of n=2 these are two inputs A, B—select via a multiplexer an associated configuration register and so configure a desired basic logic function.

14. The system as claimed in claim 11, wherein:

the configurable basic logic function of a logic cell of said plurality of logic cells is, for example, an AND, an OR, a NAND, NOR, ExOR or ExNOR gate.

15. The system as claimed in claim 11, wherein:

each logic cell includes a flip flop and on the output of said logic cell, the output signal (Q_FF) of said flip flop is available.

16. The system as claimed in claim 11, wherein:

the dynamically reconfigurable function modules are, for example, microprocessors or A/D converters or D/A converters of different bit resolutions, signal filters having different filter functions, different modems for connection to different bus systems, different electrical current control units or different in/output units.

17. The system as claimed in claim 11, wherein:

besides the regions of dynamically reconfigurable function modules, at least one static region is provided, in which at least one predeterminable function module is permanently configured.

18. The system as claimed in claim 17, wherein:

said permanently configured function module is, for example, a microprocessor having a predetermined bit resolution.

19. The system as claimed in claim 11, wherein:

the system is the measuring and control electronics of a field device for determining or monitoring a physical or chemical, process variable in process automation.

20. The system as claimed in claim 11, wherein:

the physical or chemical process variable is, for example, one of the following process variables: Pressure, fill level, flow, turbidity, concentration of a chemical substance, viscosity, density, temperature, pH value, or conductivity.