US20100255666A1

US20100255666A1 - Thermal processing method

Info

Publication number: US20100255666A1
Application number: US12/819,337
Authority: US
Inventors: Chan-Lon Yang; Ching-I Li; Tzu-Feng Kuo; Yin-Ru Shi
Original assignee: United Microelectronics Corp
Current assignee: United Microelectronics Corp
Priority date: 2007-03-05
Filing date: 2010-06-21
Publication date: 2010-10-07
Also published as: US8058733B2; US20100264550A1; US20080217788A1; US7772064B2

Abstract

A thermal processing method is provided. First, a semiconductor substrate is provided. The semiconductor substrate has a metal-oxide-semiconductor transistor formed thereon. The metal-oxide-semiconductor transistor includes a gate and source and drain regions on two sides of the gate. Dopants are implanted into the source and drain region and the gate. Next, a cap layer is formed over the semiconductor substrate. Next, a first thermal process is performed, and then a second thermal process is performed. Next, the cap layer is removed. The thermal processing method is capable of uniformly heating a semiconductor substrate and reducing the pattern effect in the fabrication of a CMOS and to improve the performance of the CMOS.

Description

BACKGROUND

1. Field of the Invention
The present invention relates to a thermal processing method, and particularly to a thermal processing method for a complementary-metal-oxide-semiconductor (COMS) fabrication so as to avoid a pattern effect and improve the performance of the CMOS.
2. Description of the Related Art
Rapid thermal process (RTP) is a very important technology and has been widely applied to the thermal activating of semiconductor processes in the fabrication of very large scale integration (VLSI) field. It may be applied in the fabrication of an ultra shallow junction (USJ) of metal-oxide-semiconductor transistors, ultra thin oxide layer growth, annealing, diffusion, metal silicide, and even the semiconductor layer of thin film transistors. According to the development of thermal processes, the high-temperature furnace is a representative tool in earlier technology, and the spike rapid thermal annealing is widely utilized for rapid thermal treatment of the semiconductor. Currently, as the semiconductor technology is progressively developed, the millisecond annealing (also called the dynamic surface anneal, DSA), such as application of laser annealing, is being researched. Correspondingly, the process time of a thermal process is also being progressively shortened. For example, the process time is about 10 sec for the earlier furnace process, and the process time is shortened to about 1 sec or even about 1 msec (millisecond) for the current thermal process.
However, uneven heating across a surface of a substrate is a problem that is often experienced with RTP. For example, in a typical CMOS fabrication, the front surface of a semiconductor substrate is often heated directly after ion implantations to diffuse implanted ions into doping regions. Because varying non-silicon structures, such as shallow trench isolations (STIs) or other films are disposed on the front surface of the semiconductor substrate, the thermal absorption capability of the doping regions of the semiconductor substrate is different. Different thermal absorption properties across different areas of the doping regions of the semiconductor substrate can make non-uniform heating of the front surface of the semiconductor substrate during the thermal process and result in a pattern effect. Thus, the performance of the COMS may be adversely affected.
Therefore, what is needed is a thermal processing method capable of uniformly heating a semiconductor substrate to overcome the above disadvantages.

BRIEF SUMMARY

The present invention provides one embodiment realizes a thermal processing method for reducing the pattern effect in a CMOS fabrication and to improve the performance of the CMOS.
In one embodiment, the thermal processing method includes providing a semiconductor substrate. A metal-oxide-semiconductor (MOS) transistor is formed on the semiconductor substrate. The MOS transistor includes a gate and a source and drain region on two sides of the gate. Next, dopants are implanted into the source and drain region and the gate. Next, a cap layer is formed over the semiconductor substrate after the implanting step without any thermal treatment therebetween. Next, a first thermal process is performed and then a second thermal process is performed. Next, the cap layer is removed, for example by performing a dry etching process followed by a post etch cleaning process.
In one embodiment, the cap layer includes an amorphous carbon layer.
In one embodiment, the cap layer includes a stress memorization technique (SMT) layer.
In one embodiment, the SMT layer includes a material selected from a group consisting of silicon nitride and silicon oxide.
In one embodiment, the cap layer is removed by a wet etching process.
In one embodiment, disposing the cap layer on the semiconductor substrate includes: forming a SMT layer over the source and drain region and the gate of the MOS transistor of the semiconductor substrate and forming an amorphous carbon layer over the SMT layer; and the step of removing the cap layer includes: removing the amorphous carbon layer from the SMT layer and removing the SMT layer from the semiconductor substrate.
In one embodiment, the first thermal process is a rapid thermal process, and the second thermal process is a millisecond annealing process.
In one embodiment, the first thermal process is a millisecond annealing process, and the second thermal process is a rapid thermal process.
In one embodiment, the first thermal process and the second thermal process are performed simultaneously.
In one embodiment, the semiconductor substrate includes a first surface and a second surface opposite to the first surface, and the rapid thermal process and the millisecond annealing process are respectively applied onto the second surface and the first surface.
In one embodiment, the rapid thermal process and the millisecond annealing process are respectively applied onto the first surface.
In one embodiment, an amorphorization step is performed before the cap layer is formed.
The present invention provides a thermal processing method, which includes the following steps. A semiconductor substrate is provided. A MOS transistor is formed on the semiconductor substrate. The MOS transistor includes a gate and a source and drain region on two sides of the gate. Next, dopants are implanted into the source and drain region and the gate. Next, a cap layer is formed over the source and drain region and the gate of the MOS transistor of the semiconductor substrate after the implanting step without any thermal treatment therebetween. Next, a first thermal process is performed. The cap layer is removed. Next, a second thermal process is performed.
In the thermal processing method of the present invention, after the dopants are implanted into the source and drain region and the gate and before the thermal processes are performed, a cap layer is formed over the source and drain region of the MOS transistor unit of the semiconductor substrate after the implanting step without any thermal treatment therebetween. Thus, the semiconductor substrate, especially the source and drain region may be uniformly heated during thermal treatment. As a result, the device, for example, the COMS, may have the excellent electrical performance.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features and advantages of the various embodiments disclosed herein will be better understood with respect to the following description and drawings, in which like numbers refer to like parts throughout, and in which:

FIG. 1 illustrates a process flow of a thermal processing method in accordance with a first embodiment of the present invention.

FIG. 2 is a schematic view of a semiconductor substrate.

FIG. 3 is a schematic view of the semiconductor substrate with a cap layer formed over the source and drain region in accordance with the first embodiment of the present invention.

FIG. 4 is a schematic view of the semiconductor substrate under the thermal processes in accordance with the first embodiment of the present invention.

FIG. 5 illustrates a process flow of a thermal processing method in accordance with a second embodiment of the present invention.

FIG. 6 is a schematic view of the semiconductor substrate with a cap layer formed over the source and drain region in accordance with the second embodiment of the present invention.

FIG. 7 is a schematic view of the semiconductor substrate under the thermal processes in accordance with the second embodiment of the present invention.

FIG. 8 is flow chart of a thermal processing method in accordance with a third embodiment of the present invention.

DETAILED DESCRIPTION

FIG. 1 is a flow chart of a thermal processing method in accordance with a first embodiment of the present invention. Referring to FIG. 1, first, a semiconductor substrate 100, for example, a silicon wafer is provided. The semiconductor substrate 100 comprises a p-channel metal-oxide-semiconductor (PMOS) transistor and an n-channel metal-oxide-semiconductor (NMOS) transistor.
Referring to FIG. 2, the semiconductor substrate 100 comprises a first surface 102 and a second surface 104 opposite to the first surface 102. A MOS transistor 110 is formed on the first surface 102 of the semiconductor substrate 100. The MOS transistor 110 includes a gate dielectric layer 112, a gate 114, and a spacer 116. The gate dielectric layer 112 is formed on the first surface 102 of the semiconductor substrate 100. The gate 114 is formed on the gate dielectric layer 112. The gate 114, optionally with a dielectric hard mask (not shown) thereon, is made of a semiconductor material, multiple semiconductor materials, a conductive material, multiple conductive materials or any combination thereof. The spacer 116 of single layer or multiple layers is formed on the sidewall of the gate 114. The MOS transistor 110 further has a source and drain region 118 defined in the semiconductor substrate 100 on two sides of the gate 114.
Again, referring to FIG. 1 and FIG. 2, dopants 115 are implanted into the source and drain region 118 and the gate 114. Thus, the source and drain region 118 and the gate 114 are doped regions. The dopants 115 can be, for example, boron for the PMOS or phosphorus for the NMOS.
Subsequently, referring to FIG. 1 and FIG. 3, a cap layer 120 is formed over the semiconductor substrate 100. In the present embodiment, the cap layer 120 is a single layer. The cap layer 120 can be comprised of an amorphous carbon layer. A thickness of the amorphous carbon layer is in a range from 100 A (angstrom) to 5000 A, preferred 1000 A to 4000 A. The cap layer 120 can also be a stress memorization technique (SMT) layer. The SMT layer includes a material selected from a group consisting of silicon nitride and silicon oxide. It should be noted that there is no high temperature thermal treatment or process of a temperature higher than 800° C. between the step of source/drain implantation and the step of cap layer formation.
Next, a first thermal process is performed. And then, a second thermal process is performed. In the present embodiment, the first thermal process is a rapid thermal process (RTP), and the second thermal process is a millisecond annealing process, such as a laser annealing process. In addition, the first thermal process and the second thermal process can be performed simultaneously. In the present embodiment, referring to FIG. 4, the rapid thermal process and the millisecond annealing process are respectively applied towards and onto the second surface 104 and the first surface 102 of the semiconductor substrate 100 simultaneously. The temperature of the rapid thermal process is between 900° C. to 1100° C. and the duration of the rapid thermal process is between 1.5 ms to 100 ms. The temperature of the millisecond annealing process is between 1000° C. to 1350° C. and the duration of the millisecond annealing process is between 0.1 ms to 20 ms.
It is noted that rapid thermal process and the millisecond annealing process can be respectively applied towards and onto the second surface 104 and the first surface 102 of the semiconductor substrate 100 in sequence. It is also noted that the rapid thermal process and millisecond annealing process can also be respectively applied onto the first surface 102 of the semiconductor substrate 100 either simultaneously or in sequence.
Next, the cap layer 120 is removed. When the cap layer 120 is an amorphous carbon layer, the cap layer 120 can be removed by a dry etching process (e.g., a reactive ion etching process, RIE) followed by a post etch cleaning process. When the cap layer 120 is a SMT layer, the cap layer 120 can be removed by a wet etching process. For example, the SMT layer can be removed by a hot phosphoric acid. It is noted that, if the MOS transistor 110 is an NMOS transistor, before forming the SMT layer the spacer of the NMOS can be slimmed to enhance the stress effect caused by the SMT layer. That is, the SMT layer is mainly dedicated for the NMOS.
Preferably, an amorphorization step can be performed after the dopants 115 are implanted into the source and drain region 118 and the gate 114 and before the cap layer 120 is formed. The amorphorization step, for example, is an implantation step using heavy atoms such as Ge or atomic cluster.
FIG. 5 illustrates a process flow of a thermal processing method in accordance with a second embodiment of the present invention. Referring to FIG. 5, the thermal processing method in the second embodiment is similar to the thermal processing method in the first embodiment except for the step of forming the cap layer and removing the cap layer.
In the present embodiment, referring to FIG. 5 and FIG. 6, the cap layer 120 includes a first cap layer 122 formed over the semiconductor substrate 100 (in detail, over the source and drain region 118 and the gate 114) and a second cap layer 124 formed over the first cap layer 122. The first cap layer 122 can be an SMT layer. The SMT layer includes a material selected from a group consisting of silicon nitride and silicon oxide. The second cap layer 124 can also be an amorphous carbon layer. A thickness of the amorphous carbon layer is in a range from 100 A to 5000 A, preferred from 1000 A to 4000 A. Correspondingly, the step of removing the cap layer 120 includes removing the second cap layer 124 from the first cap layer 122 and removing the first cap layer 122 from the semiconductor substrate 100.
Additionally, referring to FIG. 7, in the second embodiment, the first thermal process is a millisecond annealing process, and the second thermal process is a rapid thermal process. The rapid thermal process and millisecond annealing process is respectively applied onto the first surface 102 of the semiconductor substrate 100 simultaneously. It is noted that the millisecond annealing process and the rapid thermal process can be respectively applied onto the first surface 102 of the semiconductor substrate 100 in sequence. It is also noted that the rapid thermal process and the millisecond annealing process can be respectively applied onto the second surface 104 and the first surface 102 of the semiconductor substrate 100 either simultaneously or in sequence.
FIG. 8 illustrates a process flow of a thermal processing method in accordance with a third embodiment of the present invention. Referring to FIG. 8, the thermal processing method in the third embodiment is similar to the thermal processing method in the first embodiment except for the process steps after the cap layer is formed. In the present embodiment, after a cap layer 120 is formed over the source and drain region 118 of the MOS transistor 110 of the semiconductor substrate 100. Next, a second thermal process is performed. The cap layer 120 is a SMT layer. The first thermal process is a rapid thermal process, and the second thermal process is a millisecond annealing process.
In summary, the present invention has at least the following advantages:
1. Because the cap layer is disposed over the semiconductor substrate, especially the source and drain region and the gate can be uniformly heated during a thermal treatment, thereby reducing the difference of the thermal absorption properties across different areas of the source and drain region and the gate.
2. Because the thermal processing method is capable of uniformly heating a semiconductor substrate, pattern effect in the fabrication of a CMOS may be effectively reduced and improve the performance of the CMOS.
The above description is given by way of example, and not limitation. Given the above disclosure, one skilled in the art could devise variations that are within the scope and spirit of the invention disclosed herein, including configurations ways of the recessed portions and materials and/or designs of the attaching structures. Further, the various features of the embodiments disclosed herein can be used alone, or in varying combinations with each other and are not intended to be limited to the specific combination described herein. Thus, the scope of the claims is not to be limited by the illustrated embodiments.

Claims

1. A thermal processing method, comprising:

providing a semiconductor substrate having a metal-oxide-semiconductor transistor formed thereon, wherein the metal-oxide-semiconductor transistor comprises a gate and a source and drain region on two sides of the gate;

implanting dopants into the source and drain region and the gate;

forming a cap layer over the semiconductor substrate after the implanting step without any thermal treatment therebetween;

performing a first thermal process;

performing a second thermal process; and

removing the cap layer.

2. The thermal processing method as claimed in claim 1, wherein the cap layer comprises an amorphous carbon layer.

3. The thermal processing method as claimed in claim 2, wherein the cap layer is removed by a dry etching process followed by post etch cleaning process.

4. The thermal processing method as claimed in claim 1, wherein the cap layer comprises a stress memorization technique layer.

5. The thermal processing method as claimed in claim 4, wherein the stress memorization technique layer comprises a material selected from a group consisting of silicon nitride and silicon oxide.

6. The thermal processing method as claimed in claim 4, wherein the cap layer is removed by a wet etching process.

7. The thermal processing method as claimed in claim 1, wherein the step of forming the cap layer over the semiconductor substrate comprises the steps of: forming a stress memorization technique layer on the semiconductor substrate and forming an amorphous carbon layer on the stress memorization technique layer; and the step of removing the cap layer comprises the steps of: removing the amorphous carbon layer and removing the stress memorization technique layer from the semiconductor substrate.

8. The thermal processing method as claimed in claim 1, wherein the first thermal process is a rapid thermal process, and the second thermal process is a millisecond annealing process.

9. The thermal processing method as claimed in claim 1, wherein the first thermal process is a millisecond annealing process, and the second thermal process is a rapid thermal process.

10. The thermal processing method as claimed in claim 1, wherein the first thermal process and the second thermal process are performed simultaneously.

11. The thermal processing method as claimed in claim 1, wherein the semiconductor substrate comprises a first surface and a second surface opposite to the first surface, the rapid thermal process and millisecond annealing process are respectively applied onto the second surface and the first surface.

12. The thermal processing method as claimed in claim 1, wherein the rapid thermal process and millisecond annealing process are respectively applied onto the first surface.

13. The thermal processing method as claimed in claim 1, wherein an amorphorization step is performed before the cap layer is formed.

14. A thermal processing method, comprising:

providing a semiconductor substrate having a metal-oxide-semiconductor transistor formed thereon, wherein the metal-oxide-semiconductor transistor comprises a gate and source and drain regions on two sides of the gate;

implanting dopants into the source and drain region and the gate;

performing a first thermal process;

removing the cap layer after performing the first thermal process; and

performing a second thermal process.

15. The thermal processing method as claimed in claim 14, wherein the cap layer comprises a stress memorization technique layer.

16. The thermal processing method as claimed in claim 15, wherein the stress memorization technique layer comprises a material selected from a group consisting of silicon nitride and silicon oxide.

17. The thermal processing method as claimed in claim 14, wherein the first thermal process is a rapid thermal process, and the second thermal process is a millisecond annealing process.

18. The thermal processing method as claimed in claim 14, wherein an amorphorization step is performed before the cap layer is formed.

19. The thermal processing method as claimed in claim 14, wherein an amorphorization step is an implantation step.