+

US20090272568A1 - Microwave Chip Supporting Structure - Google Patents

Microwave Chip Supporting Structure Download PDF

Info

Publication number
US20090272568A1
US20090272568A1 US12/298,455 US29845506A US2009272568A1 US 20090272568 A1 US20090272568 A1 US 20090272568A1 US 29845506 A US29845506 A US 29845506A US 2009272568 A1 US2009272568 A1 US 2009272568A1
Authority
US
United States
Prior art keywords
laminate layer
microwave
supporting structure
chip
conductors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12/298,455
Inventor
Per Ligander
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of US20090272568A1 publication Critical patent/US20090272568A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/0243—Printed circuits associated with mounted high frequency components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H01L2924/30111—Impedance matching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/183—Components mounted in and supported by recessed areas of the printed circuit board
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10727—Leadless chip carrier [LCC], e.g. chip-modules for cards

Definitions

  • the present invention relates to a microwave chip supporting structure comprising a first microwave laminate layer, with a first side and a second side, the first microwave laminate layer having an outer limit, where further at least one conductor is formed on the first side of the first laminate layer, said conductor extending towards the outer limit of the first laminate layer.
  • a package normally comprises a circuit with etched components on a silicon substrate, constituting a microwave chip.
  • a package normally further comprises a carrier, for example in the form of a microwave laminate, to which the chip is fixed.
  • the chip comprises connecting points, which are connected to connecting points on the laminate by means of bonding, using very thin gold wires.
  • the laminate communicates its connecting points via a plurality of connectors, accessible for a user.
  • the laminate and its chip are normally provided with a protective covering, for example an epoxy resin, a plastic cover shell, or both.
  • BGA Bit Grid Array
  • the connectors are in the form of balls which stands out a certain distance from the package.
  • a circuit board on which the package is to be mounted has a corresponding soldering pattern comprising corresponding soldering pads, matching the footprint—one pad for each ball-shaped connector on the package.
  • An adhesive soldering paste is dispensed on each pad. The package is placed on the circuit board in such a way that the ball-shaped connectors contact the desired corresponding soldering pads. Then the circuit board is gently heated in such a way that the balls and the soldering paste melts, followed by cooling, where the pads and the connectors now are soldered together.
  • solder joint more or less preserves its spherical shape, creating a stand-off between the package and the circuit board. This is, however, disadvantageous at higher frequencies, since this stand-off constitutes an inductance which is difficult to predict with sufficient accuracy.
  • QFN Quad Flat No lead
  • the connectors do not extend out from the outline of the package, but extend at least partly along the lower side of the package.
  • the chip is glued to a laminate, and its connecting points are connected to connecting points on the laminate by means of bonding, using very thin gold wires.
  • the connecting points on the laminate are in turn connected to the connectors of the package by means of via holes that extend from the top of the laminate where its bond-connected connecting point is positioned, to the lower side of the laminate, where the connector is positioned.
  • One other type of package is called flip-chip, and comprises a chip of BGA type, but much more miniaturized.
  • the chip is soldered as an ordinary BGA package to a laminate in order to constitute either a BGA package or a QFN package.
  • a chip is bonded to connectors at a supporting element into which the chip is fastened.
  • the bottom of the chip rests on a conductive foil.
  • the supporting element is lowered into a recess in a circuit board with a ground plane. In the recess, the dielectrica of the circuit board is completely removed, allowing the lowered supporting element to rest on the conducting foil constituting the ground plane of the circuit board. In this way, the ground of the chip is easily connected to the circuit board ground.
  • the connectors of the supporting element are connected to conductors at the circuit board via conductors, soldered or glued in place.
  • the microwave chip supporting structure comprises a second microwave laminate layer, with a first side and a second side, the second laminate layer being fixed to the first laminate layer in such a way that the second side of the second laminate layer faces at least a part of the first side of the first laminate layer.
  • the first laminate layer and/or the second laminate layer comprises at least one recess arranged for receiving a microwave chip intended to be connected to said conductor.
  • the second laminate layer further extends outside the outer limit of the first laminate layer, said conductors continuing on the second side of the second laminate layer without contacting the first laminate layer.
  • FIG. 1 shows a top view of a first embodiment of the present invention
  • FIG. 2 shows a section of the first embodiment of the present invention
  • FIG. 3 shows a section of the first embodiment of the present invention
  • FIG. 4 shows a section of a variety of the first embodiment of the present invention
  • FIG. 5 shows a section of a second embodiment of the present invention
  • FIG. 6 shows a top view of a third embodiment of the present invention.
  • FIG. 7 shows a section of the third embodiment of the present invention.
  • a microwave chip supporting structure 1 is shown.
  • Said supporting structure 1 comprises a first microwave laminate layer 2 , for example a PTFE-based laminate, with a first side 3 and a second side 4 , where a copper ground plane 5 is fixed to the second side 4 .
  • the first laminate layer 2 is limited by a first edge 6 , a second edge 7 , a third edge 8 and a fourth edge 9 , the first laminate layer 2 being essentially rectangular.
  • a first recess 10 is formed in the first laminate layer 2 , where the first recess 10 is formed in such a way that a part of the copper ground plane 5 is forming an accessible surface, against which a microwave chip 11 is fixed by means of, for example, soldering or gluing.
  • a chip 11 is normally constituted by a circuit with etched components on a silicon substrate.
  • the chip 11 has a top side 12 and a bottom side 13 , the bottom side 13 facing the ground plane. In that way, the chip's ground may be directly connected to the ground plane 5 , since the chip's bottom side 13 has at least one ground connection 14 .
  • the chip 11 and the microwave chip supporting structure 1 together form a microwave package.
  • the chip 11 has connections 15 , 16 , 17 , 18 , 19 , 20 on its top side 12 , which connections 15 , 16 , 17 , 18 , 19 , 20 are brought into contact with conductors 21 , 22 , 23 , 24 , 25 , 26 formed on the first side 3 of the first laminate layer 2 by means of corresponding bonding wires 27 , 28 , 29 , 30 , 31 , 32 .
  • the conductors 21 , 22 , 23 , 24 , 25 , 26 extend towards the four edges 6 , 7 , 8 , 9 of the first laminate layer 2 .
  • the supporting structure 1 further comprises a second microwave laminate layer 33 , for example a PTFE-based laminate, with a first side 34 and a second side 35 .
  • the second laminate layer 33 is fixed to the first laminate layer 2 in such a way that the second side 35 of the second laminate layer 33 faces the first side 3 of the first laminate layer 2 .
  • the conductors 21 , 22 , 23 , 24 , 25 , 26 are thus positioned between the first laminate layer 2 and the second laminate layer 33 .
  • a second recess 36 is formed in the second laminate layer 33 , having essentially the same position as the first recess 10 , but being larger in order to allow the bond wires 27 , 28 , 29 , 30 , 31 , 32 to be connected to the conductors 21 , 22 , 23 , 24 , 25 , 26 .
  • the second laminate layer 33 further extends outside the four edges 6 , 7 , 8 , 9 of the first laminate 2 , the conductors 21 , 22 , 23 , 24 , 25 , 26 continuing out from the first laminate layer 2 and continuing on the second side 35 of the second laminate layer 33 .
  • the second laminate 33 layer thus carries the conductors 21 , 22 , 23 , 24 , 25 , 26 out from the first laminate layer 2 .
  • a first PCB (printed circuit board) 37 and a second PCB 38 is shown.
  • the first PCB 37 has a first side 39 and a second side 40
  • the second PCB 38 has a first side 41 and a second side 42 .
  • the first PCB 37 and the second PCB 38 are attached to each other in such a way that the second side 40 of the first PCB 37 and the first side 41 of the second PCB 41 face each other with a PCB ground plane 43 positioned between.
  • a third recess 44 is formed in such a way that a part of the PCB ground plane 43 is forming an accessible surface, against which the supporting structure 1 is fixed by means of, for example, soldering or gluing.
  • the first PCB 37 has a thickness that essentially is the same as the thickness of the first laminate layer 2 , resulting in that the conductors 21 , 22 , 23 , 24 , 25 , 26 , when carried only by the second laminate 33 , will rest on corresponding PCB conductors 45 , 46 .
  • the connections between the conductors 21 , 22 , 23 , 24 , 25 , 26 on the second laminate 33 and the PCB conductors 45 , 46 are achieved by means of for example soldering or gluing.
  • each conducting path is only broken by one solder or glue joint after the respective bond wire 27 , 28 , 29 , 30 , 31 , 32 .
  • the chip 11 is now surrounded by the second laminate layer 33 , which offers a protection for the chip 11 .
  • the second recess 36 formed in the second laminate layer 33 , may be filled with a protective filler substance 47 , such as for example epoxy.
  • a protective filler substance 47 such as for example epoxy.
  • Other examples of the protective filler substance 47 are a gel or a silicone compound.
  • a cover 48 is placed on the first side 34 of the second laminate layer 33 , covering the chip 11 without interfering with any conductors 23 , 26 .
  • the cover 48 may for example be made in plastic, metal or a combination of both.
  • the cover 48 may of course be combined with a protective filler substance as disclosed with reference to FIG. 3 .
  • the shape of the cover 48 may vary, it may for example be arched or be constituted by a flat lid lying directly on the first side 34 of the second microwave laminate layer 33 .
  • the second laminate layer 33 ′ is not provided with a recess, but covers the chip 11 .
  • the second laminate layer 33 ′ carries the conductors 23 , 26 partly into the first recess 10 , enabling them to achieve a direct contact with the chip connections 17 , 20 , thus dispensing with the need for bond wires.
  • the second laminate layer functions as:
  • the second embodiment corresponds to the first embodiment regarding all other features, and may of course be attached to a PCB in the same way as described for the first embodiment.
  • a microwave chip supporting structure 1 ′′ is shown.
  • Said supporting structure 1 ′′ comprises a first microwave laminate layer 49 , for example a PTFE-based laminate, with a first side 50 and a second side 51 , where a copper ground plane 52 is fixed to the second side 51 .
  • the first laminate layer 49 is limited by a first edge 53 , a second edge 54 , a third edge 55 and a fourth edge 56 , the first laminate layer 49 being essentially rectangular.
  • the supporting structure 1 ′′ further comprises a second microwave laminate layer 57 , for example a PTFE-based laminate, with a first side 58 and a second side 59 .
  • the second laminate layer 57 is fixed to the first laminate layer 49 in such a way that the second side 59 of the second laminate layer 57 faces the first side 50 of the first laminate layer 49 .
  • Conductors 60 , 61 , 62 , 63 , 64 , 65 are formed between the first laminate layer 49 and the second laminate layer 57 in a similar way as described for the previous embodiments.
  • the conductors 60 , 61 , 62 , 63 , 64 , 65 are of the type CPW (co-planar waveguide), i.e. the conductors are surrounded by their corresponding ground plane G, separated from the ground plane by a small gap, in a way well known to the person skilled in the art.
  • CPW co-planar waveguide
  • a recess 66 is formed in the second laminate layer 57 , being of such a form that a microwave chip 67 fits in the recess 66 , the chip 67 having a top side 68 and a bottom side 69 .
  • the chip 67 is arranged to rest on the first side 50 of the first laminate layer 49 in such a way that connections 70 , 71 , 72 , 73 , 74 , 75 on the bottom side 69 of the chip 67 are brought into contact with the conductors 60 , 61 , 62 , 63 , 64 , 65 formed on the first side 50 of the first laminate layer 49 .
  • connections between conductors 60 , 61 , 62 , 63 , 64 , 65 and the chip connections 70 , 71 , 72 , 73 , 74 , 75 are in the form of ball connectors B which stand out a certain distance from the package.
  • An adhesive soldering paste is dispensed on an appropriate spot at each conductor 60 , 61 , 62 , 63 , 64 , 65 before the chip 67 is fitted in place.
  • circuit board is gently heated in such a way that the balls B and the soldering paste melts, followed by cooling, where the conductors 60 , 61 , 62 , 63 , 64 , 65 and the chip connections 70 , 71 , 72 , 73 , 74 , 75 now are soldered together.
  • the second laminate layer 57 further extends outside the four edges 53 , 54 , 55 , 56 of the first laminate 49 , the conductors 60 , 61 , 62 , 63 , 64 , 65 continuing out from the first laminate layer 49 and continuing on the second side 59 of the second laminate layer 57 .
  • the second laminate 57 layer thus carries the conductors 60 , 61 , 62 , 63 , 64 , 65 out from the first laminate layer 49 in the same way as described for the previous embodiments.
  • the supporting structure 1 ′′ according to the third embodiment may thus be attached to a PCB in the same way as described for the previous embodiments.
  • the copper ground plane 52 may be used for soldering the supporting structure 1 ′′ to the appropriate PCB, but is not necessary for any electric functions. If the supporting structure 1 ′′ is glued to the appropriate PCB instead, the copper ground plane 52 may be omitted.
  • the ball connectors B of the third embodiment may be exchanged with any type of convenient connection means, for example gluing with conducting glue
  • the main idea of the third embodiment is to present a supporting structure 1 ′′ to which it is possible to connect a chip 67 having both signal and ground connections on the same side of the chip 67 , in this case the bottom side 69 , allowing it to be connected to CPW conductors.
  • the recess 66 may be filled with a protective filler substance and/or covered with a protective cover as described for the first embodiment.
  • the conductors 21 , 22 , 23 , 24 , 25 , 26 ; 60 , 61 , 62 , 63 , 64 , 65 on the first laminate layer 2 ; 49 extend towards at least one of the edges 6 , 7 , 8 , 9 ; 53 , 54 , 55 , 56 of the first laminate layer 2 ; 49 .
  • the second laminate layer 33 , 33 ′; 57 extends a certain distance outside the at least one edge 6 , 7 , 8 , 9 ; 53 , 54 , 55 , 56 of the first laminate layer 2 ; 49 , the conductors 21 , 22 , 23 , 24 , 25 , 26 ; 60 , 61 , 62 , 63 , 64 , 65 continuing out from the first laminate layer 2 ; 49 and continuing on the second side 35 ; 59 of the second laminate layer 33 , 33 ′; 57 .
  • the second laminate layer 33 , 33 ′; 57 preferably only extends outside those edges 6 , 7 , 8 , 9 ; 53 , 54 , 55 , 56 of the first laminate layer 2 ; 49 towards which the conductors 21 , 22 , 23 , 24 , 25 , 26 ; 60 , 61 , 62 , 63 , 64 , 65 of the first laminate layer 2 ; 49 extend.
  • the number of conductors on the first laminate layer 2 ; 49 is at least one.
  • the second laminate layer 33 , 33 ′; 57 thus extends outside at least one edge 6 , 7 , 8 , 9 ; 53 , 54 , 55 , 56 of the first laminate layer 2 ; 49 .
  • the length of the extension, or extensions, should be appropriate to fulfil its connecting function.
  • the widths of the conductors should be adapted to achieve optimal performance, usually by adapting them to the characteristic impedance of the system. Such an adaptation must take into account whether the conductors run as microstrip, i.e. essentially on a supporting dielectric structure without any dielectrica on the other side, or as stripline, i.e. squeezed between two supporting structures. The same is valid if the conductors run in a CPW configuration.
  • the materials may also be chosen conveniently depending on performance and cost requirements, the materials mentioned herein are only mentioned as an example.
  • the laminate layer may for example be formed using ceramics instead of PTFE.
  • the copper ground planes may for example be formed in any suitable conducting material, for example gold.
  • ground planes may furthermore be omitted if suitable, for example if other ground connections are available.
  • the shapes of the materials and the recesses may also vary in any way, the recess may be oval or circular, if that is more convenient due to manufacturing or chip structure.
  • the edges 6 , 7 , 8 , 9 ; 53 , 54 , 55 , 56 may be arranged in any way, the function of the edges is to define an outer limit of the first laminate layer 2 ; 49 .
  • the conductors on the PCB may be in the form of CPW for all embodiments.

Landscapes

  • Microelectronics & Electronic Packaging (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Dispersion Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Waveguides (AREA)
  • Waveguide Connection Structure (AREA)
  • Non-Reversible Transmitting Devices (AREA)
  • Control Of Motors That Do Not Use Commutators (AREA)

Abstract

The present invention relates to a microwave chip supporting structure comprising a first microwave laminate layer, with a first side and a second side, and an outer limit. At least one conductor is formed on said first side, extending towards said outer limit. The microwave chip supporting structure further comprises a second microwave laminate layer, with a first side and a second side, the second side of the second laminate layer being fixed to at least a part of the first side of the first laminate layer. The first laminate layer and/or the second laminate layer comprises at least one recess arranged for receiving a microwave chip intended to be connected to said conductor. The second laminate layer extends outside the outer limit of the first laminate layer, said conductors continuing on the second side of the second laminate layer without contacting the first laminate layer.

Description

    TECHNICAL FIELD
  • The present invention relates to a microwave chip supporting structure comprising a first microwave laminate layer, with a first side and a second side, the first microwave laminate layer having an outer limit, where further at least one conductor is formed on the first side of the first laminate layer, said conductor extending towards the outer limit of the first laminate layer.
    • BACKGROUND
  • In microwave technology, it has become technically feasible to integrate circuits in commercial packages for volume manufacturing and sale. Previously it was necessary to design a layout and mount discrete components on that layout, where a matching procedure often was necessary afterwards in order to tune the circuit. These packaged integrated microwave circuits thus make microwave design easier and cheaper than before.
  • A number of such packages have been developed during the last years. A package normally comprises a circuit with etched components on a silicon substrate, constituting a microwave chip. A package normally further comprises a carrier, for example in the form of a microwave laminate, to which the chip is fixed. The chip comprises connecting points, which are connected to connecting points on the laminate by means of bonding, using very thin gold wires. The laminate communicates its connecting points via a plurality of connectors, accessible for a user. The laminate and its chip are normally provided with a protective covering, for example an epoxy resin, a plastic cover shell, or both.
  • One such type of package is the so-called BGA (Ball Grid Array) package, which is an encapsulated circuit with a more or less complete M×N array of connectors on its lower side, constituting a so-called footprint. The connectors are in the form of balls which stands out a certain distance from the package. A circuit board on which the package is to be mounted has a corresponding soldering pattern comprising corresponding soldering pads, matching the footprint—one pad for each ball-shaped connector on the package. An adhesive soldering paste is dispensed on each pad. The package is placed on the circuit board in such a way that the ball-shaped connectors contact the desired corresponding soldering pads. Then the circuit board is gently heated in such a way that the balls and the soldering paste melts, followed by cooling, where the pads and the connectors now are soldered together.
  • The solder joint more or less preserves its spherical shape, creating a stand-off between the package and the circuit board. This is, however, disadvantageous at higher frequencies, since this stand-off constitutes an inductance which is difficult to predict with sufficient accuracy.
  • Another type of package is called QFN (Quad Flat No lead) which is rectangular with connectors arranged at all four sides. The connectors do not extend out from the outline of the package, but extend at least partly along the lower side of the package. The chip is glued to a laminate, and its connecting points are connected to connecting points on the laminate by means of bonding, using very thin gold wires. The connecting points on the laminate are in turn connected to the connectors of the package by means of via holes that extend from the top of the laminate where its bond-connected connecting point is positioned, to the lower side of the laminate, where the connector is positioned.
  • This configuration is, however, disadvantageous since there are two inductances present for each connection; the bond wire and the via. The higher frequency, the more problematic do these inductances become for designing an accurate, repeatable construction.
  • One other type of package is called flip-chip, and comprises a chip of BGA type, but much more miniaturized. The chip is soldered as an ordinary BGA package to a laminate in order to constitute either a BGA package or a QFN package.
  • If it is a BGA package, there are problems with stand-off distances for the ball connectors at the chip as well as at the lower side of the laminate. There are also vias connecting between connecting points on the upper side of the laminate, and the ball connectors on the lower side of the laminate.
  • If it is a QFN package, there are problems with stand-off distances for the ball connectors at the chip and those vias connecting between connecting points on the upper side of the laminate, and the connectors on the lower side of the laminate.
  • As described in U.S. Pat. No. 6,011,692, which is considered as closest prior art, a chip is bonded to connectors at a supporting element into which the chip is fastened. The bottom of the chip rests on a conductive foil. The supporting element is lowered into a recess in a circuit board with a ground plane. In the recess, the dielectrica of the circuit board is completely removed, allowing the lowered supporting element to rest on the conducting foil constituting the ground plane of the circuit board. In this way, the ground of the chip is easily connected to the circuit board ground. The connectors of the supporting element are connected to conductors at the circuit board via conductors, soldered or glued in place.
  • Although the known device functions in a satisfactory manner, there are certain aspects which can be improved, for example:
      • A glue or solder has to be applied to the conductors on the supporting structure, and may interfere with the chip and/or bond wires.
      • The transmission lines are broken by solder or glue joints at two places after the bond wires
      • When mounting the supporting structure with its chip, the circuit board has to be brought through two runs in a pick-n-place machine and solder dispenser.
      • The bond wires are unprotected if no lid is positioned over the supporting structure
      • Should a lid be placed over the supporting structure, the lid will be in contact with the conductors
    SUMMARY
  • It is an aim of the present invention to present a microwave chip supporting structure adapted for microwave frequencies, which microwave package overcomes the above disadvantages.
  • This aim is achieved by means of a microwave chip supporting structure as mentioned in the introduction, where furthermore the microwave chip supporting structure comprises a second microwave laminate layer, with a first side and a second side, the second laminate layer being fixed to the first laminate layer in such a way that the second side of the second laminate layer faces at least a part of the first side of the first laminate layer. The first laminate layer and/or the second laminate layer comprises at least one recess arranged for receiving a microwave chip intended to be connected to said conductor. The second laminate layer further extends outside the outer limit of the first laminate layer, said conductors continuing on the second side of the second laminate layer without contacting the first laminate layer.
  • Preferred embodiments are disclosed in the dependent claims.
  • Several advantages are achieved by means of the present invention, for example:
      • no glue or solder has to be applied to the conductors on the supporting structure,
      • the transmission lines are unbroken, and
      • only one run in a pick-n-place machine and solder dispenser is necessary.
    BRIEF DESCRIPTION OF THE DRAWINGS
  • The present invention will now be described more in detail with reference to the appended drawing, where
  • FIG. 1 shows a top view of a first embodiment of the present invention;
  • FIG. 2 shows a section of the first embodiment of the present invention;
  • FIG. 3 shows a section of the first embodiment of the present invention;
  • FIG. 4 shows a section of a variety of the first embodiment of the present invention;
  • FIG. 5 shows a section of a second embodiment of the present invention;
  • FIG. 6 shows a top view of a third embodiment of the present invention; and
  • FIG. 7 shows a section of the third embodiment of the present invention.
    •  DETAILED DESCRIPTION
  • In FIG. 1 and FIG. 2, illustrating a first embodiment, a microwave chip supporting structure 1 is shown. Said supporting structure 1 comprises a first microwave laminate layer 2, for example a PTFE-based laminate, with a first side 3 and a second side 4, where a copper ground plane 5 is fixed to the second side 4. The first laminate layer 2 is limited by a first edge 6, a second edge 7, a third edge 8 and a fourth edge 9, the first laminate layer 2 being essentially rectangular. A first recess 10 is formed in the first laminate layer 2, where the first recess 10 is formed in such a way that a part of the copper ground plane 5 is forming an accessible surface, against which a microwave chip 11 is fixed by means of, for example, soldering or gluing. Such a chip 11 is normally constituted by a circuit with etched components on a silicon substrate. The chip 11 has a top side 12 and a bottom side 13, the bottom side 13 facing the ground plane. In that way, the chip's ground may be directly connected to the ground plane 5, since the chip's bottom side 13 has at least one ground connection 14. The chip 11 and the microwave chip supporting structure 1 together form a microwave package.
  • The chip 11 has connections 15, 16, 17, 18, 19, 20 on its top side 12, which connections 15, 16, 17, 18, 19, 20 are brought into contact with conductors 21, 22, 23, 24, 25, 26 formed on the first side 3 of the first laminate layer 2 by means of corresponding bonding wires 27, 28, 29, 30, 31, 32. The conductors 21, 22, 23, 24, 25, 26 extend towards the four edges 6, 7, 8, 9 of the first laminate layer 2.
  • According to the present invention, the supporting structure 1 further comprises a second microwave laminate layer 33, for example a PTFE-based laminate, with a first side 34 and a second side 35. The second laminate layer 33 is fixed to the first laminate layer 2 in such a way that the second side 35 of the second laminate layer 33 faces the first side 3 of the first laminate layer 2. The conductors 21, 22, 23, 24, 25, 26 are thus positioned between the first laminate layer 2 and the second laminate layer 33. A second recess 36 is formed in the second laminate layer 33, having essentially the same position as the first recess 10, but being larger in order to allow the bond wires 27, 28, 29, 30, 31, 32 to be connected to the conductors 21, 22, 23, 24, 25, 26.
  • The second laminate layer 33 further extends outside the four edges 6, 7, 8, 9 of the first laminate 2, the conductors 21, 22, 23, 24, 25, 26 continuing out from the first laminate layer 2 and continuing on the second side 35 of the second laminate layer 33. The second laminate 33 layer thus carries the conductors 21, 22, 23, 24, 25, 26 out from the first laminate layer 2.
  • As shown in FIG. 3, a first PCB (printed circuit board) 37 and a second PCB 38 is shown. The first PCB 37 has a first side 39 and a second side 40, and the second PCB 38 has a first side 41 and a second side 42. The first PCB 37 and the second PCB 38 are attached to each other in such a way that the second side 40 of the first PCB 37 and the first side 41 of the second PCB 41 face each other with a PCB ground plane 43 positioned between. In the first PCB 37, a third recess 44 is formed in such a way that a part of the PCB ground plane 43 is forming an accessible surface, against which the supporting structure 1 is fixed by means of, for example, soldering or gluing.
  • The first PCB 37 has a thickness that essentially is the same as the thickness of the first laminate layer 2, resulting in that the conductors 21, 22, 23, 24, 25, 26, when carried only by the second laminate 33, will rest on corresponding PCB conductors 45, 46. The connections between the conductors 21, 22, 23, 24, 25, 26 on the second laminate 33 and the PCB conductors 45, 46 are achieved by means of for example soldering or gluing.
  • In this way, each conducting path is only broken by one solder or glue joint after the respective bond wire 27, 28, 29, 30, 31, 32.
  • The chip 11 is now surrounded by the second laminate layer 33, which offers a protection for the chip 11. In order to achieve a more rigid protection of the chip, the second recess 36, formed in the second laminate layer 33, may be filled with a protective filler substance 47, such as for example epoxy. Other examples of the protective filler substance 47 are a gel or a silicone compound.
  • According to a variety of the first embodiment, as shown in FIG. 4, a cover 48 is placed on the first side 34 of the second laminate layer 33, covering the chip 11 without interfering with any conductors 23, 26. The cover 48 may for example be made in plastic, metal or a combination of both. The cover 48 may of course be combined with a protective filler substance as disclosed with reference to FIG. 3. The shape of the cover 48 may vary, it may for example be arched or be constituted by a flat lid lying directly on the first side 34 of the second microwave laminate layer 33.
  • According to a second embodiment of the present invention, with reference to FIG. 5, showing a microwave chip supporting structure 1′, the second laminate layer 33′ is not provided with a recess, but covers the chip 11. In this second embodiment, there are no bond wires, but the second laminate layer 33′ carries the conductors 23, 26 partly into the first recess 10, enabling them to achieve a direct contact with the chip connections 17, 20, thus dispensing with the need for bond wires. In this way, the second laminate layer functions as:
      • a first connecting means, between the chip connections and the conductors on the first side of the first laminate,
      • a second connecting means, between the conductors on the first side of the first laminate and the PCB connections, and
      • a cover for the chip.
  • The second embodiment corresponds to the first embodiment regarding all other features, and may of course be attached to a PCB in the same way as described for the first embodiment.
  • In FIG. 6 and FIG. 7, illustrating a third embodiment, a microwave chip supporting structure 1″ is shown. Said supporting structure 1″ comprises a first microwave laminate layer 49, for example a PTFE-based laminate, with a first side 50 and a second side 51, where a copper ground plane 52 is fixed to the second side 51. The first laminate layer 49 is limited by a first edge 53, a second edge 54, a third edge 55 and a fourth edge 56, the first laminate layer 49 being essentially rectangular.
  • The supporting structure 1″ further comprises a second microwave laminate layer 57, for example a PTFE-based laminate, with a first side 58 and a second side 59. The second laminate layer 57 is fixed to the first laminate layer 49 in such a way that the second side 59 of the second laminate layer 57 faces the first side 50 of the first laminate layer 49. Conductors 60, 61, 62, 63, 64, 65 are formed between the first laminate layer 49 and the second laminate layer 57 in a similar way as described for the previous embodiments. The conductors 60, 61, 62, 63, 64, 65 are of the type CPW (co-planar waveguide), i.e. the conductors are surrounded by their corresponding ground plane G, separated from the ground plane by a small gap, in a way well known to the person skilled in the art.
  • A recess 66 is formed in the second laminate layer 57, being of such a form that a microwave chip 67 fits in the recess 66, the chip 67 having a top side 68 and a bottom side 69. The chip 67 is arranged to rest on the first side 50 of the first laminate layer 49 in such a way that connections 70, 71, 72, 73, 74, 75 on the bottom side 69 of the chip 67 are brought into contact with the conductors 60, 61, 62, 63, 64, 65 formed on the first side 50 of the first laminate layer 49.
  • The connections between conductors 60, 61, 62, 63, 64, 65 and the chip connections 70, 71, 72, 73, 74, 75 are in the form of ball connectors B which stand out a certain distance from the package. An adhesive soldering paste is dispensed on an appropriate spot at each conductor 60, 61, 62, 63, 64, 65 before the chip 67 is fitted in place. Then the circuit board is gently heated in such a way that the balls B and the soldering paste melts, followed by cooling, where the conductors 60, 61, 62, 63, 64, 65 and the chip connections 70, 71, 72, 73, 74, 75 now are soldered together.
  • The second laminate layer 57 further extends outside the four edges 53, 54, 55, 56 of the first laminate 49, the conductors 60, 61, 62, 63, 64, 65 continuing out from the first laminate layer 49 and continuing on the second side 59 of the second laminate layer 57. The second laminate 57 layer thus carries the conductors 60, 61, 62, 63, 64, 65 out from the first laminate layer 49 in the same way as described for the previous embodiments.
  • The supporting structure 1″ according to the third embodiment may thus be attached to a PCB in the same way as described for the previous embodiments. The copper ground plane 52 may be used for soldering the supporting structure 1″ to the appropriate PCB, but is not necessary for any electric functions. If the supporting structure 1″ is glued to the appropriate PCB instead, the copper ground plane 52 may be omitted.
  • The ball connectors B of the third embodiment may be exchanged with any type of convenient connection means, for example gluing with conducting glue, the main idea of the third embodiment is to present a supporting structure 1″ to which it is possible to connect a chip 67 having both signal and ground connections on the same side of the chip 67, in this case the bottom side 69, allowing it to be connected to CPW conductors.
  • The recess 66 may be filled with a protective filler substance and/or covered with a protective cover as described for the first embodiment.
  • The invention is not limited to the embodiments described, but may vary freely within the scope of the appended claims. For example, the conductors 21, 22, 23, 24, 25, 26; 60, 61, 62, 63, 64, 65 on the first laminate layer 2; 49 extend towards at least one of the edges 6, 7, 8, 9; 53, 54, 55, 56 of the first laminate layer 2; 49. The second laminate layer 33, 33′; 57 extends a certain distance outside the at least one edge 6, 7, 8, 9; 53, 54, 55, 56 of the first laminate layer 2; 49, the conductors 21, 22, 23, 24, 25, 26; 60, 61, 62, 63, 64, 65 continuing out from the first laminate layer 2; 49 and continuing on the second side 35; 59 of the second laminate layer 33, 33′; 57. The second laminate layer 33, 33′; 57 preferably only extends outside those edges 6, 7, 8, 9; 53, 54, 55, 56 of the first laminate layer 2; 49 towards which the conductors 21, 22, 23, 24, 25, 26; 60, 61, 62, 63, 64, 65 of the first laminate layer 2; 49 extend.
  • The number of conductors on the first laminate layer 2; 49 is at least one.
  • The second laminate layer 33, 33′; 57 thus extends outside at least one edge 6, 7, 8, 9; 53, 54, 55, 56 of the first laminate layer 2; 49. The length of the extension, or extensions, should be appropriate to fulfil its connecting function.
  • The widths of the conductors should be adapted to achieve optimal performance, usually by adapting them to the characteristic impedance of the system. Such an adaptation must take into account whether the conductors run as microstrip, i.e. essentially on a supporting dielectric structure without any dielectrica on the other side, or as stripline, i.e. squeezed between two supporting structures. The same is valid if the conductors run in a CPW configuration.
  • The materials may also be chosen conveniently depending on performance and cost requirements, the materials mentioned herein are only mentioned as an example. The laminate layer may for example be formed using ceramics instead of PTFE. Furthermore, the copper ground planes may for example be formed in any suitable conducting material, for example gold.
  • The ground planes may furthermore be omitted if suitable, for example if other ground connections are available.
  • The shapes of the materials and the recesses may also vary in any way, the recess may be oval or circular, if that is more convenient due to manufacturing or chip structure. The edges 6, 7, 8, 9; 53, 54, 55, 56 may be arranged in any way, the function of the edges is to define an outer limit of the first laminate layer 2; 49.
  • The conductors on the PCB may be in the form of CPW for all embodiments.

Claims (17)

1-15. (canceled)
16. A microwave chip supporting structure comprising:
a first microwave laminate layer having a first side and a second side, the first microwave laminate layer having an outer limit where further at least one conductor is formed on the first side of the first laminate layer, said conductor extending towards the outer limit of the first laminate layer;
a second microwave laminate layer with a first side and a second side, the second laminate layer being fixed to the first laminate layer in such a way that the second side of the second laminate layer faces at least a part of the first side of the first laminate layer;
the first laminate layer and/or the second laminate layer having at least one recess arranged for receiving a microwave chip intended to be coupled to said conductor, where the second laminate layer further extends outside the outer limit of the first laminate layer, said conductors continuing on the second side of the second laminate layer without contacting the first laminate layer.
17. The microwave chip supporting structure according to claim 16, further comprising the first laminate layer has a first recess, into which the microwave chip is inserted, the microwave chip having a top side and a bottom side, the bottom side facing an electrically conducting ground plane that is fixed to the second side of the first laminate layer, and the top side being equipped with chip connections, which chip connections are brought into contact with said conductors.
18. The microwave chip supporting structure according to claim 17, characterized in that said bottom side has at least one ground connection which is electrically connected to said ground plane.
19. The microwave chip supporting structure according to claim 17 wherein the second laminate layer has a second recess, having essentially the same position as the first recess, but being larger, allowing the chip connections to be brought into contact with said conductors by means of bond wires.
20. The microwave chip supporting structure according to claim 19, wherein the second recess is filled with a protective filler substance.
21. The microwave chip supporting structure according to claim 19 wherein a cover is placed on the first side of the second laminate layer, covering the chip.
22. The microwave chip supporting structure according to claim 17, wherein the second laminate layer covers the microwave chip, carrying the conductors partly into the first recess, enabling them to achieve a direct contact with the chip connections.
23. The microwave chip supporting structure according to claim 17 wherein the first laminate layer carries the conductors partly into the first recess, enabling them to achieve a direct contact with the chip connections.
24. The microwave chip supporting structure according to claim 16, wherein the second laminate layer has a recess arranged to receive the microwave chip, the microwave chip having a top side and a bottom side, where the chip is arranged to rest on the first side of the first laminate layer in such a way that connections on the bottom side of the chip are brought into contact with the conductors formed on the first side of the first laminate layer.
25. The microwave chip supporting structure according to claim 24, wherein the connections between conductors and the chip connections are in the form of ball connectors.
26. The microwave chip supporting structure according to claim 24, wherein the recess is filled with a protective filler substance.
27. The microwave chip supporting structure according to claim 24, wherein a cover is placed on the first side of the second laminate layer covering the microwave chip.
28. The microwave chip supporting structure according to claim 16, arranged for being placed in a recess formed in a first Printed Circuit Board (PCB), the first PCB being attached to a second PCB in such a way that a second side of the first PCB and a first side of the second PCB face each other with a PCB ground plane positioned between them.
29. The microwave chip supporting structure according to claim 28, wherein a part of the PCB ground plane is forming an accessible surface via the recess, against which the supporting structure may be fixed.
30. The microwave chip supporting structure according to claim 28, wherein the first PCB has a thickness that essentially is the same as the thickness of the first laminate layer, resulting in that said conductors, when carried only by the second laminate layer, will rest on corresponding PCB conductors, enabling an electrical connection between said conductors on the second laminate and the PCB conductors.
31. The microwave chip supporting structure according to claim 28, wherein the PCB conductors are in the form of a Co-Planar Waveguide.
US12/298,455 2006-04-28 2006-04-28 Microwave Chip Supporting Structure Abandoned US20090272568A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/EP2006/003997 WO2007124769A1 (en) 2006-04-28 2006-04-28 A microwave chip supporting structure

Publications (1)

Publication Number Publication Date
US20090272568A1 true US20090272568A1 (en) 2009-11-05

Family

ID=36959433

Family Applications (2)

Application Number Title Priority Date Filing Date
US12/298,455 Abandoned US20090272568A1 (en) 2006-04-28 2006-04-28 Microwave Chip Supporting Structure
US12/298,468 Expired - Fee Related US8253028B2 (en) 2006-04-28 2007-04-27 Microwave chip supporting structure

Family Applications After (1)

Application Number Title Priority Date Filing Date
US12/298,468 Expired - Fee Related US8253028B2 (en) 2006-04-28 2007-04-27 Microwave chip supporting structure

Country Status (6)

Country Link
US (2) US20090272568A1 (en)
EP (2) EP2013905A1 (en)
CN (2) CN101427366A (en)
AT (1) ATE483250T1 (en)
DE (1) DE602007009513D1 (en)
WO (2) WO2007124769A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090154124A1 (en) * 2006-04-28 2009-06-18 Per Ligander Microwave chip supporting structure

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20090129791A (en) * 2008-06-13 2009-12-17 가부시키가이샤 교토 소프트웨어 리서치 Multi-value flash memory
CN102714927B (en) * 2009-12-31 2015-03-11 华为技术有限公司 A microwave unit and method therefore
US10347558B2 (en) 2015-08-31 2019-07-09 Intel IP Corporation Low thermal resistance hanging die package
CN111229340B (en) * 2020-01-17 2021-11-23 上海新微技术研发中心有限公司 Method for manufacturing grating waveguide microfluid chip

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5206712A (en) * 1990-04-05 1993-04-27 General Electric Company Building block approach to microwave modules
US20010009499A1 (en) * 1999-06-22 2001-07-26 Carlson Russell W. Low impedance hinge for notebook computer
US20010028072A1 (en) * 1999-09-17 2001-10-11 Takashi Aoki Semiconductor pressure sensor device having sensor chip covered with protective member
US20030150641A1 (en) * 2002-02-14 2003-08-14 Noyan Kinayman Multilayer package for a semiconductor device
US20070026567A1 (en) * 2005-06-01 2007-02-01 Gottfried Beer Semiconductor module comprising components for microwave engineering in plastic casing and method for the production thereof
US20090154124A1 (en) * 2006-04-28 2009-06-18 Per Ligander Microwave chip supporting structure

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5542175A (en) * 1994-12-20 1996-08-06 International Business Machines Corporation Method of laminating and circuitizing substrates having openings therein
KR100201384B1 (en) * 1995-10-19 1999-06-15 구본준 Semiconductor package having a transparency lid
AU2155697A (en) * 1996-03-14 1997-10-01 Pav Card Gmbh Smart card, connection arrangement and method of producing smart card

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5206712A (en) * 1990-04-05 1993-04-27 General Electric Company Building block approach to microwave modules
US20010009499A1 (en) * 1999-06-22 2001-07-26 Carlson Russell W. Low impedance hinge for notebook computer
US20010028072A1 (en) * 1999-09-17 2001-10-11 Takashi Aoki Semiconductor pressure sensor device having sensor chip covered with protective member
US20030150641A1 (en) * 2002-02-14 2003-08-14 Noyan Kinayman Multilayer package for a semiconductor device
US20070026567A1 (en) * 2005-06-01 2007-02-01 Gottfried Beer Semiconductor module comprising components for microwave engineering in plastic casing and method for the production thereof
US20090154124A1 (en) * 2006-04-28 2009-06-18 Per Ligander Microwave chip supporting structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090154124A1 (en) * 2006-04-28 2009-06-18 Per Ligander Microwave chip supporting structure
US8253028B2 (en) * 2006-04-28 2012-08-28 Telefonaktiebolaget L M Ericsson (Publ) Microwave chip supporting structure

Also Published As

Publication number Publication date
US20090154124A1 (en) 2009-06-18
CN101432871A (en) 2009-05-13
DE602007009513D1 (en) 2010-11-11
WO2007125094A1 (en) 2007-11-08
EP2013906A1 (en) 2009-01-14
EP2013905A1 (en) 2009-01-14
CN101432871B (en) 2015-07-08
US8253028B2 (en) 2012-08-28
EP2013906B1 (en) 2010-09-29
WO2007124769A1 (en) 2007-11-08
CN101427366A (en) 2009-05-06
ATE483250T1 (en) 2010-10-15

Similar Documents

Publication Publication Date Title
JP5443594B2 (en) Chip to waveguide port converter
US6028358A (en) Package for a semiconductor device and a semiconductor device
US6153928A (en) Substrate for semiconductor package, fabrication method thereof, and stacked-type semiconductor package using the substrate
JP5231382B2 (en) Semiconductor device
US8982577B1 (en) Electronic component package having bleed channel structure and method
US6833614B2 (en) Semiconductor package and semiconductor device
US7547965B2 (en) Package and package module of the package
KR102607649B1 (en) semiconductor packages
JP2002510148A (en) Semiconductor component having a plurality of substrate layers and at least one semiconductor chip and a method for manufacturing the semiconductor component
US8253028B2 (en) Microwave chip supporting structure
US8222725B2 (en) Metal can impedance control structure
US20060202335A1 (en) Tape ball grid array package with electromagnetic interference protection and method for fabricating the package
US6998292B2 (en) Apparatus and method for inter-chip or chip-to-substrate connection with a sub-carrier
JP4171218B2 (en) Surface mount module
JP4883010B2 (en) Electronic component package
US6888227B2 (en) Apparatus for routing signals
JP3998562B2 (en) Semiconductor device
CN100395918C (en) Antenna and radiating metal sheet device and manufacturing method
JPH11163217A (en) Semiconductor device
JPH0936617A (en) High frequency module
KR100369501B1 (en) Semiconductor Package
JP2021034453A (en) Package board and electronic equipment
JP2001332652A (en) Semiconductor package and manufacturing method thereof
GB2433832A (en) Die package
JP2005079503A (en) Plastic package

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION

点击 这是indexloc提供的php浏览器服务，不要输入任何密码和下载