+

US20090170348A1 - Patch panel and patch panel connector - Google Patents

Patch panel and patch panel connector Download PDF

Info

Publication number
US20090170348A1
US20090170348A1 US12/023,008 US2300808A US2009170348A1 US 20090170348 A1 US20090170348 A1 US 20090170348A1 US 2300808 A US2300808 A US 2300808A US 2009170348 A1 US2009170348 A1 US 2009170348A1
Authority
US
United States
Prior art keywords
signal terminals
twenty
pairs
patch panel
connect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US12/023,008
Other versions
US7677898B2 (en
Inventor
Yi Rui
Ai-Yu Pan
Jian-She Shen
Mei Huang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hongfujin Precision Electronics Tianjin Co Ltd
Original Assignee
Hongfujin Precision Industry Shenzhen Co Ltd
Hon Hai Precision Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hongfujin Precision Industry Shenzhen Co Ltd, Hon Hai Precision Industry Co Ltd filed Critical Hongfujin Precision Industry Shenzhen Co Ltd
Assigned to HON HAI PRECISION INDUSTRY CO., LTD., HONG FU JIN PRECISION INDUSTRY (SHENZHEN) CO., LTD. reassignment HON HAI PRECISION INDUSTRY CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HUANG, MEI, PAN, AI-YU, RUI, YI, SHEN, JIAN-SHE
Publication of US20090170348A1 publication Critical patent/US20090170348A1/en
Application granted granted Critical
Publication of US7677898B2 publication Critical patent/US7677898B2/en
Assigned to HONGFUJIN PRECISION ELECTRONICS(TIANJIN)CO.,LTD. reassignment HONGFUJIN PRECISION ELECTRONICS(TIANJIN)CO.,LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HON HAI PRECISION INDUSTRY CO., LTD., HONG FU JIN PRECISION INDUSTRY (SHENZHEN) CO., LTD.
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/222—Completing of printed circuits by adding non-printed jumper connections
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0286—Programmable, customizable or modifiable circuits
    • H05K1/0295—Programmable, customizable or modifiable circuits adapted for choosing between different types or different locations of mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/04—Assemblies of printed circuits
    • H05K2201/044—Details of backplane or midplane for mounting orthogonal PCBs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09954—More mounting possibilities, e.g. on same place of PCB, or by using different sets of edge pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10189—Non-printed connector

Definitions

  • the present invention relates to a patch panel and mating patch panel connector.
  • a graphic and memory controller hub is mounted on a motherboard to connect to a peripheral component interconnect express X16 (PCI-E X16) slot for supporting a PCI-E graphic card or to connect to a high definition multimedia interface (HDMI) for supporting a monitor.
  • the GMCH is controlled by a special chipset to selectively connect to the PCI-E X16 slot and the HDMI.
  • the GMCH is connected to the HDMI via the chipset, users cannot use another expansion card such as a PCI-E X1 card mounted in the PCI-E X16 slot because the chipset can not recognize the PCI-E X1 card at this time.
  • An exemplary patch panel includes a printed circuit board having first to twenty-sixth signal terminals defined on a first side thereof.
  • the first to the thirteenth signal terminals are connected to the twentieth, twenty-fifth, twenty-sixth, twenty-third, twenty-fourth, eighteenth, nineteenth, seventeenth, sixteenth, fifteenth, fourteenth, twenty-first, and twenty-second signal terminals respectively.
  • the second to the fifth signal terminals are arranged to connect to two pairs of PCI-E X1 differential signal terminals of an ICH
  • the first signal terminal is arranged to connect to an interface terminal of an HDMI
  • the sixth to the thirteenth signal terminals are arranged to connect four pairs of differential signal terminals of the HDMI
  • the fourth to the nineteenth, twenty-first, and twenty-second signal terminals are arranged to connect to four pairs of differential signal terminals of a GMCH
  • the twentieth signal terminal is arranged to connect to one of another differential signal terminal of the GMCH
  • the twenty-third to the twenty-sixth signal terminals are connected to two pairs of differential signal terminals of a PCI-E X16 slot.
  • a patch panel connector mating with the patch panel includes first to thirty-seventh terminals, wherein the first terminal is arranged to connect to an interface terminal of an HDMI, the second to the fifth terminals are arranged to connect to two pairs of PCI-E X1 differential signal terminals of an ICH, the sixth to the thirteenth terminals are arranged to connect to four pairs of differential signal terminals of the HDMI, the fourteenth to the twenty-fifth terminals are arranged to connect to six pairs of differential signal terminals of a GMCH, and the twenty-sixth to the thirty-seventh terminals are arranged to connect to six pairs of differential signal terminals of a PCI-E X16 slot.
  • FIG. 1 is a schematic diagram of a patch panel connector in accordance with an embodiment of the present invention
  • FIG. 2 is a circuit diagram of a first side of a patch panel in accordance with an embodiment of the present invention.
  • FIG. 3 is a circuit diagram of a second side of the patch panel of FIG. 2 .
  • a patch panel connector 10 in accordance with an embodiment of the present invention comprises sixty-four terminals A 1 ⁇ A 32 and B 1 ⁇ B 32 .
  • the terminal A 1 is connected to an interface terminal of a high definition multimedia interface (HDMI).
  • the terminals A 3 , A 4 , A 6 , and A 7 are connected to two pairs of PCI-E X1 differential signal terminals HIS_N 4 /HIS_P 4 and HSO_N 4 /HSO_P 4 of an I/O controller hub (ICH) respectively.
  • ICH I/O controller hub
  • the terminals A 9 , A 10 , A 13 , A 14 , A 16 , A 17 , A 19 , and A 20 are connected to four pairs of differential signal terminals PROTC_LANE 0 _DN/PROTC_LANE 0 _DP, PROTC_LANE 1 _DN/PROTC_LANE 1 _DP, PROTC_LANE 2 _DN/PROTC_LANE 2 _DP, and PROTC_CLK_DN/PROTC_CLK_DP of the HDMI respectively.
  • the terminals A 22 , A 23 , A 25 , A 26 , A 29 , A 30 , B 23 , B 24 , B 26 , B 27 , B 30 , and B 31 are connected to six pairs of differential signal terminals EXP_TXP 0 /EXP_TXN 0 , EXP_RXP 0 /EXP_RXN 0 , EXP_TXP 1 /EXP_TXN 1 , EXP_TXP 3 /EXP_TXN 3 , EXP_RXP 3 /EXP_RXN 3 , and EXP_TXP 2 /EXP_TXN 2 of a graphic and memory controller hub (GMCH) respectively.
  • GMCH graphic and memory controller hub
  • the terminals B 2 , B 3 , B 5 , B 6 , B 8 , B 9 , B 13 , B 14 , B 16 , B 17 , B 19 , and B 20 are connected to six pairs of differential signal terminals EXP_RXP 0 /EXP_RXN 0 , EXP_TXP 0 /EXP_TXN 0 , EXP_TXP 1 /EXP_TXN 1 , EXP_TXP 2 /EXP_TXN 2 , EXP_TXP 3 /EXP_TXN 3 , and EXP_RXP 3 /EXP_RXN 3 of a peripheral component interconnect express X16 (PCI-E X16) slot respectively.
  • the other terminals are grounded.
  • a patch panel in accordance with an embodiment of the present invention comprises a printed circuit board defining sixty-four signal terminals C 1 ⁇ C 32 and D 1 ⁇ D 32 on a first side 20 thereof.
  • the signal terminals C 22 , C 23 , C 25 , C 26 , C 29 , C 30 , D 23 , D 24 , D 26 , D 27 , D 30 , and D 31 are connected to the signal terminals D 5 , D 6 , D 2 , D 3 , D 8 , D 9 , D 16 , D 17 , D 19 , D 20 , D 13 , and D 14 respectively.
  • the signal terminals C 1 ⁇ C 32 and D 1 ⁇ D 32 of the patch panel are connected to the terminals A 1 ⁇ A 32 and B 1 ⁇ B 32 of the patch panel connector 10 respectively when the first side 20 of the patch panel is mounted on the patch panel connector 10 .
  • the differential signal terminals EXP_TXP 0 , EXP_TXN 0 , EXP_RXP 0 , EXP_RXN 0 , EXP_TXP 1 , EXP_TXN 1 , EXP_TXP 3 , EXP_TXN 3 , EXP_RXP 3 , EXP_RXN 3 , EXP_TXP 2 , and EXP_TXN 2 of the GMCH are connected to the differential signal terminals EXP_TXP 0 , EXP_TXN 0 , EXP_RXP 0 , EXP_RXN 0 , EXP_TXP 1 , EXP_TXN 1 , EXP_TXP 3 , EXP_TXN 3 , EXP_RXP 3 , EXP_RXN 3 , EXP_TXP 2
  • a second side 30 of the patch panel defines sixty-four signal terminals E 1 ⁇ E 32 and F 1 ⁇ F 32 , wherein the signal terminals E 1 , E 3 , E 4 , E 6 , E 7 , E 9 , E 10 , E 13 , E 14 , E 16 , E 17 , E 19 , and E 20 are connected to the signal terminals F 26 , F 3 , F 2 , F 6 , F 5 , F 31 , F 30 , E 30 , E 29 , E 23 , E 22 , F 24 , and F 23 respectively.
  • the signal terminals E 1 ⁇ E 32 and F 1 ⁇ F 32 of the patch panel are connected to the terminals A 1 ⁇ A 32 and B 1 ⁇ B 32 of the patch panel connector 10 respectively when the first side 20 of the patch panel is mounted on the patch panel connector 10 .
  • Operators can selectively mount one of the first side 20 and the second side 30 of the patch panel on the motherboard via the patch panel connector 10 for selectively connecting the GMCH to the PCI-E X16 slot, or connecting the GMCH to the HDMI and concurrently connecting the ICH to the PCI-E X16 to support a PCI-E X1 card.

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Dc Digital Transmission (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)

Abstract

An exemplary patch panel includes a printed circuit board having a plurality of signal terminals for connecting to two pairs of peripheral component interconnect express (PCI-E) X1 differential signal terminals of an I/O controller hub (ICH), an interface terminal of a high definition multimedia interface (HDMI), four pairs of differential signal terminals of the HDMI, four pairs of differential signal terminals of a graphic and memory controller hub (GMCH), one of another differential signal terminal of the GMCH, and two pairs of differential signal terminals of a PCI-E X16 slot. Therefore, the ICH is connected to the PCI-E X16 slot via the patch panel for supporting a PCI-E X1 card while the GMCH is connected to the HDMI via the patch panel. A patch panel connector is provided to mount the patch panel on a motherboard.

Description

    BACKGROUND
  • 1. Field of the Invention
  • The present invention relates to a patch panel and mating patch panel connector.
  • 2. Description of Related Art
  • Conventionally, a graphic and memory controller hub (GMCH) is mounted on a motherboard to connect to a peripheral component interconnect express X16 (PCI-E X16) slot for supporting a PCI-E graphic card or to connect to a high definition multimedia interface (HDMI) for supporting a monitor. The GMCH is controlled by a special chipset to selectively connect to the PCI-E X16 slot and the HDMI. However, when the GMCH is connected to the HDMI via the chipset, users cannot use another expansion card such as a PCI-E X1 card mounted in the PCI-E X16 slot because the chipset can not recognize the PCI-E X1 card at this time.
  • What is needed is a patch panel which can be mounted on the motherboard via a patch panel connecter to support the HDMI and the PCI-E X1 expansion card concurrently.
    • SUMMARY
  • An exemplary patch panel includes a printed circuit board having first to twenty-sixth signal terminals defined on a first side thereof. The first to the thirteenth signal terminals are connected to the twentieth, twenty-fifth, twenty-sixth, twenty-third, twenty-fourth, eighteenth, nineteenth, seventeenth, sixteenth, fifteenth, fourteenth, twenty-first, and twenty-second signal terminals respectively. The second to the fifth signal terminals are arranged to connect to two pairs of PCI-E X1 differential signal terminals of an ICH, the first signal terminal is arranged to connect to an interface terminal of an HDMI, the sixth to the thirteenth signal terminals are arranged to connect four pairs of differential signal terminals of the HDMI, the fourth to the nineteenth, twenty-first, and twenty-second signal terminals are arranged to connect to four pairs of differential signal terminals of a GMCH, the twentieth signal terminal is arranged to connect to one of another differential signal terminal of the GMCH, and the twenty-third to the twenty-sixth signal terminals are connected to two pairs of differential signal terminals of a PCI-E X16 slot.
  • A patch panel connector mating with the patch panel includes first to thirty-seventh terminals, wherein the first terminal is arranged to connect to an interface terminal of an HDMI, the second to the fifth terminals are arranged to connect to two pairs of PCI-E X1 differential signal terminals of an ICH, the sixth to the thirteenth terminals are arranged to connect to four pairs of differential signal terminals of the HDMI, the fourteenth to the twenty-fifth terminals are arranged to connect to six pairs of differential signal terminals of a GMCH, and the twenty-sixth to the thirty-seventh terminals are arranged to connect to six pairs of differential signal terminals of a PCI-E X16 slot.
  • Other advantages and novel features of the present invention will become more apparent from the following detailed description of preferred embodiment when taken in conjunction with the accompanying drawings, in which:
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a schematic diagram of a patch panel connector in accordance with an embodiment of the present invention;
  • FIG. 2 is a circuit diagram of a first side of a patch panel in accordance with an embodiment of the present invention; and
  • FIG. 3 is a circuit diagram of a second side of the patch panel of FIG. 2.
    •  DETAILED DESCRIPTION
  • Referring to FIG. 1, a patch panel connector 10 in accordance with an embodiment of the present invention comprises sixty-four terminals A1˜A32 and B1˜B32. The terminal A1 is connected to an interface terminal of a high definition multimedia interface (HDMI). The terminals A3, A4, A6, and A7 are connected to two pairs of PCI-E X1 differential signal terminals HIS_N4/HIS_P4 and HSO_N4/HSO_P4 of an I/O controller hub (ICH) respectively. The terminals A9, A10, A13, A14, A16, A17, A19, and A20 are connected to four pairs of differential signal terminals PROTC_LANE0_DN/PROTC_LANE0_DP, PROTC_LANE1_DN/PROTC_LANE1_DP, PROTC_LANE2_DN/PROTC_LANE2_DP, and PROTC_CLK_DN/PROTC_CLK_DP of the HDMI respectively. The terminals A22, A23, A25, A26, A29, A30, B23, B24, B26, B27, B30, and B31 are connected to six pairs of differential signal terminals EXP_TXP0/EXP_TXN0, EXP_RXP0/EXP_RXN0, EXP_TXP1/EXP_TXN1, EXP_TXP3/EXP_TXN3, EXP_RXP3/EXP_RXN3, and EXP_TXP2/EXP_TXN2 of a graphic and memory controller hub (GMCH) respectively. The terminals B2, B3, B5, B6, B8, B9, B13, B14, B16, B17, B19, and B20 are connected to six pairs of differential signal terminals EXP_RXP0/EXP_RXN0, EXP_TXP0/EXP_TXN0, EXP_TXP1/EXP_TXN1, EXP_TXP2/EXP_TXN2, EXP_TXP3/EXP_TXN3, and EXP_RXP3/EXP_RXN3 of a peripheral component interconnect express X16 (PCI-E X16) slot respectively. The other terminals are grounded.
  • Referring to FIG. 2, a patch panel in accordance with an embodiment of the present invention comprises a printed circuit board defining sixty-four signal terminals C1˜C32 and D1˜D32 on a first side 20 thereof. The signal terminals C22, C23, C25, C26, C29, C30, D23, D24, D26, D27, D30, and D31 are connected to the signal terminals D5, D6, D2, D3, D8, D9, D16, D17, D19, D20, D13, and D14 respectively. The signal terminals C1˜C32 and D1˜D32 of the patch panel are connected to the terminals A1˜A32 and B1˜B32 of the patch panel connector 10 respectively when the first side 20 of the patch panel is mounted on the patch panel connector 10. Therefore, the differential signal terminals EXP_TXP0, EXP_TXN0, EXP_RXP0, EXP_RXN0, EXP_TXP1, EXP_TXN1, EXP_TXP3, EXP_TXN3, EXP_RXP3, EXP_RXN3, EXP_TXP2, and EXP_TXN2 of the GMCH are connected to the differential signal terminals EXP_TXP0, EXP_TXN0, EXP_RXP0, EXP_RXN0, EXP_TXP1, EXP_TXN1, EXP_TXP3, EXP_TXN3, EXP_RXP3, EXP_RXN3, EXP_TXP2, and EXP_TXN2 of the PCI-E X16 slot respectively when the first side 20 of the patch panel is mounted on the motherboard via the patch panel connector 10.
  • Referring to FIG. 3, a second side 30 of the patch panel defines sixty-four signal terminals E1˜E32 and F1˜F32, wherein the signal terminals E1, E3, E4, E6, E7, E9, E10, E13, E14, E16, E17, E19, and E20 are connected to the signal terminals F26, F3, F2, F6, F5, F31, F30, E30, E29, E23, E22, F24, and F23 respectively. The signal terminals E1˜E32 and F1˜F32 of the patch panel are connected to the terminals A1˜A32 and B1˜B32 of the patch panel connector 10 respectively when the first side 20 of the patch panel is mounted on the patch panel connector 10. Therefore, the interface terminal HDMI_HDP_MUX and the differential signal terminals PROTC_LANE0_DN, PROTC_LANE0_DP, PROTC_LANE1_DN, PROTC_LANE1_DP, PROTC_LANE2_DN, PROTC_LANE2_DP, PROTC_CLK_DN, and PROTC_CLK_DP of the HDMI are connected to the differential signal terminals EXP_RXP3, EXP_TXN2, EXP_TXP2, EXP_TXN1, EXP_TXP1, EXP_TXN0, EXP_TXP0, EXP_TXN3, and EXP_TXP3 of the GMCH respectively, and the PCI-E X1 differential signal terminals HIS_N4, HIS_P4, HSO_N4, and HSO_P4 of the ICH are connected to the differential signal terminals EXP_RXN0, EXP_RXP0, EXP_TXN0, and EXP_TXP0 of the PCI-E X16 slot respectively, when the second side 30 of the patch panel is mounted on the motherboard via the patch panel connector 10.
  • Operators can selectively mount one of the first side 20 and the second side 30 of the patch panel on the motherboard via the patch panel connector 10 for selectively connecting the GMCH to the PCI-E X16 slot, or connecting the GMCH to the HDMI and concurrently connecting the ICH to the PCI-E X16 to support a PCI-E X1 card.
  • The foregoing description of the exemplary embodiments of the invention has been presented only for the purposes of illustration and description and is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to explain the principles of the invention and their practical application so as to enable others skilled in the art to utilize the invention and various embodiments and with various modifications as are suited to the particular use contemplated. Alternative embodiments will become apparent to those skilled in the art to which the present invention pertains without departing from its spirit and scope. Accordingly, the scope of the present invention is defined by the appended claims rather than the foregoing description and the exemplary embodiments described therein.

Claims (3)

1. A patch panel comprising a printed circuit board having first to twenty-sixth signal terminals defined on a first side thereof, wherein the first to thirteenth signal terminals are connected to the twentieth, twenty-fifth, twenty-sixth, twenty-third, twenty-fourth, eighteenth, nineteenth, seventeenth, sixteenth, fifteenth, fourteenth, twenty-first, and twenty-second signal terminals respectively, the second to the fifth signal terminals are arranged to connect to two pairs of peripheral component interconnect express (PCI-E) X1 differential signal terminals of an I/O controller hub (ICH), the first signal terminal is arranged to connect to an interface terminal of a high definition multimedia interface (HDMI), the sixth to the thirteenth signal terminals are arranged to connect four pairs of differential signal terminals of the HDMI, the fourth to the nineteenth, twenty-first, and twenty-second signal terminals are arranged to connect to four pairs of differential signal terminals of a graphic and memory controller hub (GMCH), the twentieth signal terminal is arranged to connect to one of another differential signal terminal of the GMCH, and the twenty-third to the twenty-sixth signal terminals are connect to two pairs of differential signal terminals of a PCI-E X16 slot.
2. The patch panel as claimed in claim 1 further comprising twenty-seventh to fiftieth signal terminals defined on a second side thereof, wherein the twenty-seventh to thirty-eighth signal terminals are connected to the forty-eighth, forty-seventh, fiftieth, forty-ninth, forty-sixth, forty-fifth, forty-third, forty-fourth, thirty-ninth, fortieth, forty-first, and forty-second signal terminals respectively, the twenty-seventh to the thirty-eighth signal terminals are arranged to connect to six pairs of differential signal terminals of the GMCH, and the thirty-ninth to the fiftieth signal terminals are arranged to connect to six pairs of differential signal terminals of the PCI-E X16 slot.
3. A patch panel connector mating with the patch panel as claimed in claim 1, comprising first to thirty-seventh terminals, wherein the first terminal is arranged to connect to an interface terminal of the HDMI, the second to the fifth terminals are arranged to connect to two pairs of PCI-E X1 differential signal terminals of the ICH, the sixth to the thirteenth terminals are arranged to connect to four pairs of differential signal terminals of the HDMI, the fourteenth to the twenty-fifth terminals are arranged to connect to six pairs of differential signal terminals of the GMCH, and the twenty-sixth to the thirty-seventh terminals are arranged to connect to six pairs of differential signal terminals of the PCI-E X16 slot.
US12/023,008 2007-12-28 2008-01-30 Patch panel and patch panel connector Expired - Fee Related US7677898B2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CN200710203514 2007-12-28
CN200710203514.7 2007-12-28
CN2007102035147A CN101470687B (en) 2007-12-28 2007-12-28 Signal switching card and its connector

Publications (2)

Publication Number Publication Date
US20090170348A1 true US20090170348A1 (en) 2009-07-02
US7677898B2 US7677898B2 (en) 2010-03-16

Family

ID=40799028

Family Applications (1)

Application Number Title Priority Date Filing Date
US12/023,008 Expired - Fee Related US7677898B2 (en) 2007-12-28 2008-01-30 Patch panel and patch panel connector

Country Status (2)

Country Link
US (1) US7677898B2 (en)
CN (1) CN101470687B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI403089B (en) * 2009-07-07 2013-07-21 Asustek Comp Inc Dongle

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2697996C (en) * 2009-04-01 2016-12-06 Bce Inc. Patch panel for use in delivering voice and data to end users
CN102299458B (en) * 2010-06-23 2013-06-26 环旭电子股份有限公司 Peripheral component interconnection express (PCI Express) signal transmission structure and method thereof
CN101923530B (en) * 2010-08-17 2012-06-06 北京航空航天大学 Adapter card from PCI (Peripheral Component Interconnect) Express X1 to CPCI (Compact Peripheral Component Interconnect) Express X1
CN102929333A (en) * 2011-08-10 2013-02-13 鸿富锦精密工业（深圳）有限公司 Connector combination
CN106654771A (en) * 2017-02-24 2017-05-10 无锡气动技术研究所有限公司 General expansion board and expansion circuit

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5400391A (en) * 1990-09-17 1995-03-21 Nec Corporation Mobile communication system
US5618185A (en) * 1995-03-15 1997-04-08 Hubbell Incorporated Crosstalk noise reduction connector for telecommunication system
US20030226071A1 (en) * 2002-05-31 2003-12-04 Transcept Opencell, Inc. System and method for retransmission of data

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN2403057Y (en) * 1999-08-31 2000-10-25 海信集团公司 PCI through circuit board

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5400391A (en) * 1990-09-17 1995-03-21 Nec Corporation Mobile communication system
US5618185A (en) * 1995-03-15 1997-04-08 Hubbell Incorporated Crosstalk noise reduction connector for telecommunication system
US20030226071A1 (en) * 2002-05-31 2003-12-04 Transcept Opencell, Inc. System and method for retransmission of data
US20070147278A1 (en) * 2002-05-31 2007-06-28 Adc Wireless Solutions Llc System and method for retransmission of data

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI403089B (en) * 2009-07-07 2013-07-21 Asustek Comp Inc Dongle

Also Published As

Publication number Publication date
CN101470687A (en) 2009-07-01
CN101470687B (en) 2011-11-09
US7677898B2 (en) 2010-03-16

Similar Documents

Publication Publication Date Title
US7677898B2 (en) Patch panel and patch panel connector
US8601196B2 (en) Connector assembly
US20050270298A1 (en) Daughter card approach to employing multiple graphics cards within a system
CN103076858A (en) Expansion card and main board for supporting expansion card
CN102999097A (en) Expansion card and mainboard supporting expansion card
US20090300252A1 (en) Monitor with peripheral equipment interface and computer
CN107613233B (en) Television processing system capable of compatibly processing two signals
US8433839B2 (en) Connector assembly
JP2010134949A (en) Field changeable graphics system
US20130205059A1 (en) Motherboard comprising expansion connector
US20130290590A1 (en) Connector assembly
US7477159B2 (en) Detection device and method thereof
US8659314B2 (en) Test apparatus for peripheral component interconnect expansion slot
KR20200042400A (en) External electrical connector and computer system
TW201439777A (en) Motherboard
CN102023696B (en) Computer system, used computer mainboard and display
CN101437133A (en) Test switching device
ATE495498T1 (en) INTEGRATED CIRCUIT AND ELECTRONIC DEVICE
US20150085144A1 (en) Dual video graphics array connectors testing system
CN103970190A (en) Mainboard with two display interfaces
US9817448B2 (en) Hot swap system and electronic device utilizing the same
CN102479064B (en) display, mouse and keyboard switching device
US20140361788A1 (en) Detection system and method for testing connector
CN104142709A (en) Mainboard
TW201804686A (en) Video adapter for installing video wall quickly and the method for the same

Legal Events

Date Code Title Description
AS Assignment

Owner name: HONG FU JIN PRECISION INDUSTRY (SHENZHEN) CO., LTD

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:RUI, YI;PAN, AI-YU;SHEN, JIAN-SHE;AND OTHERS;REEL/FRAME:020440/0440

Effective date: 20071229

Owner name: HON HAI PRECISION INDUSTRY CO., LTD., TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:RUI, YI;PAN, AI-YU;SHEN, JIAN-SHE;AND OTHERS;REEL/FRAME:020440/0440

Effective date: 20071229

Owner name: HON HAI PRECISION INDUSTRY CO., LTD.,TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:RUI, YI;PAN, AI-YU;SHEN, JIAN-SHE;AND OTHERS;REEL/FRAME:020440/0440

Effective date: 20071229

FPAY Fee payment

Year of fee payment: 4

FEPP Fee payment procedure

Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.)

AS Assignment

Owner name: HONGFUJIN PRECISION ELECTRONICS(TIANJIN)CO.,LTD.,

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HONG FU JIN PRECISION INDUSTRY (SHENZHEN) CO., LTD.;HON HAI PRECISION INDUSTRY CO., LTD.;REEL/FRAME:045501/0324

Effective date: 20180112

LAPS Lapse for failure to pay maintenance fees

Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.)

STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Expired due to failure to pay maintenance fee

Effective date: 20180316

点击 这是indexloc提供的php浏览器服务，不要输入任何密码和下载