US20090112352A1 - Equivalent gate count yield estimation for integrated circuit devices - Google Patents
Equivalent gate count yield estimation for integrated circuit devices Download PDFInfo
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- US20090112352A1 US20090112352A1 US12/348,549 US34854909A US2009112352A1 US 20090112352 A1 US20090112352 A1 US 20090112352A1 US 34854909 A US34854909 A US 34854909A US 2009112352 A1 US2009112352 A1 US 2009112352A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2111/00—Details relating to CAD techniques
- G06F2111/08—Probabilistic or stochastic CAD
Definitions
- the present invention relates generally to the fabrication of integrated circuits and, more particularly, to a method for improved equivalent gate count yield estimation for integrated circuit devices.
- the fabrication of integrated circuits is an extremely complex process that may involve hundreds of individual operations.
- the process includes the diffusion of precisely predetermined amounts of dopant material into precisely predetermined areas of a silicon wafer to produce active devices such as transistors. This is typically done by forming a layer of silicon dioxide on the wafer, then utilizing a photomask and photoresist to define a pattern of areas into which diffusion is to occur through a silicon dioxide mask. Openings are then etched through the silicon dioxide layer to define the pattern of precisely sized and located openings through which diffusion will take place.
- interconnection lines are typically formed by deposition of an electrically conductive material which is defined into the desired interconnect pattern by a photomask, photoresist and etching process.
- a typical completed integrated circuit may have millions of transistors contained within a 0.1 inch by 0.1 inch silicon chip and interconnects of submicron dimensions.
- a storage medium includes a computer readable computer program code including instructions that, when executed by a computer, implement a method of modeling yield for semiconductor products.
- the method includes determining expected faults for each of a plurality of library elements by running a critical area analysis on each of the library elements, and assessing, from the critical area analysis, an expected number of faults per unit area, and comparing the same to actual observed faults on previously manufactured semiconductor products. Thereafter, the expected number of faults for each library element is updated in response to observed yield.
- a database is established, which includes the die size and expected faults for each of the library elements. Integrated circuit product die size is estimated, and library elements to be used to create the integrated circuit die are selected. Fault and size data for each of the selected library elements are obtained, the adjusted estimated faults for each of the library elements are summed, and estimated yield is calculated.
- the expected total number of faults for an integrated circuit die having N different library element types is determined by the expression:
- ⁇ (t) total number of faults per chip at time t;
- n i total number of library elements of type i present on the integrated circuit die
- ⁇ i estimated number of faults for the i th library element
- ⁇ i adjustment factor for the i th library element, determined by comparing the yield data for that library element with the estimated value ⁇ i ;
- F(t) learning factor at time t.
- the calculated yield is determined by the expression:
- Y ⁇ ( t ) Y C ⁇ ( t ) ⁇ Y 0 ⁇ i ⁇ ( t ) ⁇ 1 ( 1 + ⁇ ⁇ ( t ) / a i ) a i ;
- ⁇ (t) total average number of faults per chip
- FIG. 1 is a process flow diagram illustrating a method for modeling yield for semiconductor devices, in accordance with an embodiment of the invention
- FIG. 2 is a process flow diagram further illustrating an example of updating expected faults in response to observed yield, in accordance with a further embodiment of the invention
- FIG. 3 is simplified example of a database of predicted faults for each library element using the method of FIGS. 1 and 2 ;
- FIG. 4 is schematic block diagram of a general-purpose computing device suitable for practicing the method illustrated in FIGS. 1 and 2 .
- Disclosed herein is an improved method for modeling yield for semiconductor devices, in which the area density of a particular library element is assessed for fault sensitivity, with this information then used to predict yield by summing the faults for each library element in a product.
- the present method provides a more accurate yield (and cost) estimate through consideration of localized fault density differences.
- FIG. 1 there is shown a process flow diagram illustrating a method 100 for modeling yield for semiconductor devices, in accordance with an embodiment of the invention.
- the die size is estimated, followed by selecting the library elements (e.g., cells) planned for use in a product design as shown in block 104 .
- the number of predicted faults for each library element is determined from a database, as shown in block 106 .
- the database is generated through a parallel process, which also depicted in FIG. 1 .
- an expected number of faults for each of a plurality of library elements is first determined by running a critical area analysis on each of the library elements.
- an expected number of faults per unit area is assessed from the critical area analysis. This expected number is then compared to actual observed faults on previously manufactured semiconductor products, and the expected number faults for each library element is thus updated in response to observed yield.
- a database of predicted faults for each library element is established, as shown in block 112 .
- the total number of faults for an integrated circuit die consisting of N library element types may be determined as follows:
- ⁇ (t) total number of faults per chip at time t;
- n i total number of library elements of type i present on the integrated circuit die
- ⁇ i estimated number of faults for the i th library element
- ⁇ i adjustment factor for the i th library element, determined by comparing the yield data for that library element with the estimated value ⁇ i ;
- F(t) learning factor at time t.
- the learning factor represents a reduction in manufacturing faults over time, and is the rate at which process engineers can reduce manufacturing faults through process improvements.
- Y ⁇ ( t ) Y C ⁇ ( t ) ⁇ Y 0 ⁇ i ⁇ ( t ) ⁇ 1 ( 1 + ⁇ ⁇ ( t ) / a i ) a i ;
- ⁇ (t) total average number of faults per chip
- the present methodology takes into consideration the fault contribution of a particular library element, there is a resulting improvement in correlation between the observed yield and the predicted yield.
- the estimated yield is calculated from the sum of the faults for each of the library elements. Because the present methodology takes into consideration the fault contribution for a particular library element, there is a resulting improvement in correlation between the observed yield and the predicted yield.
- FIG. 2 there is shown another process flow diagram that expands upon block 110 of FIG. 1 , with regard to updating expected faults based on observed yield.
- block 202 specific semiconductor products exceeding or not meeting expected yield are identified.
- specific library element(s) causing the yield deviation are identified, as shown in block 204 .
- any fault entries in the database are modified to reflect the observed yield, as illustrated in block 206 .
- the revised fault entries are used for any subsequent product yield estimates.
- FIG. 3 illustrates simplified example of a database of predicted faults for each of a plurality of library elements ( 1 , 2 , 3 ) using the method of FIGS. 1 and 2 .
- the revised predicted yield for library element 1 is unchanged from the critical area analysis as a result of observed yield; however, the revised predicted yield for library elements 2 and 3 are different from the critical area analysis.
- FIG. 4 is a schematic block diagram of a general-purpose computer for practicing the present invention.
- computer system 300 has at least one microprocessor or central processing unit (CPU) 305 .
- CPU central processing unit
- CPU 305 is interconnected via a system bus 310 to a random access memory (RAM) 315 , a read-only memory (ROM) 320 , an input/output (I/O) adapter 325 for a connecting a removable data and/or program storage device 330 and a mass data and/or program storage device 335 , a user interface adapter 340 for connecting a keyboard 345 and a mouse 350 , a port adapter 355 for connecting a data port 360 and a display adapter 365 for connecting a display device 370 .
- RAM random access memory
- ROM read-only memory
- I/O input/output
- ROM 320 contains the basic operating system for computer system 300 .
- the operating system may alternatively reside in RAM 315 or elsewhere as is known in the art.
- removable data and/or program storage device 330 include magnetic media such as floppy drives and tape drives and optical media such as CD ROM drives.
- mass data and/or program storage device 335 include hard disk drives and non-volatile memory such as flash memory.
- other user input devices such as trackballs, writing tablets, pressure pads, microphones, light pens and position-sensing screen displays may be connected to user interface 340 .
- display devices include cathode-ray tubes (CRT) and liquid crystal displays (LCD).
- a computer program with an appropriate application interface may be created by one of skill in the art and stored on the system or a data and/or program storage device to simplify the practicing of this invention.
- information for or the computer program created to run the present invention is loaded on the appropriate removable data and/or program storage device 330 , fed through data port 360 or typed in using keyboard 345 .
- the present method embodiments may therefore take the form of computer or controller implemented processes and apparatuses for practicing those processes.
- the disclosure can also be embodied in the form of computer program code containing instructions embodied in tangible media, such as floppy diskettes, CD-ROMs, hard drives, or any other computer-readable storage medium, wherein, when the computer program code is loaded into and executed by a computer or controller, the computer becomes an apparatus for practicing the invention.
- the disclosure may also be embodied in the form of computer program code or signal, for example, whether stored in a storage medium, loaded into and/or executed by a computer or controller, or transmitted over some transmission medium, such as over electrical wiring or cabling, through fiber optics, or via electromagnetic radiation, wherein, when the computer program code is loaded into and executed by a computer, the computer becomes an apparatus for practicing the invention.
- the computer program code segments configure the microprocessor to create specific logic circuits.
- a technical effect of the executable instructions is to implement the exemplary method described above and illustrated in FIGS. 1 and 2 .
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Abstract
Description
- This application is a continuation of U.S. patent application Ser. No. 11/382,963, filed May 12, 2006, the disclosure of which is incorporated by reference herein in its entirety.
- The present invention relates generally to the fabrication of integrated circuits and, more particularly, to a method for improved equivalent gate count yield estimation for integrated circuit devices.
- The fabrication of integrated circuits is an extremely complex process that may involve hundreds of individual operations. Essentially, the process includes the diffusion of precisely predetermined amounts of dopant material into precisely predetermined areas of a silicon wafer to produce active devices such as transistors. This is typically done by forming a layer of silicon dioxide on the wafer, then utilizing a photomask and photoresist to define a pattern of areas into which diffusion is to occur through a silicon dioxide mask. Openings are then etched through the silicon dioxide layer to define the pattern of precisely sized and located openings through which diffusion will take place.
- After a predetermined number of such diffusion operations have been carried out to produce the desired number of transistors in the wafer, they are interconnected as required by interconnection lines. These interconnection lines, or interconnects as they are also known, are typically formed by deposition of an electrically conductive material which is defined into the desired interconnect pattern by a photomask, photoresist and etching process. A typical completed integrated circuit may have millions of transistors contained within a 0.1 inch by 0.1 inch silicon chip and interconnects of submicron dimensions.
- In view of the device and interconnect densities required in present day integrated circuits, it is imperative that the manufacturing processes be carried out with utmost precision and in a way that minimizes defects. For reliable operation, the electrical characteristics of the circuits must be kept within carefully controlled limits, which implies a high degree of control over the myriad of operations and fabrication processes. For example, in the photoresist and photomask operations, the presence of contaminants such as dust, minute scratches and other imperfections in the patterns on the photomasks can produce defective patterns on the semiconductor wafers, resulting in defective integrated circuits. Further, defects can be introduced in the circuits during the diffusion operations themselves. Defective circuits may be identified both by visual inspection under high magnification and by electrical tests. Once defective integrated circuits have been identified, it is desired to take steps to decrease the number of defective integrated circuits produced in the manufacturing process, thus increasing the yield of the integrated circuits meeting specifications.
- In the present state of the art, accurate yield prediction for an integrated circuit design based on critical area analysis can be performed only after design of the integrated circuit design is complete, while relatively simple and inaccurate die size models are used to predict yield prior to the design being completed. As integrated circuits become increasingly more complex, it is found that the pre and post design yield predictions often do not agree. Financial considerations require a more accurate method for predicating yield (and thus cost) at the time a new integrated circuit is under consideration.
- Logic library elements in current technologies have very different circuit packing density. In a conventional “equivalent gate count” modeling approach, it is assumed that all logic circuits are equally susceptible to defects. In practice, large differences are seen between different library elements. In addition, the presently used equivalent gate count prediction method assumes that circuits of a given type (e.g., logic circuits) are uniformly distributed over the entire surface of the die, when in fact this is not the case. Rather, many complex products contain areas of different circuit density. Thus, complex cores impact the yield of semiconductor parts that use these cores. Accordingly, there is a need for a further improved method for integrated circuit product yield prediction, as inaccurately predicted yields often result in poor business decisions when the product is quoted (e.g., lost business opportunity or lower than planned gross margin).
- A storage medium includes a computer readable computer program code including instructions that, when executed by a computer, implement a method of modeling yield for semiconductor products. The method includes determining expected faults for each of a plurality of library elements by running a critical area analysis on each of the library elements, and assessing, from the critical area analysis, an expected number of faults per unit area, and comparing the same to actual observed faults on previously manufactured semiconductor products. Thereafter, the expected number of faults for each library element is updated in response to observed yield. A database is established, which includes the die size and expected faults for each of the library elements. Integrated circuit product die size is estimated, and library elements to be used to create the integrated circuit die are selected. Fault and size data for each of the selected library elements are obtained, the adjusted estimated faults for each of the library elements are summed, and estimated yield is calculated.
- In one embodiment, the expected total number of faults for an integrated circuit die having N different library element types is determined by the expression:
-
- wherein
- t=time for which yield estimate is needed;
- λ(t)=total number of faults per chip at time t;
- ni=total number of library elements of type i present on the integrated circuit die;
- ri=redundancy factor for library element i;
- λi=estimated number of faults for the ith library element;
- τi=adjustment factor for the ith library element, determined by comparing the yield data for that library element with the estimated value λi; and
- F(t)=learning factor at time t.
- In another embodiment, the calculated yield is determined by the expression:
-
- wherein
- Y(t)=wafer test yield for the integrated circuit die;
- Y0i(t)=gross systematic test yield for technology i;
- YC(t)=chip custom circuit-limited yield (CLY) factor;
- λ(t)=total average number of faults per chip; and
- ai=cluster factor.
- Referring to the exemplary drawings wherein like elements are numbered alike in the several Figures:
-
FIG. 1 is a process flow diagram illustrating a method for modeling yield for semiconductor devices, in accordance with an embodiment of the invention; -
FIG. 2 is a process flow diagram further illustrating an example of updating expected faults in response to observed yield, in accordance with a further embodiment of the invention; -
FIG. 3 is simplified example of a database of predicted faults for each library element using the method ofFIGS. 1 and 2 ; and -
FIG. 4 is schematic block diagram of a general-purpose computing device suitable for practicing the method illustrated inFIGS. 1 and 2 . - Disclosed herein is an improved method for modeling yield for semiconductor devices, in which the area density of a particular library element is assessed for fault sensitivity, with this information then used to predict yield by summing the faults for each library element in a product. In contrast to more conventional yield estimation approaches that assume uniform circuit density over the area of a die, the present method provides a more accurate yield (and cost) estimate through consideration of localized fault density differences.
- Referring to
FIG. 1 , there is shown a process flow diagram illustrating a method 100 for modeling yield for semiconductor devices, in accordance with an embodiment of the invention. As is shown inblock 102, the die size is estimated, followed by selecting the library elements (e.g., cells) planned for use in a product design as shown inblock 104. Then, for each individual library element, the number of predicted faults for each library element is determined from a database, as shown inblock 106. - In an exemplary embodiment, the database is generated through a parallel process, which also depicted in
FIG. 1 . As shown inblock 108, an expected number of faults for each of a plurality of library elements is first determined by running a critical area analysis on each of the library elements. Then, inblock 110, an expected number of faults per unit area is assessed from the critical area analysis. This expected number is then compared to actual observed faults on previously manufactured semiconductor products, and the expected number faults for each library element is thus updated in response to observed yield. Upon updating the expected faults based on observed yield, a database of predicted faults for each library element is established, as shown inblock 112. - The total number of faults for an integrated circuit die consisting of N library element types may be determined as follows:
-
- wherein
- t=time for which yield estimate is needed;
- λ(t)=total number of faults per chip at time t;
- ni=total number of library elements of type i present on the integrated circuit die;
- ri=redundancy factor for library element i;
- λi=estimated number of faults for the ith library element;
- λi=adjustment factor for the ith library element, determined by comparing the yield data for that library element with the estimated value λi; and
- F(t)=learning factor at time t.
- The learning factor represents a reduction in manufacturing faults over time, and is the rate at which process engineers can reduce manufacturing faults through process improvements. Once the predicted number of faults for each library is obtained from the database (block 106) and summed as in the equation above to produce the total number of faults for a given integrated circuit chip (block 114), the yield can be predicted. This is shown in
block 116 and may be expressed as: -
- wherein
- Y(t)=wafer test yield for the integrated circuit die;
- Y0i(t)=gross systematic test yield for technology i;
- YC(t)=chip custom circuit-limited yield (CLY) factor;
- λ(t)=total average number of faults per chip; and
- ai=cluster factor.
- Because the present methodology takes into consideration the fault contribution of a particular library element, there is a resulting improvement in correlation between the observed yield and the predicted yield. Finally, as shown in
block 116, the estimated yield is calculated from the sum of the faults for each of the library elements. Because the present methodology takes into consideration the fault contribution for a particular library element, there is a resulting improvement in correlation between the observed yield and the predicted yield. - Referring now to
FIG. 2 , there is shown another process flow diagram that expands uponblock 110 ofFIG. 1 , with regard to updating expected faults based on observed yield. As shown inblock 202, specific semiconductor products exceeding or not meeting expected yield are identified. Then, specific library element(s) causing the yield deviation are identified, as shown inblock 204. With this information, any fault entries in the database are modified to reflect the observed yield, as illustrated inblock 206. Inblock 208, the revised fault entries are used for any subsequent product yield estimates. -
FIG. 3 illustrates simplified example of a database of predicted faults for each of a plurality of library elements (1, 2, 3) using the method ofFIGS. 1 and 2 . As is shown, the revised predicted yield forlibrary element 1 is unchanged from the critical area analysis as a result of observed yield; however, the revised predicted yield forlibrary elements - Generally, the method for modeling integrated circuit yield described herein is practiced with a general-purpose computer and the method may be coded as a set of instructions on removable or hard media for use by the general-purpose computer.
FIG. 4 is a schematic block diagram of a general-purpose computer for practicing the present invention. InFIG. 4 ,computer system 300 has at least one microprocessor or central processing unit (CPU) 305.CPU 305 is interconnected via asystem bus 310 to a random access memory (RAM) 315, a read-only memory (ROM) 320, an input/output (I/O)adapter 325 for a connecting a removable data and/orprogram storage device 330 and a mass data and/orprogram storage device 335, auser interface adapter 340 for connecting akeyboard 345 and amouse 350, aport adapter 355 for connecting adata port 360 and adisplay adapter 365 for connecting adisplay device 370. -
ROM 320 contains the basic operating system forcomputer system 300. The operating system may alternatively reside inRAM 315 or elsewhere as is known in the art. Examples of removable data and/orprogram storage device 330 include magnetic media such as floppy drives and tape drives and optical media such as CD ROM drives. Examples of mass data and/orprogram storage device 335 include hard disk drives and non-volatile memory such as flash memory. In addition tokeyboard 345 andmouse 350, other user input devices such as trackballs, writing tablets, pressure pads, microphones, light pens and position-sensing screen displays may be connected touser interface 340. Examples of display devices include cathode-ray tubes (CRT) and liquid crystal displays (LCD). - A computer program with an appropriate application interface may be created by one of skill in the art and stored on the system or a data and/or program storage device to simplify the practicing of this invention. In operation, information for or the computer program created to run the present invention is loaded on the appropriate removable data and/or
program storage device 330, fed throughdata port 360 or typed in usingkeyboard 345. - In view of the above, the present method embodiments may therefore take the form of computer or controller implemented processes and apparatuses for practicing those processes. The disclosure can also be embodied in the form of computer program code containing instructions embodied in tangible media, such as floppy diskettes, CD-ROMs, hard drives, or any other computer-readable storage medium, wherein, when the computer program code is loaded into and executed by a computer or controller, the computer becomes an apparatus for practicing the invention. The disclosure may also be embodied in the form of computer program code or signal, for example, whether stored in a storage medium, loaded into and/or executed by a computer or controller, or transmitted over some transmission medium, such as over electrical wiring or cabling, through fiber optics, or via electromagnetic radiation, wherein, when the computer program code is loaded into and executed by a computer, the computer becomes an apparatus for practicing the invention. When implemented on a general-purpose microprocessor, the computer program code segments configure the microprocessor to create specific logic circuits. A technical effect of the executable instructions is to implement the exemplary method described above and illustrated in
FIGS. 1 and 2 . - While the invention has been described with reference to a preferred embodiment or embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the invention will include all embodiments falling within the scope of the appended claims.
Claims (4)
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US11/382,963 US7477961B2 (en) | 2006-05-12 | 2006-05-12 | Equivalent gate count yield estimation for integrated circuit devices |
US12/348,549 US20090112352A1 (en) | 2006-05-12 | 2009-01-05 | Equivalent gate count yield estimation for integrated circuit devices |
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US11152235B2 (en) | 2017-08-24 | 2021-10-19 | Samsung Electronics Co., Ltd. | Apparatus and method for manufacture of semiconductor devices |
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US20100088129A1 (en) * | 2008-10-03 | 2010-04-08 | Chih-Shih Wei | Technology Selection and Pricing System |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6178539B1 (en) * | 1998-09-17 | 2001-01-23 | International Business Machines Corporation | Method and system for determining critical area for circuit layouts using voronoi diagrams |
US20020069369A1 (en) * | 2000-07-05 | 2002-06-06 | Tremain Geoffrey Donald | Method and apparatus for providing computer services |
US20020069396A1 (en) * | 2000-06-30 | 2002-06-06 | Zenasis Technologies, Inc. | Method for automated design of integrated circuits with targeted quality objectives using dynamically generated building blocks |
US20040009616A1 (en) * | 2002-07-09 | 2004-01-15 | International Business Machines Corporation | Method to detect systematic defects in VLSI manufacturing |
US6751519B1 (en) * | 2001-10-25 | 2004-06-15 | Kla-Tencor Technologies Corporation | Methods and systems for predicting IC chip yield |
US20050073875A1 (en) * | 2003-10-03 | 2005-04-07 | Matsushita Electric Industrial Co., Ltd. | Redundancy repaired yield calculation method |
US20050158888A1 (en) * | 1999-11-18 | 2005-07-21 | Pdf Solutions, Inc. | System and method for product yield prediction |
US6996790B2 (en) * | 2003-01-30 | 2006-02-07 | Synopsys, Inc. | System and method for generating a two-dimensional yield map for a full layout |
US7013441B2 (en) * | 2003-09-26 | 2006-03-14 | International Business Machines Corporation | Method for modeling integrated circuit yield |
US7055113B2 (en) * | 2002-12-31 | 2006-05-30 | Lsi Logic Corporation | Simplified process to design integrated circuits |
-
2006
- 2006-05-12 US US11/382,963 patent/US7477961B2/en not_active Expired - Fee Related
-
2009
- 2009-01-05 US US12/348,549 patent/US20090112352A1/en not_active Abandoned
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6178539B1 (en) * | 1998-09-17 | 2001-01-23 | International Business Machines Corporation | Method and system for determining critical area for circuit layouts using voronoi diagrams |
US20050158888A1 (en) * | 1999-11-18 | 2005-07-21 | Pdf Solutions, Inc. | System and method for product yield prediction |
US20020069396A1 (en) * | 2000-06-30 | 2002-06-06 | Zenasis Technologies, Inc. | Method for automated design of integrated circuits with targeted quality objectives using dynamically generated building blocks |
US20020069369A1 (en) * | 2000-07-05 | 2002-06-06 | Tremain Geoffrey Donald | Method and apparatus for providing computer services |
US6751519B1 (en) * | 2001-10-25 | 2004-06-15 | Kla-Tencor Technologies Corporation | Methods and systems for predicting IC chip yield |
US20040009616A1 (en) * | 2002-07-09 | 2004-01-15 | International Business Machines Corporation | Method to detect systematic defects in VLSI manufacturing |
US7055113B2 (en) * | 2002-12-31 | 2006-05-30 | Lsi Logic Corporation | Simplified process to design integrated circuits |
US6996790B2 (en) * | 2003-01-30 | 2006-02-07 | Synopsys, Inc. | System and method for generating a two-dimensional yield map for a full layout |
US7013441B2 (en) * | 2003-09-26 | 2006-03-14 | International Business Machines Corporation | Method for modeling integrated circuit yield |
US20050073875A1 (en) * | 2003-10-03 | 2005-04-07 | Matsushita Electric Industrial Co., Ltd. | Redundancy repaired yield calculation method |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11152235B2 (en) | 2017-08-24 | 2021-10-19 | Samsung Electronics Co., Ltd. | Apparatus and method for manufacture of semiconductor devices |
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US7477961B2 (en) | 2009-01-13 |
US20070265722A1 (en) | 2007-11-15 |
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