US20080138956A1

US20080138956A1 - Manufacturing method of semiconductor device

Info

Publication number: US20080138956A1
Application number: US11/962,126
Authority: US
Inventors: Shih-Chen Wang; Hsin-Ming Chen; Chun-Hung Lu; Ming-Chou Ho; Shih-Jye Shen; Ching-Hsiang Hsu
Original assignee: eMemory Technology Inc
Current assignee: eMemory Technology Inc
Priority date: 2005-11-17
Filing date: 2007-12-21
Publication date: 2008-06-12
Also published as: US20070108470A1; US20070109861A1; TWI308763B; TW200721492A; US7433243B2; US7447082B2; TW200721385A; US20070108507A1; US20070111357A1; TWI335078B; JP2007142398A; US20070109869A1; JP2007150292A; TWI311796B; JP2007158315A; TW200721189A

Abstract

A semiconductor device formed on a first conductive type substrate is provided. The device includes a gate, a second conductive type drain region, a second conductive type source region, and a second conductive type first lightly doped region. The gate is formed on the first conductive type substrate. The second conductive type drain region and the second conductive type source region are formed in the first conductive type substrate at both sides of the gate. The second conductive type first lightly doped region is formed in the first conductive type substrate between the gate and the second conductive type source region.

Description

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of an application Ser. No. 11/557,112, filed on Nov. 7, 2006, now pending, which claims the priority benefit of U.S. provisional applications Ser. No. 60/597,210, filed on Nov. 17, 2005 and 60/743,630, filed on Mar. 22, 2006. The entirety of each of the above-mentioned patent applications are hereby incorporated by reference herein and made a part of this specification.

BACKGROUND OF THE INVENTION

1. Field of the Invention
This invention relates to a manufacturing method of a semiconductor device, and more particularly to a manufacturing method of a semiconductor device which raises the limit of high-voltage stress.
2. Description of Related Art
A Metal Oxide Semiconductor (MOS) transistor device is one of the most important and fundamental electronic units among various electronic products. Since the invention of MOS transistor devices, people are constantly aiming for reducing the size of semiconductors; namely, more semiconductor devices are squeezed in a specific area so as to enhance and accelerate the performance of computation.
As the level of integration of integrated circuits increases, the dimensions of semiconductor devices decrease correspondingly. Accordingly, as the dimension of a Metal Oxide Semiconductor (MOS) transistor is reduced, the channel length also reduces. However, the dimension of the channel of a MOS transistor cannot be unlimitedly reduced. As the channel length of a semiconductor device reduces to a certain degree, various problems gradually emerge, which are generally so-called “short channel effects”. More specifically, when the channel length is decreased and the voltage applied remains unchanged, not only the operation speed of the transistor but also the lateral electric field in the channel is increased. Thereby, the energy of the channel electrons is increased, especially for the channel electrons near the drain region. The energy of these electrons is greater than the band gap of the semiconductor. Therefore, after colliding with valence-band electrons near the drain region, the channel electrons easily excite the valence-band electrons thereat to the conductive band and hot electrons are then formed. Parts of the hot electrons enter a gate oxide layer and cause damages, so that the reliability and the lifetime of the device are reduced. Especially when the dimension of a MOS transistor device is further reduced to a nanometer scale, the short channel effect and the punch through effect would become more serious, and a further size reduction of the semiconductor device is then hindered. Therefore, it is a common objective in the industry to produce a semiconductor device with small size, high integration, and high quality.

SUMMARY OF THE INVENTION

This invention is to provide a semiconductor device and the method of fabricating the same. The semiconductor device has a simple structure and a high breakdown voltage so as to raise the limit of high-voltage stress and to be operated under high voltage.
This invention provides a semiconductor device, including a gate, a second conductive type drain region, a second conductive type source region, and a second conductive type first lightly doped region. The gate is formed on a first conductive type substrate. The second conductive type drain region and the second conductive type source region are formed in the first conductive type substrate at both sides of the gate. The second conductive type first lightly doped region is formed between the gate and the second conductive type source region.
According to an embodiment of the present invention, the first conductive type is a P-type while a second conductive type is an N-type. Conversely, the second conductive type is a P-type while the first conductive type is an N-type.
According to an embodiment of the present invention, the semiconductor device further includes a first dielectric layer. The first dielectric layer is formed between the gate and the first conductive type substrate, wherein the first dielectric layer has a first thickness at a side of the second conductive type source region and a second thickness at a side of the second conductive type drain region. The first thickness is larger than the second.
According to an embodiment of the present invention, the semiconductor device further includes a first conductive type lightly doped region. The first conductive type lightly doped region is formed between the gate and the second conductive type drain region.
According to an embodiment of the present invention, the semiconductor device further includes a second conductive type second lightly doped region. The second conductive type second lightly doped region is formed between the gate and the second conductive type drain region. The second conductive type first lightly doped region contains a different dopant concentration from the second conductive type second lightly doped region.
According to an embodiment of the present invention, the semiconductor device further includes insulating spacers. The insulating spacers are formed on the side walls of the gate.
According to an embodiment of the present invention, the material of the insulating spacers includes silicon nitride or silicon oxide.
Inasmuch as a lightly doped region having a same conductive type as the source region is formed between the source region and the gate, but no lightly doped region is formed between the drain region and the gate. Even forming a neutral substrate at the sides of the drain region or forming a lightly doped region with an opposite conductive type to the drain region at the sides of the drain region are two other alternatives for the semiconductor device of the present invention.
Thus, a high breakdown voltage is then provided to raise the limit of high-voltage stress of the MOS device and to operate the semiconductor device of the present invention under a high voltage.
The invention provides a method for fabricating a semiconductor device. The fabricating process is described below. First, a first conductive type substrate is provided, and a gate is formed on the first conductive type substrate. Then, a second conductive type first lightly doped region is formed in the substrate at a first side of the gate. Thereafter, a second conductive type source region is formed in the substrate at the first side of the gate, and a second conductive type drain region is formed at a second side of the gate, wherein the second conductive type first lightly doped region is formed in the first conductive type substrate between the second conductive type source region and the gate.
According to an embodiment of the present invention, the first conductive type is a P-type while a second conductive type is an N-type. Conversely, the first conductive type is an N-type while the second conductive type is a P-type.
According to an embodiment of the present invention, the method further includes a step of forming a first dielectric layer on the first conductive type substrate before the step of forming the gate on the first conductive type substrate.
According to an embodiment of the present invention, the first dielectric layer has a first thickness at a first side and a second thickness at a second side. The second thickness is larger than the first.
According to an embodiment of the present invention, the steps of forming the second conductive type first lightly doped region in the first conductive type substrate at the first side of the gate are provided as following. First, a patterned photoresist layer exposing the first conductive type substrate at the first side of the gate is formed on the substrate. An ion implantation process is then performed to form the second conductive type first lightly doped region. Afterward, the patterned photoresist layer is removed.
According to an embodiment of the present invention, the method further includes a step of forming a first conductive type lightly doped region in the substrate at the second side of the gate. The first conductive type lightly doped region is formed between the second conductive type drain region and the gate.
According to an embodiment of the present invention, the steps of forming the second conductive type first lightly doped region in the first conductive type substrate at the first side of the gate, and forming the first conductive type lightly doped region in the substrate at the second side of the gate are provided as following. First, a first patterned photoresist layer exposing the first conductive type substrate at the first side of the gate is formed on the substrate. A first ion implantation process is then performed to form the second conductive type first lightly doped region. After the first patterned photoresist layer is removed, a second patterned photoresist layer exposing the first conductive type substrate at the second side of the gate is formed on the substrate. A second ion implantation process is then performed to form the first conductive type lightly doped region, and the second patterned photoresist layer is removed.
According to an embodiment of the present invention, the method further includes forming a second conductive type second lightly doped region in the substrate at the second side of the gate. The second conductive type second lightly doped region is formed between the second conductive type drain region and the gate.
According to an embodiment of the present invention, the steps of forming the second conductive type first lightly doped region and the second conductive type second lightly doped region in the first conductive type substrate at the first and the second sides of the gate, and forming the first conductive type lightly doped region in the substrate at the second side of the gate are provided as following. First, a first ion implantation process is performed to form the second conductive type first lightly doped region and the second conductive type second lightly doped region. A patterned photoresist layer exposing the first conductive type substrate at the second side of the gate is then formed on the substrate. After a second ion implantation process is performed to form the first conductive type lightly doped region, the patterned photoresist layer is removed.
According to an embodiment of the present invention, the method further includes forming insulating spaces at the side walls of the gate.
The method of fabricating the semiconductor device of the present invention has a simple fabricating process which can be integrated with the fabricating process of a conventional Complementary Metal Oxide Semiconductor (CMOS) so as to reduce the time of fabricating the device. Various specific embodiments of the present invention are disclosed below, illustrating examples of various possible implementations of the concepts of the present invention. The following description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a schematic cross-sectional view showing a preferred embodiment of the semiconductor device of the present invention.

FIG. 1B is a schematic cross-sectional view showing a preferred embodiment of the semiconductor device of the present invention.

FIG. 1C is a schematic cross-sectional view showing another preferred embodiment of the semiconductor device of the present invention.

FIG. 1D is a schematic cross-sectional view showing yet another preferred embodiment of the semiconductor device of the present invention.

FIGS. 2A through 2E are schematic cross-sectional views showing the steps for fabricating a semiconductor device according to a preferred embodiment of the present invention.

FIGS. 3A through 3B are schematic cross-sectional views showing the steps for fabricating a semiconductor device according to a preferred embodiment of the present invention.

FIGS. 4A through 4C are schematic cross-sectional views showing the steps for fabricating a semiconductor device according to another preferred embodiment of the present invention.

FIGS. 5A through 5D are schematic cross-sectional views showing the steps for fabricating a semiconductor device according to a preferred embodiment of the present invention.

DESCRIPTION OF EMBODIMENTS

FIG. 1A is a schematic cross-sectional view showing a preferred embodiment of the semiconductor device of the present invention.
Please refer to FIG. 1A. The semiconductor device of the present invention is, for example, formed on a first conductive type substrate 100. The first conductive type substrate 100 is a silicon substrate, for example. The semiconductor device includes a gate dielectric layer 102, a gate 104, a dielectric layer 106, insulating spacers 108, a second conductive type source region 110, a second conductive type drain region 112, and a second conductive type lightly doped region 114, for example.
The gate 104 is, for example, formed on the first conductive type substrate 100. The material of the gate 104 is, for example, doped polysilicon.
The gate dielectric layer 102 is, for example, formed between the gate 104 and the first conductive type substrate 100. The material of the gate dielectric layer 102 is, for example, silicon oxide.
The second conductive type source region 110 and the second conductive type drain region 112 are formed in the first conductive type substrate 100 at both sides of the gate 104, for example.
The insulating spacers 108 are, for example, formed on the side walls of the gate 104. The material of the insulating spacers 108 is silicon oxide or silicon nitride, for example.
The second conductive type lightly doped region 114 is, for example, formed in the first conductive type substrate 100 between the gate 104 and the second conductive type source region 110. Namely, it is positioned under the insulating spacers 108.
In the above-mentioned embodiment, if the first conductive type is a P-type and the second conductive type is an N-type, the semiconductor device is an N-channel semiconductor device. On the other hand, if the first conductive type is an N-type and the second conductive type is a P-type, the semiconductor device is then a P-channel semiconductor device.
According to the semiconductor device of the present invention, inasmuch as the second conductive type lightly doped region is not formed at the sides of the second conductive type drain region 112, the limit of high-voltage stress of the MOS device can be raised, so that the semiconductor device of the present invention can be operated under a high voltage.
FIG. 1B is a schematic cross-sectional view showing another preferred embodiment of the semiconductor device of the present invention. In FIG. 1B, the same reference numbers are used to refer to the same parts in FIG. 1A. Here, only the differences are described.
Please refer to FIG. 1B. The semiconductor device includes a first conductive type lightly doped region 116 formed at the sides of the second conductive type drain region 112. The first conductive type lightly doped region 116 is, for example, formed in the first conductive type substrate 100 between the gate 104 and the second conductive type drain region 112. Namely, it is positioned under the insulating spacers 108.
According to the semiconductor device shown in FIG. 1B, inasmuch as a lightly doped region with an opposite conductive type to the source/drain region is formed at the sides of the drain region, thereby the limit of high-voltage stress of the MOS device can be raised, so that the semiconductor device of the present invention can be operated under a high voltage.
FIG. 1C is a schematic cross-sectional view showing yet another preferred embodiment of the semiconductor device of the present invention. In FIG. 1C, the same reference numbers are used to refer to the same parts in FIG. 1A. Here, only the differences are described.
Please refer to FIG. 1C. The semiconductor device includes the first conductive type lightly doped region 116 and a second conductive type lightly doped region 114 a formed at the sides of the second conductive type drain region 112. The first conductive type lightly doped region 116 is, for example, formed in the first conductive type substrate 100 between the gate 104 and the second conductive type drain region 112. Namely, it is positioned under the insulating spacers 108. The second conductive type lightly doped region 114 a is, for example, formed in the first conductive type substrate 100 between the gate 104 and the second conductive type drain region 112. Namely, it is positioned under the insulating spacers 108.
According to the semiconductor device shown in FIG. 1C, inasmuch as a second conductive type lightly doped region 114 a and the first conductive type lightly doped region 116 are formed at the sides of the drain and have an opposite conductive type, the substrate 100 between the second conductive type drain region 112 and the gate stays at the first conductive type, thereby the limit of high-voltage stress of the MOS device can be raised, so that the semiconductor device of the present invention under a high voltage.
FIG. 1D is a schematic cross-sectional view showing yet another preferred embodiment of the semiconductor device of the present invention. In FIG. 1D, the same reference numbers are used to refer to the same parts in FIG. 1A. Here, only the differences are described.
Please refer to FIG. 1D. The gate dielectric layer 102 a between the gate 104 and the first conductive type substrate 100 is provided with a different thickness near the second conductive type drain region 112 and near the second conductive type source region 110. For example, the gate dielectric layer 102 a is provided with a thickness d1 near the second conductive type source region 110 and a thickness d2 near the second conductive type drain 112. The thickness d2 is larger than thickness d1.
According to the semiconductor device shown in FIG. 1D, inasmuch as the gate dielectric layer 102 a is relatively thick near the second conductive type drain region 112, high voltage durability is thereby achieved. Consequently, the gate dielectric layer is exempted from being damaged while a high voltage is applied to the drain region.
According to the semiconductor device shown in FIG. 1D, the lightly doped region with the same conductive type as the source region formed between the source region and the gate and the lightly doped region with a different conductive type from the drain region formed between the drain region and the gate are taken as an example to describe herein. Other alternatives are as shown in FIG. 1B and FIG. 1C. The lightly doped region with an opposite conductive type to the drain region is formed between the drain region and the gate, or two lightly doped regions having opposite conductive types are formed in the substrate between the drain region and the gate so as to neutralize the substrate between the drain region and the gate.
Inasmuch as the lightly doped region having a same conductive type as the source region is formed between the source region and the gate, but no lightly doped region is formed between the drain region and the gate. Even forming a neutral substrate at the sides of the drain region or forming a lightly doped region with an opposite conductive type to the drain region at the sides of the drain region are two other alternatives for the semiconductor device of the present invention. Accordingly, a high breakdown voltage can be provided to raise the limit of the high-voltage stress of the MOS device and to operate the semiconductor device of the present invention under a high voltage.
The method of fabricating the semiconductor device in the present invention is explained thereupon. FIGS. 2A through 2E are schematic cross-sectional views showing the steps for fabricating a semiconductor device according to a preferred embodiment of the present invention.
Please refer to FIG. 2A. First, a first conductive type substrate 200 is provided. A dielectric layer 202 and a conductive layer 204 are formed on the substrate 200 sequentially. The first conductive type substrate 200 is a silicon substrate, for example. The material of the dielectric layer 202 is, for example, silicon oxide. The dielectric layer is formed, for example, by thermal oxidation. The material of the conductive layer 204 is, for example, doped polysilicon. The method for forming conductive layer 204 includes forming a layer of undoped polysilicon by chemical vapor deposition, and then performing an ion-implantation process; or adopting an in-situ implanting operation in a chemical vapor deposition process.
Please refer to FIG. 2B. The conductive layer 204 and the dielectric layer 202 are patterned to form the gate 204 a and the gate dielectric layer 202 a. The patterned conductive layer 204 and the dielectric layer 202 are formed, for example, by performing photolithographic and etching processes. Then, a dielectric layer 206 is formed on the substrate 200. The material of the dielectric layer 206 is, for example, silicon oxide. The dielectric layer 206 is formed by thermal oxidation or chemical vapor deposition, for example.
Please refer to FIG. 2C. A patterned photoresist layer 208 exposing the substrate 200 at one side of the gate 204 a is formed on the substrate 200. The patterned photoresist layer 208 is formed by performing a photolithographic process, for example. A dopant implantation process 210 is performed by using the patterned photoresist layer 208 as a mask to form a second conductive type lightly doped region 212 in the substrate 200. The dopant implantation process 210 is, for example, to implant dopants in the substrate 200 through an ion implantation process.
Please refer to FIG. 2D. After the patterned photoresist layer 208 is removed, insulating spacers 214 are formed at the side walls of the gate 204. The material of the insulating spacers 214 is silicon oxide, silicon nitride, or SiON, for example. The insulating spacers 214 are, for example, formed by performing a chemical vapor deposition process at first to form an insulating material layer, and removing a part of the insulating material layer through an anisotropic etching operation.
Please refer to FIG. 2E. Subsequently, a dopant implantation process 216 is performed by using the gate 204 a with insulating spacers 214 as a mask to form a second conductive type source region 218 a and a second conductive type drain region 218 b in the substrate 200. The dopant implantation process 216 is, for example, to implant dopants in the substrate 200 through an ion implantation process.
FIGS. 3A through 3B are schematic cross-sectional views showing the steps for fabricating a semiconductor device according to a preferred embodiment of the present invention. In FIGS. 3A and 3B, the same reference numbers are used to refer to the same parts in FIGS. 2A through 2E. Same descriptions are as well omitted.
Please refer to FIG. 3A. The steps depicted in FIG. 3A follow FIG. 2C. Namely, the patterned photoresist layer 208 is removed after the second conductive type lightly doped region 212 is formed in the substrate 200. Afterward, another patterned photoresist layer 220 exposing the substrate 200 at another side (the side in opposition to the second conductive type lightly doped region 212) of the gate 204 a is formed on the substrate 200. The patterned photoresist layer 220 is formed by performing a photolithographic process, for example. A dopant implantation process 222 is performed by using the patterned photoresist layer 220 as a mask to form a first conductive type lightly doped region 224 in the substrate 200. The dopant implantation process 222 is, for example, to implant dopants in the substrate 200 through an ion implantation process.
Please refer to FIG. 3B. After the patterned photoresist layer 220 is removed, insulating spacers 214 are formed at the side walls of the gate 204. Subsequently, a dopant implantation process 216 is performed by using the gate 204 a with the insulating spacers 214 as a mask to form a second conductive type source region 218 a and a second conductive type drain region 218 b in the substrate 200.
FIGS. 4A through 4C are schematic cross-sectional views showing the steps for fabricating a semiconductor device according to another preferred embodiment of the present invention. In FIGS. 4A through 4C, the same reference numbers are used to refer to the same parts in FIGS. 2A through 2E. Same descriptions are as well omitted.
Please refer to FIG. 4A. The steps depicted in FIG. 4A follow FIG. 2B. Namely, after the gate 204 a, the gate dielectric layer 202 a, and the dielectric layer 206 are formed on the substrate 200. A dopant implantation process 224 is performed by using the gate 204 a as a mask so as to form the second conductive type lightly doped regions 212 a and 212 b on the substrate 200 at both sides of the gate 204 a. The dopant implantation process 224 is, for example, to implant dopants in the substrate 200 through an ion implantation process.
Please refer to FIG. 4B. A patterned photoresist layer 226 exposing the substrate 200 at one side of the gate 204 a is formed on the substrate 200. The patterned photoresist layer 226 is formed by performing a photolithographic process, for example. Then, a dopant implantation process 228 is performed by using the patterned photoresist layer 226 as a mask to form a first conductive type lightly doped region 230 in the substrate 200. The dopant implantation process 228 is, for example, to implant dopants in the substrate 200 through an ion implantation process.
Please refer to FIG. 4C. After the patterned photoresist layer 226 is removed, insulating spacers 214 are formed at the side walls of the gate 204. Subsequently, a dopant implantation process 216 is performed by using the gate 204 a with the insulating spacers 214 as a mask to form the second conductive type source region 218 a and the second conductive type drain region 218 b in the substrate 200.
FIGS. 5A through 5D are schematic cross-sectional views showing the steps for fabricating a semiconductor device according to a preferred embodiment of the present invention. In FIGS. 5A through 5E, the same reference numbers are used to refer to the same parts in FIGS. 2A through 2E. Same descriptions are as well omitted.
Please refer to FIG. 5A. First, the first conductive type substrate 200 is provided. Then a dielectric layer 202 and a conductive layer 204 are formed on the substrate 200 sequentially. The first conductive type substrate 200 is a silicon substrate, for example. The dielectric layer 202, for example, constitutes the dielectric layers 201 a and 201 b. Hence, the dielectric layer 202 has two types of thicknesses. The material of the dielectric layer 202 is, for example, silicon oxide. The method of fabricating the dielectric layer 202 is, for example, to form a dielectric layer on the substrate 200 at first. Afterward, the dielectric layer is patterned to form the dielectric layer 201 a and the dielectric layer 201 b is then formed on the substrate 200. The material of the conductive layer 204 is, for example, doped polysilicon. The method for forming the conductive layer 204 includes forming a layer of undoped polysilicon by chemical vapor deposition and then performing a process of ion-implantation; or adopting an in-situ implanting operation in a chemical vapor deposition process.
Please refer to FIG. 5B. The conducting layer 204 and the dielectric layer 202 are patterned to form the gate 204 a and the gate dielectric layer 202 a. The patterned conductive layer 204 and the dielectric layer 202 are formed, for example, by performing photolithographic and etching processes. Then, the dielectric layer 206 is formed on the substrate 200. The material of the dielectric layer 206 is, for example, silicon oxide. The dielectric layer 206 is formed by thermal oxidation or chemical vapor deposition, for instance.
Please refer to FIG. 5C. A patterned photoresist layer 208 exposing the substrate 200 at one side of the gate 204 a is formed on the substrate 200. The patterned photoresist layer 208 is formed by performing a photolithographic process, for example. A dopant implantation process 210 is performed by using the patterned photoresist layer 208 as a mask to form a second conductive type lightly doped region 212 in the substrate 200. The second conductive type lightly doped region 212 is formed at the thinner side of the dielectric layer 202 a. The dopant implantation process 210 is, for example, to implant dopants in the substrate 200 through an ion implantation process.
Please refer to FIG. 5D. After the patterned photoresist layer 208 is removed, insulating spacers 214 are formed at the side walls of the gate 204. Subsequently, a dopant implantation process 216 is performed by using the gate 204 a with insulating spacers 214 as a mask to form the second conductive type source region 218 a and the second conductive type drain region 218 b in the substrate 200. The dopant implantation process 216 is, for example, to implant dopants in the substrate 200 through an ion implantation process. As stated in the method of fabricating the semiconductor device shown in FIGS. 5A through 5D, the fabricating method disclosed in FIGS. 3A through 3B and FIGS. 4A through 4C can be likewise applied to the method of fabricating the lightly doped region.
According to the method of fabricating the semiconductor device shown in FIGS. 5A through 5D, the lightly doped region with the same conductive type as the source region formed between the source region and the gate and the lightly doped region with a different conductive type from the drain region formed between the drain region and the gate are taken as an example to describe herein. Other alternatives are as shown in FIGS. 3A through 3B and FIGS. 4A through 4C. The lightly doped region with an opposite conductive type to the drain region is formed between the drain region and the gate, or two lightly doped regions having opposite conductive types are formed in the substrate between the drain region and the gate so as to neutralize the substrate between the drain region and the gate.
As stated above, the method of fabricating the semiconductor device of the present invention has a simple fabricating process which can be integrated with the process of fabricating a conventional Complementary Metal Oxide Semiconductor (CMOS) so as to reduce the time of fabricating the device.
In conclusion, inasmuch as a lightly doped region having a same conductive type as the source region is formed between the source region and the gate, but on lightly doped region is formed between the drain region and the gate. Even forming a neutral substrate at the sides of the drain region or forming a lightly doped region with an opposite conductive type to the drain region at the sides of the drain region are two other alternatives for the semiconductor device of the present invention. If the semiconductor device is operated under a smaller turned-on current, a better device performance can be then achieved and the limit of high-voltage stress can be raised so as to operate the semiconductor device of the present invention under a high voltage.
Furthermore, since the method of fabricating the semiconductor device of the present invention can be integrated with the process of fabricating a conventional Bipolar Complementary Metal Oxide Semiconductor (CMOS), the time of fabricating the device can be reduced without performing the photolithographic and etching processes.
The above description provides a full and complete description of the preferred embodiments of the present invention. Various modifications, alternate construction, and equivalent may be made by those skilled in the art without changing the scope or spirit of the invention. Accordingly, the above description and illustrations should not be construed as limiting the scope of the invention which is defined by the following claims.

Claims

What is claimed is:

1. A method of fabricating a semiconductor device, comprising:

providing a first conductive type substrate;

forming a gate on the first conductive type substrate;

forming a second conductive type first lightly doped region in the substrate at a first side of the gate; and

forming a second conductive type source region in the substrate at the first side of the gate, and forming a second conductive type drain region at a second side of the gate, wherein the second conductive type first lightly doped region is formed in the first conductive type substrate between the second conductive type source region and the gate.

2. The method of fabricating the semiconductor device of claim 1, wherein the first conductive type is a P-type while the second conductive type is an N-type; or the first conductive type is an N-type while the second conductive type is a P-type.

3. The method of fabricating the semiconductor device of claim 1, further comprising forming a first dielectric layer on the first conductive type substrate before the step of forming the gate on the first conductive type substrate.

4. The method of fabricating the semiconductor device of claim 3, wherein the first dielectric layer has a first thickness at the first side and a second thickness at the second side, and the second thickness is larger than the first thickness.

5. The method of fabricating the semiconductor device of claim 1, wherein the steps of forming the second conductive type first lightly doped region in the first conductive type substrate at the first side of the gate comprise:

forming a patterned photoresist layer exposing the first conductive type substrate at the first side of the gate on the substrate;

performing an ion implantation process to form the second conductive type first lightly doped region; and

removing the patterned photoresist layer.

6. The method of fabricating the semiconductor device of claim 1, further comprising forming a first conductive type lightly doped region in the substrate at the second side of the gate, wherein the first conductive type lightly doped region is formed between the second conductive type drain region and the gate.

7. The method of fabricating the semiconductor device of claim 6, wherein the steps of forming the second conductive type first lightly doped region in the first conductive type substrate at the first side of the gate and forming the first conductive type lightly doped region in the substrate at the second side of the gate comprise:

forming a first patterned photoresist layer exposing the first conductive type substrate at the first side of the gate on the substrate;

performing a first ion implantation process to form the second conductive type first lightly doped region;

removing the first patterned photoresist layer;

forming a second patterned photoresist layer exposing the first conductive type substrate at the second side of the gate on the substrate;

performing a second ion implantation process to form the first conductive type lightly doped region; and

removing the second patterned photoresist layer.

8. The method of fabricating the semiconductor device of claim 6, further comprising: forming a second conductive type second lightly doped region in the substrate at the second side of the gate, wherein the second conductive type second lightly doped region is formed between the second conductive type drain region and the gate.

9. The method of fabricating the semiconductor device of claim 8, wherein the steps of forming the second conductive type first lightly doped region and the second conductive type second lightly doped region in the first conductive type substrate at the first side and the second side of the gate and forming the first conductive type lightly doped region in the substrate at the second side of the gate comprise:

performing a first ion implantation process to form the second conductive type first lightly doped region and the second conductive type second lightly doped region;

forming a patterned photoresist layer exposing the first conductive type substrate at the second side of the gate on the substrate;

removing the patterned photoresist layer.

10. The method of fabricating the semiconductor device of claim 1, further comprising forming insulating spacers at the side walls of the gate.