US20080081456A1 - Chip-on-board package having flip chip assembly structure and manufacturing method thereof - Google Patents
Chip-on-board package having flip chip assembly structure and manufacturing method thereof Download PDFInfo
- Publication number
- US20080081456A1 US20080081456A1 US11/941,421 US94142107A US2008081456A1 US 20080081456 A1 US20080081456 A1 US 20080081456A1 US 94142107 A US94142107 A US 94142107A US 2008081456 A1 US2008081456 A1 US 2008081456A1
- Authority
- US
- United States
- Prior art keywords
- chip
- conductive film
- conductive
- metal
- holes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13144—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
- H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/81201—Compression bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/81201—Compression bonding
- H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/81201—Compression bonding
- H01L2224/81205—Ultrasonic bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/90—Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/90—Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0388—Other aspects of conductors
- H05K2201/0394—Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09472—Recessed pad for surface mounting; Recessed electrode of component
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
Definitions
- the present invention relates generally to semiconductor package technology and, more particularly, to a chip-on-board (COB) package having a flip-chip assembly structure and to a manufacturing method thereof.
- COB chip-on-board
- An integrated circuit (IC) card in which an IC chip is contained, can substitute for a conventional magnetic card.
- the IC chip is assembled in the form of typical COB package and then embedded in the IC card.
- FIG. 1 shows, in a cross-sectional view, a conventional COB package used for the IC card.
- the COB package 10 mounts in a card body 9 through one surface of the card body 9 .
- Conductive patterns such as metal patterns 11 formed on the COB package 10 and exposed outside the card body 9 act as contact terminals of the IC card.
- the metal patterns 11 are formed on an outer surface 12 a of a thin, non-conductive film 12 .
- An IC chip 13 is attached on an inner surface 12 b of the non-conductive film 12 .
- the non-conductive film 12 has several holes 12 c formed near the IC chip 13 .
- Metal wires 14 electrically couple the IC chip 13 to the metal patterns 11 through the holes 12 c in the non-conductive film 12 .
- the IC chip 13 and the metal wires 14 are encapsulated in a mold resin 15 provided on the inner surface 12 b of the non-conductive film 12 .
- the mold resin 15 may protect and fix the IC chip 13 and the metal wires 14 .
- a typical package assembly process may be used to manufacture the aforementioned conventional COB package 10 . Therefore, mass-productivity may be a merit of the conventional COB package 10 .
- the IC card can be very thin, e.g., less than one millimeter thick, and can be inherently flexible.
- the conventional COB package 10 may tend to be affected by external force.
- an active surface 13 a of the IC chip 13 faces toward the inside of the card body 9 while the metal patterns 11 face toward the outside of the card body 9 . This makes the length of the metal wire 14 relatively longer. Often, poorer electrical connections arise from longer metal wires 14 in spite of protection by the mold resin 15 .
- FIG. 2 shows in cross-section another conventional COB package used for the IC card.
- COB package 20 has a flip chip assembly structure instead of the metal wires and the mold resin as discussed above.
- an active surface 23 a of an IC chip 23 faces toward a non-conductive film 22 .
- Conductive bumps such as metal bumps 24 are formed on the active surface 23 a of the IC chip 23
- second metal patterns 21 a are formed on an inner surface 22 b of the non-conductive film 22 .
- the second metal patterns 21 a are electrically coupled through interconnection vias 21 b to first metal patterns 21 formed on an outer surface 22 a of the non-conductive film 22 .
- the metal bumps 24 are mechanically joined to the second metal patterns 21 a , providing electrical paths between the IC chip 23 and the first metal patterns 21 .
- Metal bumps 24 provide relatively shorter and more reliable electrical paths.
- the above-discussed flip chip assembly structure may not only have less possibility of poor electrical connections, but also may have no need of the mold resin.
- Conventional COB package 20 however, necessarily requires the second metal patterns 21 a on the inner surface 22 b of the non-conductive film 22 . This represents greater production cost in comparison with the previous example using the metal wires.
- the first and second metal patterns 21 and 21 a may be formed from metal plates, which are bonded to both surfaces 22 a and 22 b of the non-conductive film 22 and then patterned by selective etching in a photolithographic process. Therefore, using the second metal patterns 21 a as well as the metal bumps 24 may incur relatively higher production cost in comparison with using the metal wires.
- the process of forming the second metal patterns 21 a may be carried out separately from the process of forming the first metal patterns 21 . As a result, this conventional COB package 20 may have no significant advantage in its manufacturing method.
- Exemplary, non-limiting embodiments of the present invention provide a structure and a manufacturing method of a chip-on-board (COB) package allowing a reduction in production cost, simplified process, better electrical connections, and improved reliability.
- COB chip-on-board
- the COB package comprises a non-conductive film, metal patterns, an integrated circuit (IC) chip, and a number of metal bumps.
- the non-conductive film has a first surface, a second surface opposite to the first surface, and a number of holes.
- the metal patterns are formed on the first surface of the non-conductive film, but partly exposed through the holes of the non-conductive film.
- the IC chip has an active surface facing the second surface of the non-conductive film.
- the metal bumps are formed on the active surface of the IC chip and insertable into the holes of the non-conductive film to mechanically join and electrically couple to the metal patterns.
- the metal bumps may have a height greater than the thickness of the non-conductive film.
- the height of the metal bump may be about 40 ⁇ m, e.g., between about 30 ⁇ m and about 50 ⁇ m, and the thickness of the non-conductive film may be about 10 ⁇ m to about 20 ⁇ m.
- the metal bumps may be made of gold and the non-conductive film may be made of epoxy or polyimide.
- the width of the metal bumps may be about 20 ⁇ m and the diameter of the holes may be about 1 mm.
- the method of manufacturing a COB package comprises forming holes in a non-conductive film having a first surface and a second surface opposite to the first surface; forming metal patterns on the first surface of the non-conductive film to partly expose the metal patterns through the holes; forming metal bumps on an active surface of an integrated circuit (IC) chip; disposing the IC chip relative to the second surface of the non-conductive film to insert the metal bumps into the holes of the non-conductive film; and mechanically joining and electrically coupling the metal bumps and the metal patterns.
- IC integrated circuit
- the forming of the holes may be carried out using a punch. Further, the forming of the metal patterns may include bonding a metal plate to the first surface of the non-conductive film and thereafter photo-etching the metal plate. Additionally, the forming of the metal bumps may be carried out using electroplating or stud bumping.
- the method may further comprise, before the joining of the metal bumps, providing a non-conductive adhesive between the active surface of the IC chip and the second surface of the non-conductive film.
- Exemplary, non-limiting embodiments of the present invention provide an IC card having a thin and flexible card body and the above-discussed COB package.
- the COB package is mounted in the card body through one surface of the card body, and the metal patterns of the package are exposed outside the card body to act as contact terminals of the IC card.
- FIG. 1 is a cross-sectional view showing a conventional COB package used for an IC card.
- FIG. 2 is a cross-sectional view showing another convention COB package used for the IC card.
- FIG. 3 is a cross-sectional view showing a COB package of a flip chip assembly structure in accordance with an exemplary embodiment of the present invention.
- FIGS. 4A to 4 D are cross-sectional views showing a method of manufacturing the COB package in accordance with an exemplary embodiment of the present invention.
- FIG. 3 shows, in a cross-sectional view, a COB package of a flip chip assembly structure in accordance with an exemplary embodiment of the present invention.
- the COB package 30 is mounted in a card body 9 through one surface of the card body 9 .
- the COB package 30 has metal patterns 31 exposed to the outside of the card body 9 to act as contact terminals of the IC card.
- the metal patterns 31 are formed on an outer surface 32 a of a thin, non-conductive film 32 .
- the metal patterns 31 may be made of copper, for example, and may be plated with, for example, gold.
- the non-conductive film 32 may be made of resin material such as epoxy or polyimide and have a thickness of about 10 ⁇ m to about 20 ⁇ m.
- the non-conductive film 32 has a number of holes 32 c through which the metal patterns 31 are partly exposed.
- An IC chip 33 faces an inner surface 32 b of the non-conductive film 32 . More particularly, an active surface 33 a of the IC chip 33 faces the inner surface 32 b of the non-conductive film 32 .
- Metal bumps 34 are formed on the active surface 33 a of the IC chip 33 .
- the metal bumps 34 are locatable in the holes 32 c of the non-conductive film 32 to thereby mechanically join and electrically couple to the metal patterns 31 . Therefore, the metal bumps 34 may have a height greater than the thickness of the non-conductive film 32 . The height of the metal bumps 34 may be about 40 ⁇ m, for example. Further, the metal bumps 34 may have a width smaller than the diameter of the hole 32 c . For example, if the diameter of a hole 32 c is about 1 mm, the width of the corresponding metal bump 34 can be about 20 ⁇ m.
- the metal bump 34 may be made of gold or other suitable metals.
- the metal bumps 34 are directly connected to the metal patterns 31 through the holes 32 c . It is thereby unnecessary to form additional metal patterns on the inner surface 32 b of the non-conductive film 32 . Further, since the metal bumps 34 replace conventional metal wires; the COB package 30 may have no need of conventional mold resin.
- FIGS. 4A to 4 D show, in cross-sectional views, a method of manufacturing the COB package in accordance with an exemplary embodiment of the present invention. From the description of the method, the structure of the COB package will be further disclosed.
- FIG. 4A illustrates a step of forming the holes 32 c at proper positions of the non-conductive film 32 .
- the positions of the holes 32 c correspond to the locations of the metal bumps on the IC chip.
- the holes 32 c may be formed using suitable piercing tool such as a punch.
- the metal patterns 31 are formed on the outer surface 32 a of the non-conductive film 32 .
- the metal patterns 31 may be formed from a metal plate first bonded to the outer surface 32 a of the non-conductive film 32 and then patterned by photo etching. The bottom of the metal patterns 31 is partly exposed through the holes 32 c for connections with the metal bumps 34 .
- the metal bumps 34 are formed on the active surface 33 a of the IC chip 33 .
- the IC chip 33 has a number of input/output pads (not shown) arranged on the active surface 33 a , and the metal bumps 34 may be formed on the respective input/output pads.
- the metal bumps 34 may be formed using electroplating, stud bumping, or other suitable known bump-forming techniques.
- the IC chip 33 is positioned relative to the inner surface 32 b of the non-conductive film 32 such that the metal bumps 34 enter into the holes 32 c .
- Corresponding ones of the metal bumps 34 and the metal patterns 31 are mechanically joined and electrically coupled to each other with suitable heat, pressure and/or vibration applied thereto.
- a non-conductive adhesive may be interposed between the active surface 33 a of the IC chip 33 and the inner surface 32 b of the film 32 to enhance connection reliability therebetween.
- the non-conductive adhesive may be, for example, a laminated adhesive tape or adhesive paste.
- the COB package according to the present invention has single-sided metal patterns, e.g., formed on only one surface of the non-conductive film. In comparison with conventional double-sided metal patterns, therefore, the COB package of the present invention may have the advantage of reduced production cost. Further, the COB package of embodiments of the present invention may be manufactured through more simplified process since it does not necessarily require additional metal patterns, metal wires and mold resin. As a result, embodiments of the present invention provide a cost-effective IC card.
- the COB package according to embodiments of the present invention adopts the flip chip assembly structure in which the metal bumps provide electrical connections instead of conventional metal wires. Accordingly, embodiments of the present invention may not only avoid poor electrical connections in the COB package, but also improve reliability of the IC card.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
A chip-on-board (COB) package has a flip chip assembly structure and is used for an integrated circuit (IC) card. The COB package has conductive patterns as contact terminals on an outer surface of a non-conductive film, and an IC chip on an inner surface of the film. The film has a number of holes through which the conductive patterns are partly exposed. A number of conductive bumps on an active surface of the IC chip face the inner surface of the film and enter corresponding holes in the non-conductive film to mechanically join and electrically couple to the conductive patterns. The disclosed COB package and a related manufacturing method allow a reduction in production cost, simplified process, better electrical connections, and improved reliability.
Description
- This application is a Divisional of U.S. Ser. No. 11/181,145, filed on Jul. 13, 2005, now pending, which claims priority from Korean Patent Application No. 2004-88783, filed on Nov. 3, 2004, all of which are hereby incorporated by reference in their entirety.
- 1. Field of the Invention
- The present invention relates generally to semiconductor package technology and, more particularly, to a chip-on-board (COB) package having a flip-chip assembly structure and to a manufacturing method thereof.
- 2. Description of the Related Art
- An integrated circuit (IC) card, in which an IC chip is contained, can substitute for a conventional magnetic card. Generally, the IC chip is assembled in the form of typical COB package and then embedded in the IC card.
-
FIG. 1 shows, in a cross-sectional view, a conventional COB package used for the IC card. Referring toFIG. 1 , the COB package 10 mounts in acard body 9 through one surface of thecard body 9. Conductive patterns such asmetal patterns 11 formed on theCOB package 10 and exposed outside thecard body 9 act as contact terminals of the IC card. - The
metal patterns 11 are formed on anouter surface 12 a of a thin,non-conductive film 12. AnIC chip 13 is attached on aninner surface 12 b of thenon-conductive film 12. Thenon-conductive film 12 has several holes 12 c formed near theIC chip 13.Metal wires 14 electrically couple theIC chip 13 to themetal patterns 11 through the holes 12 c in thenon-conductive film 12. TheIC chip 13 and themetal wires 14 are encapsulated in amold resin 15 provided on theinner surface 12 b of thenon-conductive film 12. Themold resin 15 may protect and fix theIC chip 13 and themetal wires 14. - A typical package assembly process may be used to manufacture the aforementioned
conventional COB package 10. Therefore, mass-productivity may be a merit of theconventional COB package 10. However, the IC card can be very thin, e.g., less than one millimeter thick, and can be inherently flexible. Theconventional COB package 10 may tend to be affected by external force. In theconventional COB package 10, anactive surface 13 a of theIC chip 13 faces toward the inside of thecard body 9 while themetal patterns 11 face toward the outside of thecard body 9. This makes the length of themetal wire 14 relatively longer. Often, poorer electrical connections arise fromlonger metal wires 14 in spite of protection by themold resin 15. -
FIG. 2 shows in cross-section another conventional COB package used for the IC card.COB package 20 has a flip chip assembly structure instead of the metal wires and the mold resin as discussed above. - Referring to
FIG. 2 , anactive surface 23 a of anIC chip 23 faces toward anon-conductive film 22. Conductive bumps such asmetal bumps 24 are formed on theactive surface 23 a of theIC chip 23, andsecond metal patterns 21 a are formed on aninner surface 22 b of thenon-conductive film 22. Thesecond metal patterns 21 a are electrically coupled throughinterconnection vias 21 b tofirst metal patterns 21 formed on anouter surface 22 a of thenon-conductive film 22. Themetal bumps 24 are mechanically joined to thesecond metal patterns 21 a, providing electrical paths between theIC chip 23 and thefirst metal patterns 21. -
Metal bumps 24 provide relatively shorter and more reliable electrical paths. The above-discussed flip chip assembly structure may not only have less possibility of poor electrical connections, but also may have no need of the mold resin.Conventional COB package 20, however, necessarily requires thesecond metal patterns 21 a on theinner surface 22 b of thenon-conductive film 22. This represents greater production cost in comparison with the previous example using the metal wires. - The first and
second metal patterns surfaces non-conductive film 22 and then patterned by selective etching in a photolithographic process. Therefore, using thesecond metal patterns 21 a as well as themetal bumps 24 may incur relatively higher production cost in comparison with using the metal wires. The process of forming thesecond metal patterns 21 a may be carried out separately from the process of forming thefirst metal patterns 21. As a result, thisconventional COB package 20 may have no significant advantage in its manufacturing method. - Exemplary, non-limiting embodiments of the present invention provide a structure and a manufacturing method of a chip-on-board (COB) package allowing a reduction in production cost, simplified process, better electrical connections, and improved reliability.
- According to an exemplary embodiment of the present invention, the COB package comprises a non-conductive film, metal patterns, an integrated circuit (IC) chip, and a number of metal bumps. The non-conductive film has a first surface, a second surface opposite to the first surface, and a number of holes. The metal patterns are formed on the first surface of the non-conductive film, but partly exposed through the holes of the non-conductive film. The IC chip has an active surface facing the second surface of the non-conductive film. The metal bumps are formed on the active surface of the IC chip and insertable into the holes of the non-conductive film to mechanically join and electrically couple to the metal patterns.
- In the COB package, the metal bumps may have a height greater than the thickness of the non-conductive film. For example, the height of the metal bump may be about 40 μm, e.g., between about 30 μm and about 50 μm, and the thickness of the non-conductive film may be about 10 μm to about 20 μm.
- Further, the metal bumps may be made of gold and the non-conductive film may be made of epoxy or polyimide. The width of the metal bumps may be about 20 μm and the diameter of the holes may be about 1 mm.
- According to another exemplary embodiment of the present invention, the method of manufacturing a COB package comprises forming holes in a non-conductive film having a first surface and a second surface opposite to the first surface; forming metal patterns on the first surface of the non-conductive film to partly expose the metal patterns through the holes; forming metal bumps on an active surface of an integrated circuit (IC) chip; disposing the IC chip relative to the second surface of the non-conductive film to insert the metal bumps into the holes of the non-conductive film; and mechanically joining and electrically coupling the metal bumps and the metal patterns.
- In the method, the forming of the holes may be carried out using a punch. Further, the forming of the metal patterns may include bonding a metal plate to the first surface of the non-conductive film and thereafter photo-etching the metal plate. Additionally, the forming of the metal bumps may be carried out using electroplating or stud bumping.
- In an alternative embodiment of the invention, the method may further comprise, before the joining of the metal bumps, providing a non-conductive adhesive between the active surface of the IC chip and the second surface of the non-conductive film.
- Exemplary, non-limiting embodiments of the present invention provide an IC card having a thin and flexible card body and the above-discussed COB package. The COB package is mounted in the card body through one surface of the card body, and the metal patterns of the package are exposed outside the card body to act as contact terminals of the IC card.
-
FIG. 1 is a cross-sectional view showing a conventional COB package used for an IC card. -
FIG. 2 is a cross-sectional view showing another convention COB package used for the IC card. -
FIG. 3 is a cross-sectional view showing a COB package of a flip chip assembly structure in accordance with an exemplary embodiment of the present invention. -
FIGS. 4A to 4D are cross-sectional views showing a method of manufacturing the COB package in accordance with an exemplary embodiment of the present invention. - Exemplary, non-limiting embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings. This invention, however, may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, the disclosed embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The principles and features of this invention may be employed in varied and numerous embodiments without departing from the scope of the invention.
- In this disclosure, well-known structures and processes are not described or illustrated in detail to avoid obscuring the present invention. Furthermore, the figures in the drawings are not drawn to scale. Rather, for simplicity and clarity of illustration, the dimensions of some of the elements are exaggerated relative to other elements. Like reference numerals are used for like and corresponding parts of the various drawings.
-
FIG. 3 shows, in a cross-sectional view, a COB package of a flip chip assembly structure in accordance with an exemplary embodiment of the present invention. - Referring to
FIG. 3 , theCOB package 30 is mounted in acard body 9 through one surface of thecard body 9. TheCOB package 30 hasmetal patterns 31 exposed to the outside of thecard body 9 to act as contact terminals of the IC card. Themetal patterns 31 are formed on anouter surface 32 a of a thin,non-conductive film 32. Themetal patterns 31 may be made of copper, for example, and may be plated with, for example, gold. Thenon-conductive film 32 may be made of resin material such as epoxy or polyimide and have a thickness of about 10 μm to about 20 μm. - The
non-conductive film 32 has a number ofholes 32 c through which themetal patterns 31 are partly exposed. AnIC chip 33 faces aninner surface 32 b of thenon-conductive film 32. More particularly, anactive surface 33 a of theIC chip 33 faces theinner surface 32 b of thenon-conductive film 32. Metal bumps 34 are formed on theactive surface 33 a of theIC chip 33. - The metal bumps 34 are locatable in the
holes 32 c of thenon-conductive film 32 to thereby mechanically join and electrically couple to themetal patterns 31. Therefore, the metal bumps 34 may have a height greater than the thickness of thenon-conductive film 32. The height of the metal bumps 34 may be about 40 μm, for example. Further, the metal bumps 34 may have a width smaller than the diameter of thehole 32 c. For example, if the diameter of ahole 32 c is about 1 mm, the width of the correspondingmetal bump 34 can be about 20 μm. Themetal bump 34 may be made of gold or other suitable metals. - As discussed above, the metal bumps 34 are directly connected to the
metal patterns 31 through theholes 32 c. It is thereby unnecessary to form additional metal patterns on theinner surface 32 b of thenon-conductive film 32. Further, since the metal bumps 34 replace conventional metal wires; theCOB package 30 may have no need of conventional mold resin. -
FIGS. 4A to 4D show, in cross-sectional views, a method of manufacturing the COB package in accordance with an exemplary embodiment of the present invention. From the description of the method, the structure of the COB package will be further disclosed. -
FIG. 4A illustrates a step of forming theholes 32 c at proper positions of thenon-conductive film 32. The positions of theholes 32 c correspond to the locations of the metal bumps on the IC chip. Theholes 32 c may be formed using suitable piercing tool such as a punch. - In
FIG. 4B , themetal patterns 31 are formed on theouter surface 32 a of thenon-conductive film 32. Themetal patterns 31 may be formed from a metal plate first bonded to theouter surface 32 a of thenon-conductive film 32 and then patterned by photo etching. The bottom of themetal patterns 31 is partly exposed through theholes 32 c for connections with the metal bumps 34. - As shown in
FIG. 4C , the metal bumps 34 are formed on theactive surface 33 a of theIC chip 33. As well known in the art, theIC chip 33 has a number of input/output pads (not shown) arranged on theactive surface 33 a, and the metal bumps 34 may be formed on the respective input/output pads. The metal bumps 34 may be formed using electroplating, stud bumping, or other suitable known bump-forming techniques. - Thereafter, as shown in
FIG. 4D , theIC chip 33 is positioned relative to theinner surface 32 b of thenon-conductive film 32 such that the metal bumps 34 enter into theholes 32 c. Corresponding ones of the metal bumps 34 and themetal patterns 31 are mechanically joined and electrically coupled to each other with suitable heat, pressure and/or vibration applied thereto. - In an alternative embodiment, before the metal bumps 34 are joined to the
metal patterns 31, a non-conductive adhesive may be interposed between theactive surface 33 a of theIC chip 33 and theinner surface 32 b of thefilm 32 to enhance connection reliability therebetween. The non-conductive adhesive may be, for example, a laminated adhesive tape or adhesive paste. - As discussed above, the COB package according to the present invention has single-sided metal patterns, e.g., formed on only one surface of the non-conductive film. In comparison with conventional double-sided metal patterns, therefore, the COB package of the present invention may have the advantage of reduced production cost. Further, the COB package of embodiments of the present invention may be manufactured through more simplified process since it does not necessarily require additional metal patterns, metal wires and mold resin. As a result, embodiments of the present invention provide a cost-effective IC card.
- In addition, the COB package according to embodiments of the present invention adopts the flip chip assembly structure in which the metal bumps provide electrical connections instead of conventional metal wires. Accordingly, embodiments of the present invention may not only avoid poor electrical connections in the COB package, but also improve reliability of the IC card.
- While this invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (6)
1. A method of manufacturing a chip-on-board package, the method comprising:
forming a plurality of holes through a non-conductive film having a first surface and a second surface opposite the first surface;
forming conductive patterns on the first surface of the non-conductive film and exposed through the holes;
forming conductive bumps on an active surface of an integrated circuit chip; and
disposing the integrated circuit chip relative to the second surface of the non-conductive film to make insertable the conductive bumps into the holes of the non-conductive film.
2. A method of claim 1 , further comprising mechanically joining and electrically coupling the conductive bumps and the conductive patterns by way of the holes.
3. The method of claim 2 , wherein the forming of the holes is carried out using a punch.
4. The method of claim 2 , wherein the forming of the conductive patterns includes bonding a metal plate to the first surface of the non-conductive film and photo-etching the metal plate.
5. The method of claim 2 , wherein the forming of the conductive bumps is carried out using at least one of electroplating and stud bumping.
6. The method of claim 2 , further comprising:
interposing a non-conductive adhesive between the active surface of the integrated circuit chip and the second surface of the non-conductive film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/941,421 US20080081456A1 (en) | 2004-11-03 | 2007-11-16 | Chip-on-board package having flip chip assembly structure and manufacturing method thereof |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR20040088783A KR100610144B1 (en) | 2004-11-03 | 2004-11-03 | Manufacturing method of chip-on-board package having flip chip assembly structure |
KR2004-88783 | 2004-11-03 | ||
US11/181,145 US7315086B2 (en) | 2004-11-03 | 2005-07-13 | Chip-on-board package having flip chip assembly structure and manufacturing method thereof |
US11/941,421 US20080081456A1 (en) | 2004-11-03 | 2007-11-16 | Chip-on-board package having flip chip assembly structure and manufacturing method thereof |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/181,145 Division US7315086B2 (en) | 2004-11-03 | 2005-07-13 | Chip-on-board package having flip chip assembly structure and manufacturing method thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
US20080081456A1 true US20080081456A1 (en) | 2008-04-03 |
Family
ID=36260859
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/181,145 Active 2025-09-28 US7315086B2 (en) | 2004-11-03 | 2005-07-13 | Chip-on-board package having flip chip assembly structure and manufacturing method thereof |
US11/941,421 Abandoned US20080081456A1 (en) | 2004-11-03 | 2007-11-16 | Chip-on-board package having flip chip assembly structure and manufacturing method thereof |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/181,145 Active 2025-09-28 US7315086B2 (en) | 2004-11-03 | 2005-07-13 | Chip-on-board package having flip chip assembly structure and manufacturing method thereof |
Country Status (2)
Country | Link |
---|---|
US (2) | US7315086B2 (en) |
KR (1) | KR100610144B1 (en) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100499097C (en) * | 2006-08-21 | 2009-06-10 | 南茂科技股份有限公司 | High frequency integrated circuit package structure with improved embedded bump connectivity and method of manufacture |
KR100891330B1 (en) * | 2007-02-21 | 2009-03-31 | 삼성전자주식회사 | A semiconductor package device, a method of manufacturing a semiconductor package, a card device having a semiconductor package device and a method of manufacturing a card device having a semiconductor package device |
US7745260B2 (en) * | 2008-09-22 | 2010-06-29 | Freescale Semiconductor, Inc. | Method of forming semiconductor package |
US9508626B2 (en) * | 2010-04-23 | 2016-11-29 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming openings in thermally-conductive frame of FO-WLCSP to dissipate heat and reduce package height |
CN102646606B (en) * | 2011-02-16 | 2014-12-24 | 中电智能卡有限责任公司 | Packaging method of integrated circuit (IC) card module |
EP3151167B1 (en) | 2015-09-30 | 2020-05-20 | Nxp B.V. | Dual-interface ic card module |
CN108963035B (en) * | 2018-07-30 | 2020-04-03 | 安徽科技学院 | Manufacturing method of COB (chip on Board) packaged photoelectric chip with side protection |
Citations (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3832769A (en) * | 1971-05-26 | 1974-09-03 | Minnesota Mining & Mfg | Circuitry and method |
US5504035A (en) * | 1989-08-28 | 1996-04-02 | Lsi Logic Corporation | Process for solder ball interconnecting a semiconductor device to a substrate using a noble metal foil embedded interposer substrate |
US5742100A (en) * | 1995-03-27 | 1998-04-21 | Motorola, Inc. | Structure having flip-chip connected substrates |
US5990546A (en) * | 1994-12-29 | 1999-11-23 | Nitto Denko Corporation | Chip scale package type of semiconductor device |
US6046073A (en) * | 1997-11-26 | 2000-04-04 | Siemens Aktiengesellschaft | Process for producing very thin semiconductor chips |
US6100112A (en) * | 1998-05-28 | 2000-08-08 | The Furukawa Electric Co., Ltd. | Method of manufacturing a tape carrier with bump |
US6285081B1 (en) * | 1999-07-13 | 2001-09-04 | Micron Technology, Inc. | Deflectable interconnect |
US6323058B1 (en) * | 1997-07-30 | 2001-11-27 | Hitachi Cable Ltd. | Semiconductor device, tab tape for semiconductor device, method of manufacturing the tab tape and method of manufacturing the semiconductor device |
US6433409B2 (en) * | 1998-03-18 | 2002-08-13 | Hitachi Cable Ltd. | Semiconductor device, lead-patterning substrate, and electronics device, and method for fabricating same |
US6492737B1 (en) * | 2000-08-31 | 2002-12-10 | Hitachi, Ltd. | Electronic device and a method of manufacturing the same |
US6624006B2 (en) * | 1999-06-18 | 2003-09-23 | Micron Technology, Inc. | Methods of attaching a semiconductor chip to a leadframe with a footprint of about the same size as the chip |
US6894888B2 (en) * | 2001-06-07 | 2005-05-17 | Ngk Insulators, Ltd. | Multilayer board having precise perforations and circuit substrate having precise through-holes |
US6995476B2 (en) * | 1998-07-01 | 2006-02-07 | Seiko Epson Corporation | Semiconductor device, circuit board and electronic instrument that include an adhesive with conductive particles therein |
US7129585B2 (en) * | 2003-01-30 | 2006-10-31 | Samsung Electronics Co., Ltd. | Semiconductor device and method of packaging the same |
US7348215B2 (en) * | 2002-03-04 | 2008-03-25 | Micron Technology, Inc. | Methods for assembly and packaging of flip chip configured dice with interposer |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE69118308T2 (en) * | 1990-10-24 | 1996-08-08 | Nippon Electric Co | Method of making an electrical connection for an integrated circuit |
JPH0547847A (en) | 1991-08-09 | 1993-02-26 | Seiko Epson Corp | Semiconductor device |
JP2606110B2 (en) | 1993-12-15 | 1997-04-30 | 日本電気株式会社 | Multilayer substrate and method of manufacturing the same |
KR19980025889A (en) | 1996-10-05 | 1998-07-15 | 김광호 | Bump connection structure between a semiconductor chip and a substrate with a polymer layer interposed therebetween |
JP2002231762A (en) * | 2001-02-01 | 2002-08-16 | Toppan Forms Co Ltd | Mounting method for ic chip and ic chip mounting body |
JP2003086629A (en) | 2001-09-13 | 2003-03-20 | Hitachi Ltd | COF semiconductor device and method of manufacturing the same |
-
2004
- 2004-11-03 KR KR20040088783A patent/KR100610144B1/en not_active Expired - Lifetime
-
2005
- 2005-07-13 US US11/181,145 patent/US7315086B2/en active Active
-
2007
- 2007-11-16 US US11/941,421 patent/US20080081456A1/en not_active Abandoned
Patent Citations (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3832769A (en) * | 1971-05-26 | 1974-09-03 | Minnesota Mining & Mfg | Circuitry and method |
US5504035A (en) * | 1989-08-28 | 1996-04-02 | Lsi Logic Corporation | Process for solder ball interconnecting a semiconductor device to a substrate using a noble metal foil embedded interposer substrate |
US5990546A (en) * | 1994-12-29 | 1999-11-23 | Nitto Denko Corporation | Chip scale package type of semiconductor device |
US5742100A (en) * | 1995-03-27 | 1998-04-21 | Motorola, Inc. | Structure having flip-chip connected substrates |
US6323058B1 (en) * | 1997-07-30 | 2001-11-27 | Hitachi Cable Ltd. | Semiconductor device, tab tape for semiconductor device, method of manufacturing the tab tape and method of manufacturing the semiconductor device |
US6046073A (en) * | 1997-11-26 | 2000-04-04 | Siemens Aktiengesellschaft | Process for producing very thin semiconductor chips |
US6433409B2 (en) * | 1998-03-18 | 2002-08-13 | Hitachi Cable Ltd. | Semiconductor device, lead-patterning substrate, and electronics device, and method for fabricating same |
US6100112A (en) * | 1998-05-28 | 2000-08-08 | The Furukawa Electric Co., Ltd. | Method of manufacturing a tape carrier with bump |
US6995476B2 (en) * | 1998-07-01 | 2006-02-07 | Seiko Epson Corporation | Semiconductor device, circuit board and electronic instrument that include an adhesive with conductive particles therein |
US6624006B2 (en) * | 1999-06-18 | 2003-09-23 | Micron Technology, Inc. | Methods of attaching a semiconductor chip to a leadframe with a footprint of about the same size as the chip |
US6285081B1 (en) * | 1999-07-13 | 2001-09-04 | Micron Technology, Inc. | Deflectable interconnect |
US6492737B1 (en) * | 2000-08-31 | 2002-12-10 | Hitachi, Ltd. | Electronic device and a method of manufacturing the same |
US6894888B2 (en) * | 2001-06-07 | 2005-05-17 | Ngk Insulators, Ltd. | Multilayer board having precise perforations and circuit substrate having precise through-holes |
US7348215B2 (en) * | 2002-03-04 | 2008-03-25 | Micron Technology, Inc. | Methods for assembly and packaging of flip chip configured dice with interposer |
US7129585B2 (en) * | 2003-01-30 | 2006-10-31 | Samsung Electronics Co., Ltd. | Semiconductor device and method of packaging the same |
Also Published As
Publication number | Publication date |
---|---|
US7315086B2 (en) | 2008-01-01 |
US20060091511A1 (en) | 2006-05-04 |
KR100610144B1 (en) | 2006-08-09 |
KR20060039613A (en) | 2006-05-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP3481444B2 (en) | Semiconductor device and manufacturing method thereof | |
KR100600683B1 (en) | Semiconductor device and manufacturing method thereof | |
US6515357B2 (en) | Semiconductor package and semiconductor package fabrication method | |
US6486544B1 (en) | Semiconductor device and method manufacturing the same, circuit board, and electronic instrument | |
JP4322844B2 (en) | Semiconductor device and stacked semiconductor device | |
US6977441B2 (en) | Interconnect substrate and method of manufacture thereof, electronic component and method of manufacturing thereof, circuit board and electronic instrument | |
US7161242B2 (en) | Semiconductor device, semiconductor device substrate, and manufacturing method thereof that can increase reliability in mounting a semiconductor element | |
US8329507B2 (en) | Semiconductor package, integrated circuit cards incorporating the semiconductor package, and method of manufacturing the same | |
JP5713598B2 (en) | Socket and manufacturing method thereof | |
US5612259A (en) | Method for manufacturing a semiconductor device wherein a semiconductor chip is mounted on a lead frame | |
US20060049495A1 (en) | Semiconductor package and laminated semiconductor package | |
JP2001077293A (en) | Semiconductor device | |
JP2002110898A (en) | Semiconductor device | |
KR20030083553A (en) | Semiconductor device and manufacturing method thereof | |
US6521483B1 (en) | Semiconductor device, method of manufacture thereof, circuit board, and electronic device | |
US20080081456A1 (en) | Chip-on-board package having flip chip assembly structure and manufacturing method thereof | |
JP2006156436A (en) | Semiconductor device and its manufacturing method | |
JPH10199924A (en) | Semiconductor chip package, method of manufacturing the same, and laminated package using the same | |
US20080251944A1 (en) | Semiconductor device | |
JP2001308258A (en) | Semiconductor package and method of manufacturing it | |
US10163820B2 (en) | Chip carrier and method thereof | |
JP2008288327A (en) | Semiconductor device and manufacturing method thereof | |
US7847414B2 (en) | Chip package structure | |
KR20040045017A (en) | Semiconductor device and semiconductor device manufacturing method | |
KR100533847B1 (en) | Stacked flip chip package using carrier tape |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |