US20080070429A1 - Surface mounted electronic component - Google Patents
Surface mounted electronic component Download PDFInfo
- Publication number
- US20080070429A1 US20080070429A1 US11/567,593 US56759306A US2008070429A1 US 20080070429 A1 US20080070429 A1 US 20080070429A1 US 56759306 A US56759306 A US 56759306A US 2008070429 A1 US2008070429 A1 US 2008070429A1
- Authority
- US
- United States
- Prior art keywords
- soldering
- electronic component
- peripheral wall
- mounted electronic
- cutout
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000005476 soldering Methods 0.000 claims abstract description 126
- 230000002093 peripheral effect Effects 0.000 claims abstract description 53
- 230000000694 effects Effects 0.000 claims abstract description 19
- 229910000679 solder Inorganic materials 0.000 claims abstract description 19
- 238000002844 melting Methods 0.000 abstract description 8
- 230000008018 melting Effects 0.000 abstract description 8
- 230000003014 reinforcing effect Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3442—Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09145—Edge details
- H05K2201/09181—Notches in edge pads
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10636—Leadless chip, e.g. chip capacitor or resistor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10727—Leadless chip carrier [LCC], e.g. chip-modules for cards
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Definitions
- the present invention generally relates to electronic components, and more particularly relates to a surface mounted electronic component.
- ‘Tombstoning’ also known as Drawbridge effect or Manhattan Skyline effect, is considered a common defect in surface mounting technology. ‘Tombstoning’, i.e., a phenomenon where electronic components erect like tombstones, is due to unbalanced surface tension of two soldered end portions of an electronic component. Particularly, when a low mass chip-type electronic component is soldered on a substrate such as a printed circuit board, the unbalanced surface tension may easily occur and draw one soldered end portion to the substrate and the other soldered end portion free, thus causing ‘tombstoning’.
- the unbalanced surface tension of two soldered end portions occurs due to poor soldering pad design, non-uniform heating of soldering surfaces, low reactivity of solder, non-uniform application of solder and so on.
- the surface mounted electronic component has a block body.
- the block body includes a bottom soldering surface, a top surface opposite to the bottom soldering surface and a peripheral wall.
- the bottom soldering surface defines a first soldering area and a second soldering area.
- the peripheral wall includes a first peripheral wall portion and a second peripheral wall portion.
- the first peripheral wall portion adjoins the first soldering area of the bottom soldering surface and has a first cutout defined between the first peripheral wall portion and the first soldering area of the bottom soldering surface.
- the second peripheral wall portion adjoins the second soldering area of the bottom soldering surface and has a second cutout defined between the second peripheral wall portion and the second soldering area of the bottom soldering surface.
- FIG. 1 is a schematic view of a surface mounted electronic component according to a first embodiment
- FIG. 2 is a bottom view of the surface mounted electronic component according to the first embodiment
- FIG. 3 is a schematic view of a surface mounted electronic component according to a second embodiment
- FIG. 4 is a bottom view of the surface mounted electronic component according to the second embodiment
- FIG. 5 is a schematic view of a surface mounted electronic component according to a third embodiment
- FIG. 6 is a bottom view of the surface mounted electronic component according to the third embodiment.
- FIG. 7 is a schematic view of a surface mounted electronic component according to a fourth embodiment
- FIG. 8 is a bottom view of the surface mounted electronic component according to the fourth embodiment.
- FIG. 9 is a schematic view of a typical surface mounted electronic component.
- FIG. 10 is a schematic view of ‘tombstoning’ on a typical surface mounted electronic component.
- FIG. 1 and FIG. 2 a surface mounted electronic component 20 according to a first exemplary embodiment is shown.
- the surface mounted electronic component 20 has a block body 200 .
- the block body 200 has a polyhedron configuration.
- the block body 200 is a rectangular parallelepiped having a soldering bottom surface 21 , a top surface 22 opposite to the soldering bottom surface 21 and a peripheral wall 23 .
- the peripheral wall 23 adjoins the soldering bottom surface 21 and the top surface 22 simultaneously.
- the peripheral wall 23 includes a first peripheral wall portion 231 and a second peripheral wall portion 232 opposite to the first peripheral wall portion 231 , a third peripheral wall portion 233 and a fourth peripheral wall portion 234 opposite to the third sidewall section 233 . Therefore, the first peripheral wall portion 231 , the second peripheral wall portion 232 , the third peripheral wall portion 233 and the fourth peripheral wall portion 234 adjoin both the soldering bottom surface 21 and the top surface 22 .
- the soldering bottom surface 21 defines a first soldering area 211 and a second soldering area 212 .
- the first soldering area 211 adjoins the first peripheral wall portion 231 and the second soldering area 212 adjoins the second peripheral wall portion 232 .
- the first soldering area 211 and the second soldering area 212 are symmetrical.
- a first cutout 24 is defined between the first peripheral wall portion 231 and the first soldering area 211 of the bottom soldering surface 21 .
- a second cutout 25 is defined between the second peripheral wall portion 232 and the second soldering area 212 of the bottom soldering surface 21 .
- the first cutout 24 should extend in a direction perpendicular to the first soldering area 211
- the second cutout 25 should extend in a direction perpendicular to the second soldering area 212 .
- the first/second cutout could be a through hole or a blind hole defined in the first/second soldering area of the bottom soldering surface, and should be considered to be within the scope of the present invention.
- Cross-section shape of the first cutout 24 and the second cutout 25 taken normal to the bottom soldering surface 21 can be selected from the group consisting of arc-shaped, U-shaped, V-shaped, and broken-lines-shaped.
- cross-section shape of the first cutout 24 taken normal to the bottom soldering surface is arc-shaped and cross-section shape of the second cutout 25 taken normal to the bottom soldering surface is also arc-shaped.
- first soldering pad 213 and a second soldering pad 214 can be attached on the first soldering area 211 and the second soldering area 212 respectively.
- the first soldering pad 213 and the second soldering pad 214 are configured for facilitating soldering of the surface mounted electronic component 20 .
- the surface mounted electronic component 20 can be mounted by interposing solder between the soldering areas and a circuit board and melting the solder to provide mechanical and electrical connections between the surface mounted electronic component 20 and circuits on the circuit board.
- Capillary effect can occur due to the thin first cutout 24 and the thin second cutout 25 like capillary tubes.
- Capillary effect is the ability of a substance to draw a liquid upwards against the force of gravity. Due to capillary effect the melting solder on the first soldering area 211 can climb up the first cutout 24 along the inside wall thereof, and the melting solder on the second soldering area 212 also can climb up the second cutout 25 along the inside wall thereof. Therefore, the first cutout 24 and the second cutout 25 can be filled with solder, thereby increasing area the surface mounted electronic component 20 contacting with the solder.
- temperature of downside portion of the first cutout 24 adjoining the soldering bottom surface 21 is higher than temperature of upside portion of the first cutout 24 adjoining the top surface 21
- temperature of downside portion of the second cutout 25 adjoining the soldering bottom surface 21 is higher than temperature of upside portion of the second cutout 25 adjoining the top surface 21 .
- Temperature difference causes a ‘chimney effect’.
- the ‘chimney effect’ is a tendency of heated air to rise in a duct or other vertical passage that results from thermal differences.
- Thermal differences between the downside portion and upside portion of the cutouts will result in pressure differences, because warm air is less dense than cold air. The less dense warm air in the downside portion will rise because of its thermal buoyancy, thereby making the melting solder climb up the first cutout 24 and the second cutout 25 along the inside wall thereof respectively and fill the first cutout 24 and the second cutout 25 respectively.
- the solder filled into the first cutout 24 and the second cutout 25 connect with the solder between the soldering bottom surface 21 and the circuit board, thereby forming a whole.
- the unbalanced surface tension between the first soldering area 211 and the second soldering area 212 of the surface mounted electronic component 20 can be balanced, thereby avoiding ‘tombstoning’.
- the surface mounted electronic component 20 can be mounted on the circuit board hard.
- cutouts can also be defined in the third peripheral wall portion 233 and the fourth peripheral wall portion 234 respectively.
- area the surface mounted electronic component 20 contacting with the solder can be further increased, thereby reinforcing mounting of the surface mounted electronic component 20 on the circuit board.
- a surface mounted electronic component 30 according to a second exemplary embodiment is shown.
- the surface mounted electronic component 30 is similar to the surface mounted electronic component 20 in the first exemplary embodiment except that a first cutout 34 is defined between the first soldering area 311 of the bottom soldering surface 31 and the top surface 32 and a second cutout 35 is also defined between the second soldering area 312 of the bottom soldering surface 31 and the top surface 32 .
- a surface mounted electronic component 40 according to a third exemplary embodiment is shown.
- the surface mounted electronic component 40 is similar to the surface mounted electronic component 20 in the first exemplary embodiment except that a number of first cutouts 44 are defined between the first peripheral wall portion 431 and the first soldering area 411 of the bottom soldering surface 41 and a number of second cutouts 45 are defined between the first peripheral wall portion 431 and the first soldering area 411 of the bottom soldering surface 41 .
- the melting solder on a first soldering area 411 can climb up the first cutouts 44 along the inside wall thereof, and the melting solder on a second soldering area 412 can also climb up the second cutouts 45 along the inside wall thereof.
- area of the surface mounted electronic component 40 contacting with the solder can be further increased, thereby further balancing the surface tension between the first soldering area 411 and the second soldering area 412 of the surface mounted electronic component 40 and reinforcing mounting of the surface mounted electronic component 40 on the circuit board.
- the surface mounted electronic component can have a configuration of any other structure.
- a surface electronic component 50 according to a fourth exemplary embodiment is shown.
- the surface electronic component 50 has a block body 500 .
- the block body 500 is a cylinder having a soldering bottom surface 51 , a top surface 52 opposite to the soldering bottom surface 51 and a peripheral wall 53 .
- the peripheral wall 53 adjoins the soldering bottom surface 21 and the top surface 22 simultaneously.
- the peripheral wall 53 includes a first peripheral wall portion 531 and a second peripheral wall portion 532 opposite to the first peripheral wall portion 531 . Therefore, the first peripheral wall portion 531 and the second peripheral wall portion 532 adjoin both the soldering bottom surface 51 and the top surface 52 .
- the soldering bottom surface 51 defines a first soldering area 511 and a second soldering area 512 .
- the first soldering area 511 adjoins the first peripheral wall portion 531 and the second soldering area 512 adjoins the second peripheral wall portion 532 .
- the first soldering area 511 and the second soldering area 512 are symmetrical.
- a first cutout 54 is defined between the first peripheral wall portion 531 and the first soldering area 511 of the bottom soldering surface 51 and a second cutout 55 is defined between the first peripheral wall portion 531 and the first soldering area 511 of the bottom soldering surface 51 .
- the first cutout 54 is symmetrical to the second cutout 55 .
- first cutout 54 can be defined between the first soldering area 511 of the bottom soldering surface 21 and the top surface 52
- the second cutout 55 can be defined between the second soldering area 512 of the bottom soldering surface 51 and the top surface 52
- first cutout 54 should extend in a direction perpendicular to the first soldering area 511
- second cutout 55 should extend in a direction perpendicular to the second soldering area 512
- Cross-section shape of the first cutout 54 and the second cutout 55 taken normal to the bottom soldering surface 51 can be selected from the group consisting of arc-shaped, U-shaped, V-shaped, and broken-lines-shaped.
- cross-section shape of the first cutout 54 taken normal to the bottom soldering surface 51 is arc-shaped and cross-section shape of the second cutout 55 taken normal to the bottom soldering surface 51 is also arc-shaped.
- a first soldering pad 513 and a second soldering pad 514 can be attached on the first soldering area 511 and the second soldering area 512 respectively, thereby facilitating soldering of the surface mounted electronic component 50 .
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
- The present invention generally relates to electronic components, and more particularly relates to a surface mounted electronic component.
- ‘Tombstoning’, also known as Drawbridge effect or Manhattan Skyline effect, is considered a common defect in surface mounting technology. ‘Tombstoning’, i.e., a phenomenon where electronic components erect like tombstones, is due to unbalanced surface tension of two soldered end portions of an electronic component. Particularly, when a low mass chip-type electronic component is soldered on a substrate such as a printed circuit board, the unbalanced surface tension may easily occur and draw one soldered end portion to the substrate and the other soldered end portion free, thus causing ‘tombstoning’.
- Generally, the unbalanced surface tension of two soldered end portions occurs due to poor soldering pad design, non-uniform heating of soldering surfaces, low reactivity of solder, non-uniform application of solder and so on.
- With the current trend toward miniaturization of electronic devices there is a concomitant trend toward reducing the size of the electronic components themselves. The reduction in size and mass of electronic components has been a significant aid in the miniaturization process but has created problems such as ‘tombstoning’. Referring to
FIG. 9 andFIG. 10 , such a typicalelectronic component 10 is prone to tombstoning on a printedcircuit board 12 due to unbalanced surface tension of two soldered end portions. ‘Tombstoning’ can cause electric connections between the electronic component and circuits to be broken, resulting in the electronic component losing its functions and causing a mounting failure. - What is needed, therefore, is a surface mounted electronic component having ability of avoiding ‘tombstoning’.
- One preferred embodiment provides a surface mounted electronic component. The surface mounted electronic component has a block body. The block body includes a bottom soldering surface, a top surface opposite to the bottom soldering surface and a peripheral wall. The bottom soldering surface defines a first soldering area and a second soldering area. The peripheral wall includes a first peripheral wall portion and a second peripheral wall portion. The first peripheral wall portion adjoins the first soldering area of the bottom soldering surface and has a first cutout defined between the first peripheral wall portion and the first soldering area of the bottom soldering surface. The second peripheral wall portion adjoins the second soldering area of the bottom soldering surface and has a second cutout defined between the second peripheral wall portion and the second soldering area of the bottom soldering surface.
- Many aspects of the present embodiments can be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the present embodiments. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views.
-
FIG. 1 is a schematic view of a surface mounted electronic component according to a first embodiment; -
FIG. 2 is a bottom view of the surface mounted electronic component according to the first embodiment; -
FIG. 3 is a schematic view of a surface mounted electronic component according to a second embodiment; -
FIG. 4 is a bottom view of the surface mounted electronic component according to the second embodiment; -
FIG. 5 is a schematic view of a surface mounted electronic component according to a third embodiment; -
FIG. 6 is a bottom view of the surface mounted electronic component according to the third embodiment; -
FIG. 7 is a schematic view of a surface mounted electronic component according to a fourth embodiment; -
FIG. 8 is a bottom view of the surface mounted electronic component according to the fourth embodiment; -
FIG. 9 is a schematic view of a typical surface mounted electronic component; and -
FIG. 10 is a schematic view of ‘tombstoning’ on a typical surface mounted electronic component. - Embodiments will now be described in detail below and with reference to the drawings.
- Referring to
FIG. 1 andFIG. 2 , a surface mountedelectronic component 20 according to a first exemplary embodiment is shown. - The surface mounted
electronic component 20 has ablock body 200. Theblock body 200 has a polyhedron configuration. In the embodiment, theblock body 200 is a rectangular parallelepiped having a solderingbottom surface 21, atop surface 22 opposite to the solderingbottom surface 21 and aperipheral wall 23. Theperipheral wall 23 adjoins the solderingbottom surface 21 and thetop surface 22 simultaneously. Theperipheral wall 23 includes a firstperipheral wall portion 231 and a secondperipheral wall portion 232 opposite to the firstperipheral wall portion 231, a thirdperipheral wall portion 233 and a fourthperipheral wall portion 234 opposite to thethird sidewall section 233. Therefore, the firstperipheral wall portion 231, the secondperipheral wall portion 232, the thirdperipheral wall portion 233 and the fourthperipheral wall portion 234 adjoin both the solderingbottom surface 21 and thetop surface 22. - The soldering
bottom surface 21 defines afirst soldering area 211 and asecond soldering area 212. Thefirst soldering area 211 adjoins the firstperipheral wall portion 231 and thesecond soldering area 212 adjoins the secondperipheral wall portion 232. Thefirst soldering area 211 and thesecond soldering area 212 are symmetrical. - A
first cutout 24 is defined between the firstperipheral wall portion 231 and thefirst soldering area 211 of thebottom soldering surface 21. Asecond cutout 25 is defined between the secondperipheral wall portion 232 and thesecond soldering area 212 of thebottom soldering surface 21. Preferably thefirst cutout 24 should extend in a direction perpendicular to thefirst soldering area 211, and thesecond cutout 25 should extend in a direction perpendicular to thesecond soldering area 212. Alternatively, the first/second cutout could be a through hole or a blind hole defined in the first/second soldering area of the bottom soldering surface, and should be considered to be within the scope of the present invention. Cross-section shape of thefirst cutout 24 and thesecond cutout 25 taken normal to thebottom soldering surface 21 can be selected from the group consisting of arc-shaped, U-shaped, V-shaped, and broken-lines-shaped. In the embodiment, cross-section shape of thefirst cutout 24 taken normal to the bottom soldering surface is arc-shaped and cross-section shape of thesecond cutout 25 taken normal to the bottom soldering surface is also arc-shaped. - Additionally, a
first soldering pad 213 and asecond soldering pad 214 can be attached on thefirst soldering area 211 and thesecond soldering area 212 respectively. Thefirst soldering pad 213 and thesecond soldering pad 214 are configured for facilitating soldering of the surface mountedelectronic component 20. - The surface mounted
electronic component 20 can be mounted by interposing solder between the soldering areas and a circuit board and melting the solder to provide mechanical and electrical connections between the surface mountedelectronic component 20 and circuits on the circuit board. - Capillary effect can occur due to the thin
first cutout 24 and the thinsecond cutout 25 like capillary tubes. Capillary effect is the ability of a substance to draw a liquid upwards against the force of gravity. Due to capillary effect the melting solder on thefirst soldering area 211 can climb up thefirst cutout 24 along the inside wall thereof, and the melting solder on thesecond soldering area 212 also can climb up thesecond cutout 25 along the inside wall thereof. Therefore, thefirst cutout 24 and thesecond cutout 25 can be filled with solder, thereby increasing area the surface mountedelectronic component 20 contacting with the solder. - Whilst melting the solder, temperature of downside portion of the
first cutout 24 adjoining the solderingbottom surface 21 is higher than temperature of upside portion of thefirst cutout 24 adjoining thetop surface 21, and temperature of downside portion of thesecond cutout 25 adjoining the solderingbottom surface 21 is higher than temperature of upside portion of thesecond cutout 25 adjoining thetop surface 21. Temperature difference causes a ‘chimney effect’. The ‘chimney effect’ is a tendency of heated air to rise in a duct or other vertical passage that results from thermal differences. Thermal differences between the downside portion and upside portion of the cutouts will result in pressure differences, because warm air is less dense than cold air. The less dense warm air in the downside portion will rise because of its thermal buoyancy, thereby making the melting solder climb up thefirst cutout 24 and thesecond cutout 25 along the inside wall thereof respectively and fill thefirst cutout 24 and thesecond cutout 25 respectively. - The solder filled into the
first cutout 24 and thesecond cutout 25 connect with the solder between the solderingbottom surface 21 and the circuit board, thereby forming a whole. Thus the unbalanced surface tension between thefirst soldering area 211 and thesecond soldering area 212 of the surface mountedelectronic component 20 can be balanced, thereby avoiding ‘tombstoning’. As a result, the surface mountedelectronic component 20 can be mounted on the circuit board hard. - Additionally, cutouts can also be defined in the third
peripheral wall portion 233 and the fourthperipheral wall portion 234 respectively. Thus, area the surface mountedelectronic component 20 contacting with the solder can be further increased, thereby reinforcing mounting of the surface mountedelectronic component 20 on the circuit board. - Referring to
FIG. 3 andFIG. 4 , a surface mountedelectronic component 30 according to a second exemplary embodiment is shown. The surface mountedelectronic component 30 is similar to the surface mountedelectronic component 20 in the first exemplary embodiment except that afirst cutout 34 is defined between thefirst soldering area 311 of thebottom soldering surface 31 and thetop surface 32 and asecond cutout 35 is also defined between thesecond soldering area 312 of thebottom soldering surface 31 and thetop surface 32. - Referring to
FIG. 5 andFIG. 6 , a surface mountedelectronic component 40 according to a third exemplary embodiment is shown. The surface mountedelectronic component 40 is similar to the surface mountedelectronic component 20 in the first exemplary embodiment except that a number offirst cutouts 44 are defined between the firstperipheral wall portion 431 and thefirst soldering area 411 of thebottom soldering surface 41 and a number ofsecond cutouts 45 are defined between the firstperipheral wall portion 431 and thefirst soldering area 411 of thebottom soldering surface 41. When the surface mountedelectronic component 40 is soldered, due to capillary effect and the ‘chimney effect’, the melting solder on afirst soldering area 411 can climb up thefirst cutouts 44 along the inside wall thereof, and the melting solder on asecond soldering area 412 can also climb up thesecond cutouts 45 along the inside wall thereof. Thus area of the surface mountedelectronic component 40 contacting with the solder can be further increased, thereby further balancing the surface tension between thefirst soldering area 411 and thesecond soldering area 412 of the surface mountedelectronic component 40 and reinforcing mounting of the surface mountedelectronic component 40 on the circuit board. - Additionally, the surface mounted electronic component can have a configuration of any other structure. Referring to
FIG. 7 andFIG. 8 , a surfaceelectronic component 50 according to a fourth exemplary embodiment is shown. The surfaceelectronic component 50 has ablock body 500. Theblock body 500 is a cylinder having asoldering bottom surface 51, atop surface 52 opposite to thesoldering bottom surface 51 and aperipheral wall 53. Theperipheral wall 53 adjoins thesoldering bottom surface 21 and thetop surface 22 simultaneously. Theperipheral wall 53 includes a firstperipheral wall portion 531 and a secondperipheral wall portion 532 opposite to the firstperipheral wall portion 531. Therefore, the firstperipheral wall portion 531 and the secondperipheral wall portion 532 adjoin both thesoldering bottom surface 51 and thetop surface 52. - The
soldering bottom surface 51 defines afirst soldering area 511 and asecond soldering area 512. Thefirst soldering area 511 adjoins the firstperipheral wall portion 531 and thesecond soldering area 512 adjoins the secondperipheral wall portion 532. Thefirst soldering area 511 and thesecond soldering area 512 are symmetrical. Afirst cutout 54 is defined between the firstperipheral wall portion 531 and thefirst soldering area 511 of thebottom soldering surface 51 and asecond cutout 55 is defined between the firstperipheral wall portion 531 and thefirst soldering area 511 of thebottom soldering surface 51. Thefirst cutout 54 is symmetrical to thesecond cutout 55. Moreover, thefirst cutout 54 can be defined between thefirst soldering area 511 of thebottom soldering surface 21 and thetop surface 52, and thesecond cutout 55 can be defined between thesecond soldering area 512 of thebottom soldering surface 51 and thetop surface 52. Preferably, thefirst cutout 54 should extend in a direction perpendicular to thefirst soldering area 511, and thesecond cutout 55 should extend in a direction perpendicular to thesecond soldering area 512. Cross-section shape of thefirst cutout 54 and thesecond cutout 55 taken normal to thebottom soldering surface 51 can be selected from the group consisting of arc-shaped, U-shaped, V-shaped, and broken-lines-shaped. In the embodiment, cross-section shape of thefirst cutout 54 taken normal to thebottom soldering surface 51 is arc-shaped and cross-section shape of thesecond cutout 55 taken normal to thebottom soldering surface 51 is also arc-shaped. Additionally, afirst soldering pad 513 and asecond soldering pad 514 can be attached on thefirst soldering area 511 and thesecond soldering area 512 respectively, thereby facilitating soldering of the surface mountedelectronic component 50. - While certain embodiments have been described and exemplified above, various other embodiments will be apparent to those skilled in the art from the foregoing disclosure. The present invention is not limited to the particular embodiments described and exemplified but is capable of considerable variation and modification without departure from the scope of the appended claims.
Claims (12)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/567,593 US7338299B1 (en) | 2003-08-06 | 2006-12-06 | Surface mounted electronic component |
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/635,333 US20040136974A1 (en) | 2002-01-16 | 2003-08-06 | Therapeutic platelets and methods |
US10/722,200 US20040147024A1 (en) | 2000-02-10 | 2003-11-25 | Therapeutic platelets and methods |
PCT/US2004/025653 WO2005020893A2 (en) | 2003-08-06 | 2004-08-06 | Therapeutic platelets and methods |
CN200610062621.8 | 2006-09-15 | ||
CNA2006100626218A CN101145416A (en) | 2006-09-15 | 2006-09-15 | Surface Mount Electronic Components |
US11/567,593 US7338299B1 (en) | 2003-08-06 | 2006-12-06 | Surface mounted electronic component |
Publications (2)
Publication Number | Publication Date |
---|---|
US7338299B1 US7338299B1 (en) | 2008-03-04 |
US20080070429A1 true US20080070429A1 (en) | 2008-03-20 |
Family
ID=39135340
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/567,593 Expired - Fee Related US7338299B1 (en) | 2003-08-06 | 2006-12-06 | Surface mounted electronic component |
Country Status (1)
Country | Link |
---|---|
US (1) | US7338299B1 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090027859A1 (en) * | 2007-07-26 | 2009-01-29 | Giacoma Lawrence M | Surface mounted heat sink and electromagnetic shield |
US8749989B1 (en) | 2009-12-28 | 2014-06-10 | Scientific Components Corporation | Carrier for LTCC components |
JP5679548B2 (en) | 2010-08-02 | 2015-03-04 | 矢崎総業株式会社 | Fixing bracket for components mounted on circuit board |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3148356A (en) * | 1959-09-14 | 1964-09-08 | Jr George A Hedden | Printed circuit connector |
US5569880A (en) * | 1994-12-02 | 1996-10-29 | Avx Corporation | Surface mountable electronic component and method of making same |
US5825633A (en) * | 1996-11-05 | 1998-10-20 | Motorola, Inc. | Multi-board electronic assembly including spacer for multiple electrical interconnections |
US6031728A (en) * | 1997-12-23 | 2000-02-29 | Aerospatiale Societe Nationale Industrielle | Device and method for interconnection between two electronic devices |
US6534726B1 (en) * | 1999-10-25 | 2003-03-18 | Murata Manufacturing Co., Ltd. | Module substrate and method of producing the same |
US6862190B2 (en) * | 2001-01-17 | 2005-03-01 | Honeywell International, Inc. | Adapter for plastic-leaded chip carrier (PLCC) and other surface mount technology (SMT) chip carriers |
US7189083B2 (en) * | 2002-04-01 | 2007-03-13 | Interplex Nas, Inc, | Method of retaining a solder mass on an article |
-
2006
- 2006-12-06 US US11/567,593 patent/US7338299B1/en not_active Expired - Fee Related
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3148356A (en) * | 1959-09-14 | 1964-09-08 | Jr George A Hedden | Printed circuit connector |
US5569880A (en) * | 1994-12-02 | 1996-10-29 | Avx Corporation | Surface mountable electronic component and method of making same |
US5825633A (en) * | 1996-11-05 | 1998-10-20 | Motorola, Inc. | Multi-board electronic assembly including spacer for multiple electrical interconnections |
US6031728A (en) * | 1997-12-23 | 2000-02-29 | Aerospatiale Societe Nationale Industrielle | Device and method for interconnection between two electronic devices |
US6534726B1 (en) * | 1999-10-25 | 2003-03-18 | Murata Manufacturing Co., Ltd. | Module substrate and method of producing the same |
US6862190B2 (en) * | 2001-01-17 | 2005-03-01 | Honeywell International, Inc. | Adapter for plastic-leaded chip carrier (PLCC) and other surface mount technology (SMT) chip carriers |
US7189083B2 (en) * | 2002-04-01 | 2007-03-13 | Interplex Nas, Inc, | Method of retaining a solder mass on an article |
Also Published As
Publication number | Publication date |
---|---|
US7338299B1 (en) | 2008-03-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6541857B2 (en) | Method of forming BGA interconnections having mixed solder profiles | |
EP0767495B1 (en) | Surface-mounting type semiconductor device | |
US6410861B1 (en) | Low profile interconnect structure | |
US8125795B2 (en) | Circuit module and circuit board assembly having surface-mount connector | |
CN201213333Y (en) | Combined apparatus for heat radiating device and circuit board, and communication apparatus | |
US7338299B1 (en) | Surface mounted electronic component | |
US7303443B1 (en) | Socket and method for compensating for differing coefficients of thermal expansion | |
JP5078683B2 (en) | Printed circuit board and surface mount device mounting structure | |
JP2859143B2 (en) | Module parts | |
US20080266823A1 (en) | Circuit board assembly | |
JPH0569887U (en) | Connector, connector-integrated circuit device, and housing with connector-integrated circuit | |
JPH08191128A (en) | Electronic equipment | |
US6423906B2 (en) | Surface mount package for long lead devices | |
JP2007027576A (en) | Semiconductor device | |
JPH06268086A (en) | Semiconductor integrated circuit device and printed circuit board on which the same is mounted | |
JPH1187907A (en) | Soldering mounting method for mounting component | |
JPH08321580A (en) | Structure and manufacture fo hybrid integrated circuit device | |
JP3145984B2 (en) | Electronic components | |
JP2008166525A (en) | Electronic circuit module | |
JP2558239Y2 (en) | Circuit parts with heat sink | |
JPH0125491Y2 (en) | ||
JPH118459A (en) | Structure for mounting surface mount components on printed wiring boards | |
JPH11307564A (en) | Semiconductor device | |
JPH02112267A (en) | semiconductor equipment | |
JP2004134303A (en) | Press fit joining method and its wiring board |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: FOXCONN ADVANCED TECHNOLOGY INC., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LEE, WEN-CHIN;LIN, CHENG-HSIEN;REEL/FRAME:018592/0296 Effective date: 20061205 |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
AS | Assignment |
Owner name: ZHEN DING TECHNOLOGY CO., LTD., TAIWAN Free format text: CHANGE OF NAME;ASSIGNOR:FOXCONN ADVANCED TECHNOLOGY INC.;REEL/FRAME:026893/0929 Effective date: 20110613 |
|
REMI | Maintenance fee reminder mailed | ||
LAPS | Lapse for failure to pay maintenance fees | ||
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20160304 |