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US20080020576A1 - Method of forming polysilicon pattern - Google Patents

Method of forming polysilicon pattern Download PDF

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Publication number
US20080020576A1
US20080020576A1 US11/782,196 US78219607A US2008020576A1 US 20080020576 A1 US20080020576 A1 US 20080020576A1 US 78219607 A US78219607 A US 78219607A US 2008020576 A1 US2008020576 A1 US 2008020576A1
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United States
Prior art keywords
pattern
polysilicon
layer
oxide
oxide layer
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Abandoned
Application number
US11/782,196
Inventor
Duck-Hwan Kim
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DB HiTek Co Ltd
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Dongbu HitekCo Ltd
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Assigned to DONGBU HITEK CO., LTD. reassignment DONGBU HITEK CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KIM, DUCK-HWAN
Publication of US20080020576A1 publication Critical patent/US20080020576A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3088—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

Definitions

  • Polysilicon may be used in fabricating a semiconductor device.
  • Polysilicon may be a material for a gate electrode and may be also used in an active area of a thin film transistor. Photolithography may be used to form various patterns of the polysilicon.
  • the photolithography process may include a coating step to coat photoresist on polysilicon, an exposure step to apply light to predetermined portions of the coated photoresist, and a development step to remove exposed or unexposed portions of the photoresist.
  • the polysilicon may be etched using the photoresist pattern, to thereby form a desired pattern.
  • a line width of the polysilicon pattern may be determined based on a mask pattern used to form the photoresist pattern and a wavelength used in the exposure step.
  • Embodiments relate to semiconductor technology, and to a method of forming a polysilicon pattern that may realize a minute pattern.
  • Embodiments relate to a method of forming a polysilicon pattern, which may reduce a fabrication cost and decrease a line width of the polysilicon pattern.
  • a method of forming a polysilicon pattern may include forming a first polysilicon pattern by selectively etching a polysilicon layer using a photoresist pattern at a fixed interval, forming an oxide layer having a concavo-convex pattern in the first polysilicon pattern, so as to form a second polysilicon pattern covered with the oxide layer, grinding the oxide layer in such an extent that exposes the upper surface of the second polysilicon pattern, etching the second polysilicon pattern exposed in state of using the oxide layer as a mask, forming an oxide-layer pattern used for a mask of a final polysilicon pattern being completed, by etching the oxide layer, and forming the final polysilicon pattern by selectively etching the polysilicon layer in state the oxide-layer pattern is used as a mask.
  • FIGS. 1A to 1G are cross section drawings illustrating a method of forming a polysilicon pattern according to embodiments.
  • a photoresist material may be coated on polysilicon film 2 , and may be patterned, whereby photoresist patterns 11 may be formed at fixed intervals on polysilicon film 2 .
  • polysilicon film 2 may be deposited by chemical vapor deposition (CVD). In embodiments, polysilicon film 2 may be deposited by other methods generally known.
  • CVD chemical vapor deposition
  • Polysilicon film 2 may be selectively etched to a predetermined depth using photoresist patterns 11 as a mask. This may form first polysilicon pattern 2 a shown in FIG. 1B .
  • first polysilicon pattern 2 a When forming first polysilicon pattern 2 a , a lower portion of polysilicon film 2 , which may not have been etched, may be referred to as polysilicon layer 2 b.
  • oxide layer 4 may be formed on polysilicon film 2 including first polysilicon pattern 2 a .
  • oxide layer 4 may be formed by a thermal oxidation process. Accordingly, oxide layer 4 having a concavo-convex pattern may be formed on a surface of first polysilicon pattern 2 a.
  • oxide layer 4 may be formed on a surface of first polysilicon pattern 2 a .
  • the polysilicon pattern covered with oxide layer 4 may be referred to as second polysilicon pattern 2 c.
  • Oxide layer 4 may function as a mask for the final polysilicon pattern to be formed. In embodiments, a position and width of oxide layer 4 may be determined based on the polysilicon pattern to be formed virtually.
  • oxide layer 4 may be grinded to such a depth that may expose second polysilicon pattern 2 c covered with oxide layer 4 . This may form a plurality of concave patterns of oxide layer 4 .
  • a substrate may have a cross section where oxide layer 4 having the concave pattern may be formed between every portion of second polysilicon pattern 2 c.
  • the exposed second polysilicon pattern 2 c may be removed.
  • second polysilicon pattern 2 c may be removed in an etching method using Fluoronate Ethylen Prophylen Solution (FEP Solution).
  • FEP Solution Fluoronate Ethylen Prophylen Solution
  • second polysilicon pattern 2 c is removed to a predetermined depth corresponding to a bottom of the concave pattern of oxide layer 4 , as shown in FIG. 1E , only the concave patterns of oxide layer 4 may remain on polysilicon layer 2 b . A top portion of polysilicon layer 2 b may be exposed between concave patterns of oxide layer 4 .
  • oxide layer 4 may be etched to a predetermined depth. In embodiments oxide layer 4 may be so as to expose portions of polysilicon layer 2 b . In embodiments, oxide layer may be etched by removing an inner bottom portion of the concave pattern, as shown in FIG. 1F . In embodiments, the upper portion of oxide layer 4 may be also etched to such an extent that etches the inner bottom portion of the concave pattern of oxide layer 4 , whereby the total height of oxide layer 4 may be decreased.
  • oxide-layer mask 4 a may be formed.
  • Oxide-layer mask 4 a that may be formed by removing oxide layer 4 at a predetermined depth, may be used as a mask for the final polysilicon pattern to be formed.
  • oxide-layer mask 4 a may function as a mask for the final polysilicon pattern to be formed.
  • polysilicon layer 2 b may be selectively etched based on oxide-layer mask 4 a , and may thus form final polysilicon pattern 10 .
  • an anisotropic etching using oxide-layer mask 4 a may be used so as to obtain the final polysilicon pattern.
  • oxide-layer mask 4 a may be formed not by the general photolithography process, but instead by a thermal oxidation process using the general polysilicon pattern.
  • oxide layer 4 a may be thinner than the width of mask to pattern the related art polysilicon, it may be possible to form the polysilicon pattern having the minute pattern.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Embodiments relate to a method of forming a polysilicon pattern, which may be able to form a minute pattern. In embodiments, the method may in clued forming a first polysilicon pattern by selectively etching a polysilicon layer using a photoresist pattern at a fixed interval, forming an oxide layer having a concavo-convex pattern in the first polysilicon pattern, so as to form a second polysilicon pattern covered with the oxide layer, grinding the oxide layer in such an extent that exposes the upper surface of the second polysilicon pattern, etching the second polysilicon pattern exposed in state of using the oxide layer as a mask, forming an oxide-layer pattern used for a mask of a final polysilicon pattern being completed, by etching the oxide layer to a predetermined depth, and forming the final polysilicon pattern by selectively etching the polysilicon layer in state the oxide-layer pattern is used as a mask.

Description

  • The present application claims priority under 35 U.S.C. 119 and 35 U.S.C. 365 to Korean Patent Application No. 10-2006-0069172 (filed on Jul. 24, 2006), which is hereby incorporated by reference in its entirety.
    • BACKGROUND
  • Polysilicon may be used in fabricating a semiconductor device. Polysilicon may be a material for a gate electrode and may be also used in an active area of a thin film transistor. Photolithography may be used to form various patterns of the polysilicon.
  • The photolithography process may include a coating step to coat photoresist on polysilicon, an exposure step to apply light to predetermined portions of the coated photoresist, and a development step to remove exposed or unexposed portions of the photoresist. After forming a photoresist pattern through the aforementioned steps, the polysilicon may be etched using the photoresist pattern, to thereby form a desired pattern.
  • When forming a polysilicon pattern by photolithography, a line width of the polysilicon pattern may be determined based on a mask pattern used to form the photoresist pattern and a wavelength used in the exposure step.
  • To decrease the line width of a polysilicon pattern when forming the polysilicon pattern, it may be necessary to control a size of a mask to form the photoresist pattern and to minutely control a resolution of an optical apparatus used in the exposure step.
  • However, there may be a limitation to the extent to which the mask size can be controlled and the resolution of optical apparatus can be improved. To improve the resolution of an optical apparatus, it may require a high-priced optical apparatus, thereby increasing a fabrication cost.
    • SUMMARY
  • Embodiments relate to semiconductor technology, and to a method of forming a polysilicon pattern that may realize a minute pattern.
  • Embodiments relate to a method of forming a polysilicon pattern, which may reduce a fabrication cost and decrease a line width of the polysilicon pattern.
  • According to embodiments, a method of forming a polysilicon pattern may include forming a first polysilicon pattern by selectively etching a polysilicon layer using a photoresist pattern at a fixed interval, forming an oxide layer having a concavo-convex pattern in the first polysilicon pattern, so as to form a second polysilicon pattern covered with the oxide layer, grinding the oxide layer in such an extent that exposes the upper surface of the second polysilicon pattern, etching the second polysilicon pattern exposed in state of using the oxide layer as a mask, forming an oxide-layer pattern used for a mask of a final polysilicon pattern being completed, by etching the oxide layer, and forming the final polysilicon pattern by selectively etching the polysilicon layer in state the oxide-layer pattern is used as a mask.
    • DRAWINGS
  • FIGS. 1A to 1G are cross section drawings illustrating a method of forming a polysilicon pattern according to embodiments.
    •  DETAILED DESCRIPTION
  • A process of forming a polysilicon pattern according to embodiments will be described.
  • Referring to FIG. 1A, a photoresist material may be coated on polysilicon film 2, and may be patterned, whereby photoresist patterns 11 may be formed at fixed intervals on polysilicon film 2.
  • In embodiments, polysilicon film 2 may be deposited by chemical vapor deposition (CVD). In embodiments, polysilicon film 2 may be deposited by other methods generally known.
  • Polysilicon film 2 may be selectively etched to a predetermined depth using photoresist patterns 11 as a mask. This may form first polysilicon pattern 2 a shown in FIG. 1B.
  • When forming first polysilicon pattern 2 a, a lower portion of polysilicon film 2, which may not have been etched, may be referred to as polysilicon layer 2 b.
  • Referring to FIG. 1C, oxide layer 4 may be formed on polysilicon film 2 including first polysilicon pattern 2 a. In embodiments, oxide layer 4 may be formed by a thermal oxidation process. Accordingly, oxide layer 4 having a concavo-convex pattern may be formed on a surface of first polysilicon pattern 2 a.
  • Through the thermal oxidation process, oxide layer 4 may be formed on a surface of first polysilicon pattern 2 a. The polysilicon pattern covered with oxide layer 4 may be referred to as second polysilicon pattern 2 c.
  • Oxide layer 4 may function as a mask for the final polysilicon pattern to be formed. In embodiments, a position and width of oxide layer 4 may be determined based on the polysilicon pattern to be formed virtually.
  • Referring to FIG. 1D, after forming oxide layer 4, a planarization process may be performed. In the planarization process, oxide layer 4 may be grinded to such a depth that may expose second polysilicon pattern 2 c covered with oxide layer 4. This may form a plurality of concave patterns of oxide layer 4.
  • Through the planarization process for oxide layer 4, a substrate may have a cross section where oxide layer 4 having the concave pattern may be formed between every portion of second polysilicon pattern 2 c.
  • In embodiments, the exposed second polysilicon pattern 2 c may be removed. In embodiments second polysilicon pattern 2 c may be removed in an etching method using Fluoronate Ethylen Prophylen Solution (FEP Solution).
  • In embodiments, as second polysilicon pattern 2 c is removed to a predetermined depth corresponding to a bottom of the concave pattern of oxide layer 4, as shown in FIG. 1E, only the concave patterns of oxide layer 4 may remain on polysilicon layer 2 b. A top portion of polysilicon layer 2 b may be exposed between concave patterns of oxide layer 4.
  • In embodiments, oxide layer 4 may be etched to a predetermined depth. In embodiments oxide layer 4 may be so as to expose portions of polysilicon layer 2 b. In embodiments, oxide layer may be etched by removing an inner bottom portion of the concave pattern, as shown in FIG. 1F. In embodiments, the upper portion of oxide layer 4 may be also etched to such an extent that etches the inner bottom portion of the concave pattern of oxide layer 4, whereby the total height of oxide layer 4 may be decreased.
  • Referring to FIG. 1F, by etching oxide layer 4, oxide-layer mask 4 a may be formed. Oxide-layer mask 4 a, that may be formed by removing oxide layer 4 at a predetermined depth, may be used as a mask for the final polysilicon pattern to be formed. In embodiments, oxide-layer mask 4 a may function as a mask for the final polysilicon pattern to be formed.
  • Referring to FIG. 1G, polysilicon layer 2 b may be selectively etched based on oxide-layer mask 4 a, and may thus form final polysilicon pattern 10. In embodiments, an anisotropic etching using oxide-layer mask 4 a may be used so as to obtain the final polysilicon pattern.
  • In embodiments, oxide-layer mask 4 a may be formed not by the general photolithography process, but instead by a thermal oxidation process using the general polysilicon pattern.
  • Thus, a high-priced optical apparatus which performs the photolithography process to directly form the mask having the minute pattern may not be necessary.
  • Also, since oxide layer 4 a may be thinner than the width of mask to pattern the related art polysilicon, it may be possible to form the polysilicon pattern having the minute pattern.
  • It may thus be possible to form minute polysilicon patterns without requiring the use of high-priced optical apparatus for the photolithography process.
  • It will be apparent to those skilled in the art that various modifications and variations can be made to embodiments. Thus, it is intended that embodiments cover modifications and variations thereof within the scope of the appended claims. It is also understood that when a layer is referred to as being “on” or “over” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present.

Claims (16)

1. A method, comprising:
forming a first polysilicon pattern by selectively etching a polysilicon layer using a photoresist pattern at a fixed interval;
forming an oxide layer over the first polysilicon pattern, to form a second polysilicon pattern covered with the oxide layer;
grinding the oxide layer to expose an upper surface of the second polysilicon pattern;
etching the exposed second polysilicon pattern using the oxide layer as a mask;
forming an oxide-layer pattern by etching the oxide layer to expose portions of the polysilicon layer; and
forming a final polysilicon pattern by selectively etching the polysilicon layer using the oxide-layer pattern as a mask.
2. The method of claim 1, wherein the oxide layer is formed by a thermal oxidation process.
3. The method of claim 1, wherein grinding the oxide layer comprises a planarization process.
4. The method of claim 1, wherein the exposed second polysilicon pattern is etched using Fluoronate Ethylen Prophylen Solution (FEP Solution).
5. The method of claim 1, wherein the polysilicon layer is selectively etched to form the final polysilicon pattern in an anisotropic etching method using the oxide-layer pattern as a mask.
6. The method of claim 1, wherein the polysilicon layer is deposited by chemical vapor deposition (CVD).
7. The method of claim 1, wherein the oxide layer is formed to have a concavo-convex pattern over the first polysilicon pattern.
8. The method of claim 1, wherein etching the oxide-layer pattern to form the mask to etch the final polysilicon pattern comprises exposing portions of a top surface of the polysilicon layer.
9. A device, comprising:
a polysilicon layer having a final polysilicon pattern formed thereon, wherein the final polysilicon pattern is formed by:
selectively etching a polysilicon layer using a photoresist pattern at a fixed interval to form a first polysilicon pattern;
forming an oxide layer over the first polysilicon pattern;
grinding the oxide layer to expose an upper surface of the first polysilicon pattern;
etching the exposed polysilicon pattern using the oxide layer as a mask;
forming an oxide-layer pattern by etching the oxide layer to expose portions of the polysilicon layer; and
forming the final polysilicon pattern by selectively etching the polysilicon layer using the oxide-layer pattern as a mask.
10. The device of claim 9, wherein the oxide layer is formed by a thermal oxidation process.
11. The device of claim 9, wherein grinding the oxide layer comprises a planarization process.
12. The device of claim 9, wherein the exposed polysilicon pattern is etched using Fluoronate Ethylen Prophylen Solution (FEP Solution).
13. The device of claim 9, wherein the polysilicon layer is selectively etched in an anisotropic etching method which using the oxide-layer pattern as a mask to form the final polysilicon pattern.
14. The device of claim 9, wherein the polysilicon layer is deposited by chemical vapor deposition (CVD).
15. The device of claim 9, wherein the oxide layer is formed to have a concavo-convex pattern over the first polysilicon pattern.
16. The device of claim 9, wherein etching the oxide-layer pattern to form the mask for etching the final polysilicon pattern comprises exposing portions of a top surface of the polysilicon layer.
US11/782,196 2006-07-24 2007-07-24 Method of forming polysilicon pattern Abandoned US20080020576A1 (en)

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KR1020060069172A KR100741926B1 (en) 2006-07-24 2006-07-24 How to Form Polysilicon Pattern

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103794476A (en) * 2012-10-30 2014-05-14 中芯国际集成电路制造(上海)有限公司 Method for forming self-aligned triple pattern
CN103928313A (en) * 2014-04-22 2014-07-16 上海华力微电子有限公司 Manufacturing method for small-sized graph

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KR100823847B1 (en) 2006-12-20 2008-04-21 동부일렉트로닉스 주식회사 Method for pattern formation of semiconductor device
KR102056789B1 (en) 2017-09-26 2019-12-18 국민대학교산학협력단 Method for manufacturing silicon pattern using silica particles and device manufactured by the same
KR102056791B1 (en) 2017-09-26 2019-12-18 국민대학교산학협력단 Method for manufacturing silicon pattern using silica substrate and device manufactured by the same

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US6710395B2 (en) * 2001-12-19 2004-03-23 Renesas Technology Corp. Non-volatile semiconductor memory device with improved performance
US6794313B1 (en) * 2002-09-20 2004-09-21 Taiwan Semiconductor Manufacturing Company, Ltd. Oxidation process to improve polysilicon sidewall roughness
US6972240B2 (en) * 2002-11-19 2005-12-06 Stmicroelectronics S.A. Forming of close thin trenches

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KR20010003465A (en) * 1999-06-23 2001-01-15 김영환 method of forming fine pattern of semiconductor device

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Publication number Priority date Publication date Assignee Title
US6710395B2 (en) * 2001-12-19 2004-03-23 Renesas Technology Corp. Non-volatile semiconductor memory device with improved performance
US6794313B1 (en) * 2002-09-20 2004-09-21 Taiwan Semiconductor Manufacturing Company, Ltd. Oxidation process to improve polysilicon sidewall roughness
US6972240B2 (en) * 2002-11-19 2005-12-06 Stmicroelectronics S.A. Forming of close thin trenches

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103794476A (en) * 2012-10-30 2014-05-14 中芯国际集成电路制造(上海)有限公司 Method for forming self-aligned triple pattern
CN103928313A (en) * 2014-04-22 2014-07-16 上海华力微电子有限公司 Manufacturing method for small-sized graph

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