+

US20080017966A1 - Pillar Bump Package Technology - Google Patents

Pillar Bump Package Technology Download PDF

Info

Publication number
US20080017966A1
US20080017966A1 US11/696,172 US69617207A US2008017966A1 US 20080017966 A1 US20080017966 A1 US 20080017966A1 US 69617207 A US69617207 A US 69617207A US 2008017966 A1 US2008017966 A1 US 2008017966A1
Authority
US
United States
Prior art keywords
die
semiconductor die
leadframe
bump
pillar bump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/696,172
Inventor
Richard Williams
Allen Lam
Keng Lin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Analogic Technologies Inc
Original Assignee
Advanced Analogic Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Analogic Technologies Inc filed Critical Advanced Analogic Technologies Inc
Priority to US11/696,172 priority Critical patent/US20080017966A1/en
Publication of US20080017966A1 publication Critical patent/US20080017966A1/en
Assigned to ADVANCED ANALOGIC TECHNOLOGIES reassignment ADVANCED ANALOGIC TECHNOLOGIES ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: WILLIAMS, RICHARD K.
Assigned to ADVANCED ANALOGIC TECHNOLOGIES reassignment ADVANCED ANALOGIC TECHNOLOGIES ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LAM, ALLEN
Assigned to ADVANCED ANALOGIC TECHNOLOGIES reassignment ADVANCED ANALOGIC TECHNOLOGIES ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LIN, KENG HUNG
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12032—Schottky diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13063—Metal-Semiconductor Field-Effect Transistor [MESFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • U.S. patent application Ser. No. 11/381,292 discloses a package technology for semiconductor products that reduces electrical parasitics.
  • the package technology provides an interconnection method referred to as “bump-on-leadframe” or BOL.
  • a typical implementation of a semiconductor product that uses the BOL method includes a leadframe and a die both included in a plastic package.
  • the BOL method uses “bumps” made out of silver or other conducting material to interconnect the leadframe and die.
  • the leadframe consists of a series of leads that project from one or more sides of the package. Inside the package, each lead extends to overlap some portion of the die. A bump or ball, made of a conductive material such as silver, is positioned between each lead and the die in the region of overlap.
  • the bumps perform several different functions, including: 1) they form the electrical connection between the leads and the die, 2) they support the die during packaging, and 3) they conduct heat away from the die.
  • the die is positioned below the leads. In other words, this means that the leads extend over or above the die to create the required regions of overlap. Alternately, the die may be position above the leads with the leads extending under the die. This flexibility also means that two separate die may be included: one above and one below the leadframe.
  • one or more leads may be electrically isolated from the die.
  • BOL is typically accomplished by omitting the bump between those leads and the die.
  • the die may be fabricated to be non-conducting at the relevant locations.
  • the BOL method may be used in combination with traditional interconnection methods such as wire bonding. In some cases, this means that a single die may be attached to the leadframe using a combination of wire bonds and bumps. In other cases, where a single package includes multiple dice, some die may be connected using bumps while others are connected using traditional techniques such as wire bonds.
  • the current invention provides an interconnection method referred to as “pillar bump-on-leadframe” or PBOL.
  • a typical implementation of a semiconductor product that uses the PBOL method includes a leadframe and a die both included in a plastic package.
  • the PBOL method uses “pillar bumps” to interconnect the leadframe and die.
  • Each pillar bump has a cylindrical (or substantially cylindrical) base section. On one end of the base section, a solder bump or ball is attached.
  • the leadframe consists of a series of leads that project from one or more sides of the package. Inside the package, each lead extends to overlap some portion of the die. A pillar bump is positioned between each lead and the die in the region of overlap. The base section of each pillar bump is connected to the die and the pillar bump portion is in contact with one of the leads.
  • the pillar bumps perform several different functions, including: 1) they form the electrical connection between the leads and the die, 2) they support the die during packaging, and 3) they conduct heat away from the die.
  • the die is positioned below the leads. In other words, this means that the leads extend over or above the die to create the required regions of overlap. Alternately, the die may be position above the leads with the leads extending under the die. This flexibility also means that two separate die may be included: one above and one below the leadframe.
  • one or more leads may be electrically isolated from the die.
  • PBOL PBOL
  • the die may be fabricated to be non-conducting at the relevant locations.
  • the PBOL method may be used in combination with traditional interconnection methods such as wire bonding. In some cases, this means that a single die may be attached to the leadframe using a combination of wire bonds and pillar bumps. In other cases, where a single package includes multiple dice, some die may be connected using pillar bumps while others are connected using traditional techniques such as wire bonds.
  • the PBOL technique may be used to produce a range of innovative single die and multi-die semiconductor products.
  • One example is a two die implementation of a synchronous Buck converter.
  • a silicon controller IC is included as a first die and a silicon MOSFET push-pull power stage is included as a second die.
  • the power stage includes a high-side power MOSFET, which may be a P-channel or N-channel device, and a low-side N-channel MOSFET.
  • the controller IC includes appropriate buffers to drive the high and low-side switches.
  • the buffers are driven, in turn by a PFM/PFM control circuit and a break-before-make (BBM) circuit.
  • BBM break-before-make
  • the Buck converter just described replaces the silicon MOSFET die with a MESFET based power stage.
  • the MESFET power stage includes a high-side switch and a low-side switch both implemented as enhancement mode N-channel MESFET devices.
  • the high-side switch is necessarily an N-channel device (P-channel MESFET devices are difficult to manufacture and are not commercially available)
  • its gate buffer must “float” with respect to the output voltage Vx. For this reason, an additional connection between the two die is required so that the voltage Vx may be utilized as the ground voltage for the gate buffer of the high-side switch.
  • the disadvantage of an extra connection may be outweighed by the higher frequency switching possible using MESFETs when compared to traditional silicon devices.
  • a second variation on the silicon Buck converter repartitions the two dice so that the PFM/PFM control is included in a first die and all other functions (including the BBM circuit, gate drive buffers, high and low-side switches) are included in a second die.
  • Integrating the BBM circuit and gate drivers monolithically facilitates circuit methods to cancel the adverse impact of threshold variation in controlling the timing of the break-before-make interval. In other words, a shorter BBM time can be employed without risk of shoot-through.
  • Only three interconnections are required to interconnect the two dice, namely V batt , ground and the input to the BBM circuit. In this partitioning, no power parasitics are present.
  • the monolithic construction of the switches, buffers and PFM/PWM circuit makes the use of non-silicon implementations (such as MESFET) problematic.
  • a boost converter that includes a control die and a separate die for a discrete Schottky diode rectifier.
  • the control die includes a PWM/PFM control circuit, gate buffers as well as high and low-side switches.
  • the two dice require four interconnections for V batt , ground, feedback V FB , and output V x .
  • the buck and boost converters just described partition their functions between two dice.
  • the two dice share a number of interconnections, some of which are also connected to external components.
  • both dice are connected to the battery voltage V batt and ground.
  • both dice share a connection for the output voltage Vx.
  • these converters are advantageously implemented in a configuration that places one die above and one die below the leadframe.
  • the two dice are configures so that common interconnections (e.g., V BATT , V x . and ground) may be bump connected to the same lead.
  • Implementations that combine PBOL connected dice with wire bond connected dice can also be used to produce a range of novel semiconductor products.
  • a vertical power MOSFET device and a parallel Schottky diode are combined in a single package.
  • the MOSFET is attached using wire bonding techniques and the Schottky is bumped attached to the same leads.
  • a complementary half-bridge for use in synchronous Buck converters may be produced.
  • the two MOSFETS are connected in series using wire bonds to the leadframe.
  • the Schottky is pillar bump connected to the leadframe in parallel with the N-channel device.
  • the PBOL method may also be used to produce a novel protection circuit for one-cell lithium ion batteries implemented as two separate dice.
  • Each dice includes an overcharge protection (OCP) trench powered MOSFET and an over discharge protection (ODCP) trench powered MOSFET.
  • OCP overcharge protection
  • ODCP over discharge protection
  • the two MOSFETS in each dice are connected in series—drain to drain.
  • the two dice are positioned in the same package with one above and one below the leadframe.
  • the PBOL method is used to connect to the two dice in parallel with the two OCP MOSFETS (one in each die) connected source to source and gate to gate and the two two ODCP MOSFETS (one in each die) connected source to source and gate to gate.
  • the use of two die and therefore, two OCP MOSFETS and two ODCP MOSFETS) means that the overall resistance of the safety switch is reduced in comparison with traditional single die implementations.
  • FIG. 1A is a cross-section of a PBOL (Pillar Bump-On-Leadframe) semiconductor product.
  • PBOL Planar Bump-On-Leadframe
  • FIG. 1B is a detailed view of a pillar bump connecting a leadframe and semiconductor.
  • FIG. 2 is another detailed view of a pillar bump connecting a leadframe and semiconductor.
  • FIG. 3 is a cross-section of a stacked PBOL semiconductor product.
  • FIG. 4 is a cross-section of a combination PBOL and wirebond semiconductor product.
  • FIG. 5 is a cross-section of a gullwing PBOL (Pillar Bump-On-Leadframe) semiconductor product.
  • FIG. 6 is a cross-section of a flatpack PBOL (Pillar Bump-On-Leadframe) semiconductor product.
  • PBOL Planar Bump-On-Leadframe
  • a representative semiconductor product 100 that uses this method includes an injection molded plastic package 102 that surrounds leads 104 A and 104 B, a semiconductor dice 106 and conducting pillar bumps 108 A and 108 B.
  • the pillar bumps serve both as the mechanical support for the die during assembly and as an electrical connection to the die, and therefore should ideally exhibit low thermal and electrical resistance.
  • the conductive pillar bump includes a substantially cylindrical base which may or may not be tapered and is typically made from a conductive material such as copper.
  • the base section is connected to the surface of the semiconductor dice.
  • the second end of the base i.e., the end not connected to the dice) is a soft metal ball or cap typically made of solder.
  • each pillar bump is typically on the order of 140 microns in width (dimension A) and 100 microns in height (dimension B).
  • the base portion is typically 60 microns in height (dimension C) and the bump portion is 35 microns high.
  • Adjacent pillar bumps are spaced 300 microns or more apart (dimension D).
  • each of the preceding dimensions is intended to be representative in nature and other values may be used for differing implementations.
  • the pillar bump interconnection method may be used for a wide range of differing semiconductor products.
  • the pillar bump method is used for an implementation where the leads extend over the semiconductor dice. It is equally practical to produce products in which the dice extends over the leads. Alternately, as shown in FIG. 3 , two dice may be used—one under and one over the leads.
  • FIG. 4 shows another variation that also includes two dice. In this case, however one device is connected using pillar bumps and the other is connected using traditional wire bonds. It may be appreciated that the two dice in FIG. 4 may be repositioned with the wirebonded dice on top and the pillar bump attached dice underneath.
  • FIGS. 5 and 6 show semiconductor products that use the pillar bump method for interconnection.
  • a gullwing package is shown and in FIG. 6 a flat package is shown.
  • single or multiple dice may be used with pillar bump interconnection or any combination of pillar bump and wire bond interconnections.
  • the pillar bump method offers the following advantages:

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

A semiconductor product includes a die and leadframe included in a package made of plastic or other insulating material. The die and leadframe are dimensioned so that they overlap in at least one location. One or more pillar bumps, formed from as a cylindrical conductive base topped with a solder bump are used to interconnect the leadframe and die in the region of overlap. The pillar bumps perform several purposes including: electrical connection between the leadframe and die, support for the die during packaging and conduction of heat away from the die.

Description

    BACKGROUND OF THE INVENTION
  • U.S. patent application Ser. No. 11/381,292 (incorporated in this document by reference) discloses a package technology for semiconductor products that reduces electrical parasitics. The package technology provides an interconnection method referred to as “bump-on-leadframe” or BOL. A typical implementation of a semiconductor product that uses the BOL method includes a leadframe and a die both included in a plastic package. Unlike prior art, where wires are used to interconnect the leadframe and die, the BOL method uses “bumps” made out of silver or other conducting material to interconnect the leadframe and die.
  • In its simplest form, the leadframe consists of a series of leads that project from one or more sides of the package. Inside the package, each lead extends to overlap some portion of the die. A bump or ball, made of a conductive material such as silver, is positioned between each lead and the die in the region of overlap. The bumps perform several different functions, including: 1) they form the electrical connection between the leads and the die, 2) they support the die during packaging, and 3) they conduct heat away from the die.
  • In a typical implementation, the die is positioned below the leads. In other words, this means that the leads extend over or above the die to create the required regions of overlap. Alternately, the die may be position above the leads with the leads extending under the die. This flexibility also means that two separate die may be included: one above and one below the leadframe.
  • In some implementations, it may be desirable or necessary for one or more leads to be electrically isolated from the die. When BOL is used, this is typically accomplished by omitting the bump between those leads and the die. Alternately, the die may be fabricated to be non-conducting at the relevant locations.
  • The BOL method may be used in combination with traditional interconnection methods such as wire bonding. In some cases, this means that a single die may be attached to the leadframe using a combination of wire bonds and bumps. In other cases, where a single package includes multiple dice, some die may be connected using bumps while others are connected using traditional techniques such as wire bonds.
    • SUMMARY OF THE INVENTION
  • To alleviate the deficiencies of conventional bond wire packages, the current invention provides an interconnection method referred to as “pillar bump-on-leadframe” or PBOL. A typical implementation of a semiconductor product that uses the PBOL method includes a leadframe and a die both included in a plastic package. Unlike prior art, where wires are used to interconnect the leadframe and die, the PBOL method uses “pillar bumps” to interconnect the leadframe and die. Each pillar bump has a cylindrical (or substantially cylindrical) base section. On one end of the base section, a solder bump or ball is attached.
  • In its simplest form, the leadframe consists of a series of leads that project from one or more sides of the package. Inside the package, each lead extends to overlap some portion of the die. A pillar bump is positioned between each lead and the die in the region of overlap. The base section of each pillar bump is connected to the die and the pillar bump portion is in contact with one of the leads.
  • The pillar bumps perform several different functions, including: 1) they form the electrical connection between the leads and the die, 2) they support the die during packaging, and 3) they conduct heat away from the die.
  • In a typical implementation, the die is positioned below the leads. In other words, this means that the leads extend over or above the die to create the required regions of overlap. Alternately, the die may be position above the leads with the leads extending under the die. This flexibility also means that two separate die may be included: one above and one below the leadframe.
  • In some implementations, it may be desirable or necessary for one or more leads to be electrically isolated from the die. When PBOL is used, this is typically accomplished by omitting the pillar bump between those leads and the die. Alternately, the die may be fabricated to be non-conducting at the relevant locations.
  • The PBOL method may be used in combination with traditional interconnection methods such as wire bonding. In some cases, this means that a single die may be attached to the leadframe using a combination of wire bonds and pillar bumps. In other cases, where a single package includes multiple dice, some die may be connected using pillar bumps while others are connected using traditional techniques such as wire bonds.
  • The PBOL technique may be used to produce a range of innovative single die and multi-die semiconductor products. One example is a two die implementation of a synchronous Buck converter. For this implementation, a silicon controller IC is included as a first die and a silicon MOSFET push-pull power stage is included as a second die. The power stage includes a high-side power MOSFET, which may be a P-channel or N-channel device, and a low-side N-channel MOSFET. The controller IC includes appropriate buffers to drive the high and low-side switches. The buffers are driven, in turn by a PFM/PFM control circuit and a break-before-make (BBM) circuit.
  • One possible variation of the Buck converter just described replaces the silicon MOSFET die with a MESFET based power stage. The MESFET power stage includes a high-side switch and a low-side switch both implemented as enhancement mode N-channel MESFET devices. Because the high-side switch is necessarily an N-channel device (P-channel MESFET devices are difficult to manufacture and are not commercially available), its gate buffer must “float” with respect to the output voltage Vx. For this reason, an additional connection between the two die is required so that the voltage Vx may be utilized as the ground voltage for the gate buffer of the high-side switch. The disadvantage of an extra connection may be outweighed by the higher frequency switching possible using MESFETs when compared to traditional silicon devices.
  • A second variation on the silicon Buck converter repartitions the two dice so that the PFM/PFM control is included in a first die and all other functions (including the BBM circuit, gate drive buffers, high and low-side switches) are included in a second die. Integrating the BBM circuit and gate drivers monolithically facilitates circuit methods to cancel the adverse impact of threshold variation in controlling the timing of the break-before-make interval. In other words, a shorter BBM time can be employed without risk of shoot-through. Only three interconnections are required to interconnect the two dice, namely Vbatt, ground and the input to the BBM circuit. In this partitioning, no power parasitics are present. The monolithic construction of the switches, buffers and PFM/PWM circuit makes the use of non-silicon implementations (such as MESFET) problematic.
  • Another example of an innovative multi-die semiconductor product that uses the PBOL technique is a boost converter that includes a control die and a separate die for a discrete Schottky diode rectifier. The control die includes a PWM/PFM control circuit, gate buffers as well as high and low-side switches. The two dice require four interconnections for Vbatt, ground, feedback VFB, and output Vx.
  • The buck and boost converters just described partition their functions between two dice. The two dice share a number of interconnections, some of which are also connected to external components. For example, in each of the examples, both dice are connected to the battery voltage Vbatt and ground. In several implementations, both dice share a connection for the output voltage Vx. When the PBOL method is used, these converters are advantageously implemented in a configuration that places one die above and one die below the leadframe. The two dice are configures so that common interconnections (e.g., VBATT, Vx. and ground) may be bump connected to the same lead.
  • Implementations that combine PBOL connected dice with wire bond connected dice can also be used to produce a range of novel semiconductor products. For one such example, a vertical power MOSFET device and a parallel Schottky diode are combined in a single package. The MOSFET is attached using wire bonding techniques and the Schottky is bumped attached to the same leads. Similarly, by combining an N-channel MOSFET, P-channel MOSFET and Schottky diode, in a single package, a complementary half-bridge for use in synchronous Buck converters may be produced. In this particular implementation, the two MOSFETS are connected in series using wire bonds to the leadframe. The Schottky is pillar bump connected to the leadframe in parallel with the N-channel device.
  • The PBOL method may also be used to produce a novel protection circuit for one-cell lithium ion batteries implemented as two separate dice. Each dice includes an overcharge protection (OCP) trench powered MOSFET and an over discharge protection (ODCP) trench powered MOSFET. The two MOSFETS in each dice are connected in series—drain to drain. The two dice are positioned in the same package with one above and one below the leadframe. The PBOL method is used to connect to the two dice in parallel with the two OCP MOSFETS (one in each die) connected source to source and gate to gate and the two two ODCP MOSFETS (one in each die) connected source to source and gate to gate. The use of two die (and therefore, two OCP MOSFETS and two ODCP MOSFETS) means that the overall resistance of the safety switch is reduced in comparison with traditional single die implementations.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1A is a cross-section of a PBOL (Pillar Bump-On-Leadframe) semiconductor product.
  • FIG. 1B is a detailed view of a pillar bump connecting a leadframe and semiconductor.
  • FIG. 2 is another detailed view of a pillar bump connecting a leadframe and semiconductor.
  • FIG. 3 is a cross-section of a stacked PBOL semiconductor product.
  • FIG. 4 is a cross-section of a combination PBOL and wirebond semiconductor product.
  • FIG. 5 is a cross-section of a gullwing PBOL (Pillar Bump-On-Leadframe) semiconductor product.
  • FIG. 6 is a cross-section of a flatpack PBOL (Pillar Bump-On-Leadframe) semiconductor product.
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • This document discloses a method for interconnecting semiconductor products to their leadframes using pillar bumps. As shown in FIG. 1A, a representative semiconductor product 100 that uses this method includes an injection molded plastic package 102 that surrounds leads 104A and 104B, a semiconductor dice 106 and conducting pillar bumps 108A and 108B. The pillar bumps serve both as the mechanical support for the die during assembly and as an electrical connection to the die, and therefore should ideally exhibit low thermal and electrical resistance. In a preferred embodiment shown more clearly in FIG. 1B, the conductive pillar bump includes a substantially cylindrical base which may or may not be tapered and is typically made from a conductive material such as copper. The base section is connected to the surface of the semiconductor dice. The second end of the base (i.e., the end not connected to the dice) is a soft metal ball or cap typically made of solder.
  • As shown in FIG. 2, each pillar bump is typically on the order of 140 microns in width (dimension A) and 100 microns in height (dimension B). The base portion is typically 60 microns in height (dimension C) and the bump portion is 35 microns high. Adjacent pillar bumps are spaced 300 microns or more apart (dimension D). Of course, each of the preceding dimensions is intended to be representative in nature and other values may be used for differing implementations.
  • The pillar bump interconnection method may be used for a wide range of differing semiconductor products. In FIG. 1, the pillar bump method is used for an implementation where the leads extend over the semiconductor dice. It is equally practical to produce products in which the dice extends over the leads. Alternately, as shown in FIG. 3, two dice may be used—one under and one over the leads.
  • FIG. 4 shows another variation that also includes two dice. In this case, however one device is connected using pillar bumps and the other is connected using traditional wire bonds. It may be appreciated that the two dice in FIG. 4 may be repositioned with the wirebonded dice on top and the pillar bump attached dice underneath.
  • FIGS. 5 and 6 show semiconductor products that use the pillar bump method for interconnection. In FIG. 5, a gullwing package is shown and in FIG. 6 a flat package is shown. In each case, single or multiple dice may be used with pillar bump interconnection or any combination of pillar bump and wire bond interconnections.
  • Compared to the bump on leadframe method, the pillar bump method offers the following advantages:
      • 1) Copper pillar has fine pitch capability of 80 um and below;
      • 2) Bump height control or coplanarity is better (or more accurate).
      • 3) Copper pillar allows easier flow of mold compound (or underfill) between bumps, minimizing molding voids in molded packages.
      • 4) Copper has better thermal resistance than Solder—better heat dissipation.
      • 5) Copper pillar can make pillar bar (i.e. elongated bump) to reduce contact resistance for both thermal and electrical performance.
      • 6) Copper pillar bump can have less current crowding, reduced local Joule heating, longer bump life (better reliability), and increase current density/capability.
      • 7) Copper does not have Tin (Solder) whisker reliability issue.
  • In general, it should be appreciated that the present invention is specifically intended to cover the specific embodiments shown in the accompanying figures. In addition, the present invention specifically includes modification of all of the embodiments shown in U.S. patent application Ser. No. 11/381,292 to replace the disclosed bump on leadframe with the pillar bump on leadframe method of the present invention.

Claims (13)

1. An integrated circuit product that includes:
a first semiconductor die,
a first lead, the first lead connected to the first semiconductor die by a first electrically conductive pillar bump where the pillar bump includes a substantially cylindrical base section connected to the first semiconductor die and a bump portion in contact with the first lead; and
a package containing the first semiconductor die, the first electrically conductive pillar bump and a portion of the first lead.
2. An integrated circuit product as recited in claim 1 that further comprises a second semiconductor die, the second semiconductor die electrically connected to the first lead.
3. An integrated circuit product as recited in claim 2 in which the second semiconductor die is connected to the first lead by a wire.
4. An integrated circuit product as recited in claim 2 in which the second semiconductor die is connected to the first lead by a second electrically conductive pillar bump.
5. An integrated circuit product as recited in claim 2 in which the first and second semiconductor dice are stacked to substantially overlap each other.
6. An integrated circuit product as recited in claim 2 in which the first and second semiconductor dice are positioned adjacent to each other.
7. An integrated circuit product as recited in claim 2 in which the first semiconductor die includes a vertical power MOSFET and the second semiconductor die includes a Schottky diode.
8. An integrated circuit product in claim 2 in which the first semiconductor die includes a first MOSFET and the second semiconductor die includes a second MOSFET.
9. A method for manufacturing an integrated circuit product,
the method comprising:
fabricating a first semiconductor die;
forming a first electrically conductive pillar bump on the first semiconductor die where the a first electrically conductive pillar bump includes a substantially cylindrical base section connected to the first semiconductor die and a bump portion; and
positioning a leadframe in contact with the bump portion of the first electrically conductive pillar bump.
10. A method as recited in claim 9 that further comprises:
fabricating a second semiconductor die;
forming a second electrically conductive pillar bump on the second semiconductor die; and
positioning the leadframe in contact with the bump portion of the second electrically conductive pillar bump.
11. A method as recited in claim 10 in which the first and second semiconductor dice are stacked to substantially overlap each other.
11. A method as recited in claim 10 in which the first semiconductor die includes a vertical power MOSFET and the second semiconductor die includes a Schottky diode.
12. A method as recited in claim 10 in which the first semiconductor die includes a first MOSFET and the second semiconductor die includes a second MOSFET.
US11/696,172 2006-05-02 2007-04-03 Pillar Bump Package Technology Abandoned US20080017966A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/696,172 US20080017966A1 (en) 2006-05-02 2007-04-03 Pillar Bump Package Technology

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US38129206A 2006-05-02 2006-05-02
US11/696,172 US20080017966A1 (en) 2006-05-02 2007-04-03 Pillar Bump Package Technology

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US38129206A Continuation-In-Part 2006-05-02 2006-05-02

Publications (1)

Publication Number Publication Date
US20080017966A1 true US20080017966A1 (en) 2008-01-24

Family

ID=38970658

Family Applications (1)

Application Number Title Priority Date Filing Date
US11/696,172 Abandoned US20080017966A1 (en) 2006-05-02 2007-04-03 Pillar Bump Package Technology

Country Status (1)

Country Link
US (1) US20080017966A1 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080136003A1 (en) * 2006-12-07 2008-06-12 Stats Chippac, Inc. Multi-layer semiconductor package
US20090189678A1 (en) * 2006-08-30 2009-07-30 Neill Thornton High temperature operating package and circuit design
US20110000224A1 (en) * 2008-03-19 2011-01-06 Uttam Ghoshal Metal-core thermoelectric cooling and power generation device
US8669139B1 (en) * 2007-08-29 2014-03-11 Marvell International Ltd. Leadless multi-chip module structure
US9922945B2 (en) 2012-06-15 2018-03-20 Stmicroelectronics S.R.L. Methods, circuits and systems for a package structure having wireless lateral connections
US20220246489A1 (en) * 2020-03-20 2022-08-04 Texas Instruments Incorporated Semiconductor device package with reduced stress

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5917242A (en) * 1996-05-20 1999-06-29 Micron Technology, Inc. Combination of semiconductor interconnect
US20040104456A1 (en) * 2002-11-12 2004-06-03 Duffy Thomas P. Methods and apparatus for reducing parasitic inductance using inter-digitated bond, wires
US20070131938A1 (en) * 2005-11-29 2007-06-14 Advanced Analogic Technologies, Inc. Merged and Isolated Power MESFET Devices

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5917242A (en) * 1996-05-20 1999-06-29 Micron Technology, Inc. Combination of semiconductor interconnect
US20040104456A1 (en) * 2002-11-12 2004-06-03 Duffy Thomas P. Methods and apparatus for reducing parasitic inductance using inter-digitated bond, wires
US20070131938A1 (en) * 2005-11-29 2007-06-14 Advanced Analogic Technologies, Inc. Merged and Isolated Power MESFET Devices

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8030764B2 (en) * 2006-08-30 2011-10-04 Fairchild Semiconductor Corporation High temperature operating package and circuit design
US20090189678A1 (en) * 2006-08-30 2009-07-30 Neill Thornton High temperature operating package and circuit design
US8803239B2 (en) 2006-08-30 2014-08-12 Fairchild Semiconductor Corporation High temperature operating package and circuit design
US20100007002A1 (en) * 2006-12-07 2010-01-14 Pendse Rajendra D Multi-layer semiconductor package
US7994626B2 (en) 2006-12-07 2011-08-09 Stats Chippac, Inc. Multi-layer semiconductor package with vertical connectors and method of manufacture thereof
US20080136003A1 (en) * 2006-12-07 2008-06-12 Stats Chippac, Inc. Multi-layer semiconductor package
US7608921B2 (en) * 2006-12-07 2009-10-27 Stats Chippac, Inc. Multi-layer semiconductor package
US8669139B1 (en) * 2007-08-29 2014-03-11 Marvell International Ltd. Leadless multi-chip module structure
US8912664B1 (en) * 2007-08-29 2014-12-16 Marvell International Ltd. Leadless multi-chip module structure
US20110000224A1 (en) * 2008-03-19 2011-01-06 Uttam Ghoshal Metal-core thermoelectric cooling and power generation device
US9922945B2 (en) 2012-06-15 2018-03-20 Stmicroelectronics S.R.L. Methods, circuits and systems for a package structure having wireless lateral connections
US10497655B2 (en) 2012-06-15 2019-12-03 Stmicroelectronics S.R.L. Methods, circuits and systems for a package structure having wireless lateral connections
US20220246489A1 (en) * 2020-03-20 2022-08-04 Texas Instruments Incorporated Semiconductor device package with reduced stress
US12119280B2 (en) * 2020-03-20 2024-10-15 Texas Instruments Incorporated Semiconductor device package with reduced stress

Similar Documents

Publication Publication Date Title
US10204899B2 (en) Semiconductor device with first and second chips and connections thereof and a manufacturing method of the same
US8344459B2 (en) Semiconductor device
US8345458B2 (en) Semiconductor device
CN100495702C (en) Stacked Dual Metal Oxide Semiconductor Field Effect Transistor Package
USRE41719E1 (en) Power MOSFET with integrated drivers in a common package
US8497574B2 (en) High power semiconductor package with conductive clips and flip chip driver IC
US7227198B2 (en) Half-bridge package
US8742490B2 (en) Vertical power transistor die packages and associated methods of manufacturing
US7095099B2 (en) Low profile package having multiple die
US20080017966A1 (en) Pillar Bump Package Technology
US9754862B2 (en) Compound semiconductor device including a multilevel carrier

Legal Events

Date Code Title Description
AS Assignment

Owner name: ADVANCED ANALOGIC TECHNOLOGIES, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:WILLIAMS, RICHARD K.;REEL/FRAME:020527/0218

Effective date: 20080219

AS Assignment

Owner name: ADVANCED ANALOGIC TECHNOLOGIES, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LAM, ALLEN;REEL/FRAME:020547/0268

Effective date: 20080221

AS Assignment

Owner name: ADVANCED ANALOGIC TECHNOLOGIES, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LIN, KENG HUNG;REEL/FRAME:020568/0034

Effective date: 20080227

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION

点击 这是indexloc提供的php浏览器服务，不要输入任何密码和下载