US20080003747A1

US20080003747A1 - Non-volatile memory device and manufacturing method thereof

Info

Publication number: US20080003747A1
Application number: US11/635,910
Authority: US
Inventors: Eun Seok Choi
Original assignee: Hynix Semiconductor Inc
Current assignee: SK Hynix Inc
Priority date: 2006-06-29
Filing date: 2006-12-08
Publication date: 2008-01-03
Also published as: US7923335B2; KR20080001352A; CN101097965A; US20090081841A1; KR100812933B1

Abstract

A non-volatile memory device having a Polysilicon Oxide Nitride Oxide Semiconductor (SONOS) structure in which a charge trap layer is separated physically in a horizontal direction, and a method of manufacturing the same. The charge trap layer that traps electric charges toward the source and the drain is physically divided. It can fundamentally prevent the charges at both sides from being moved mutually. It is therefore possible to prevent interference between charges at both sides although the cell size is reduced.

Description

BACKGROUND OF THE INVENTION

The invention relates, in general, to non-volatile memory devices and, more particularly, to a non-volatile memory device having a Polysilicon Oxide Nitride Oxide Semiconductor (SONOS) structure in which a charge trap layer is separated physically horizontally and a method of manufacturing the same.
In recent years, Non-volatile Semiconductor Memories (NVSM) are largely classified into floating gate series and Metal Insulator Semiconductor (MIS) series in which two or more kinds of dielectric layers are laminated doubly or triply in terms of the process technology.
The floating gate series implement a memory characteristic by employing the potential well. A representative example of the floating gate series is an EPROM Tunnel Oxide (ETO) structure that has been widely used as flash Electrically Erasable Programmable Read Only Memory (EEPROM). The MIS series performs the memory function employing traps existing at the dielectric layer bulk, the dielectric layer dielectric layer interface, and the dielectric layer-semiconductor interface. A representative example of the MIS series is a Metal/Polysilicon Oxide Nitride Oxide Semiconductor (MONOS/SONOS) that has been widely used as flash EEPROM.
A difference between the SONOS and general flash memory is that in the general flash memory, charges are stored in the floating gate, whereas in the SONOS, charges are stored in the nitride layer in terms of the structure.
Furthermore, in the general flash memory, the floating gate is formed using polysilicon. Thus, if any one defect exists in polysilicon, the retention time of charge is significantly lowered. In contrast, in the SONOS, the nitride layer is used instead of polysilicon as described above. Accordingly, the sensitivity to defect in process is relatively small.
In addition, in the general flash memory, tunnel oxide having a thickness of about 70 Å is formed under the floating gate. There is a limit to the implementation of a low-voltage and high-speed operation. However, in SONOS, direct tunneling oxide is formed under the nitride layer. It is therefore possible to implement a memory device having a lower voltage, lower power and high-speed operation.
A conventional flash memory device having the SONOS structure will be described below with reference to FIG. 1.
Referring to FIG. 1, a tunnel oxide layer 11, a charge trap layer 12, a blocking gate (oxide layer) 13, and an electrode 14 for a gate are sequentially formed on a semiconductor substrate 10. Word line patterns are then formed by an etch process. In the flash memory cell of the SONOS structure, since the same E-field is applied to the whole complex layer of the blocking oxide layer 13 (i.e., an insulating layer), the charge trap layer 12 for storing charges and the tunnel oxide layer 11, different electric field (E-field) cannot be applied to the insulating layers, respectively.
In this case, if a voltage is applied to the electrode 14 for gate in order to erase the charges stored in the charge trap layer 12, the charges stored in the nitride layer 12 are moved toward the semiconductor substrate 10 by means of a Fowler-Nordheim (F-N) tunneling current through the tunnel oxide layer 11 and are then erased.
As the cell size of a memory cell is reduced, it becomes difficult to separate charges trapped at the source region 15 and the drain region 16 in the cell of the SONOS structure. If the density of charges is increased in order to implement a multi-level, the interference phenomenon becomes more profound, which leads to limit the level of integration.

SUMMARY OF THE INVENTION

Accordingly, the invention addresses the above problems, and provides a non-volatile memory device having a SONOS structure, in which a charge trap layer in which charges are trapped toward source and drain is separated physically in order to prevent charges at both sides of the charge trap layer from being moved mutually, and interference between the charges at both sides can be prevented although the cell size is reduced, and a method of manufacturing the same.
According to one aspect, the invention provides a non-volatile memory device, including a gate in which a gate insulating layer, a charge trap layer, a blocking oxide layer and a gate electrode are formed, respectively over a semiconductor substrate. The charge trap layer is physically divided by a buffer layer.
According to another embodiment, the invention provides a method of manufacturing a non-volatile memory device, including the steps of depositing a gate insulating layer, a buffer layer, a blocking oxide layer and a gate electrode over a semiconductor substrate, respectively, etching the gate electrode, the blocking oxide layer, the buffer layer and the gate insulating layer to form a gate, performing an ion implant process to form source and drain regions within the semiconductor substrate, selectively forming a recessed pattern of the buffer layer by selectively etching the buffer layer both sides, and forming a charge trap layer in the recessed pattern of the buffer layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a conventional flash memory device having the SONOS structure; and

FIGS. 2 to 5 are cross-sectional views illustrating a method of manufacturing a semiconductor memory device having a SONOS structure according to an embodiment of the invention.

DETAILED DESCRIPTION OF EMBODIMENTS

Hereinafter, specific embodiments of the invention will be described with reference to the accompanying drawings.
FIGS. 2 to 5 are cross-sectional views illustrating a method of manufacturing a non-volatile memory device having a SONOS structure according to an embodiment of the invention.
Referring to FIG. 2, a gate insulating layer 101, a buffer layer 102, a blocking oxide layer 103 and a gate electrode 104 are sequentially formed on a semiconductor substrate 100. The buffer layer 102 may be formed using a silicon oxide layer or a silicon nitride layer. The blocking oxide layer 103 may be formed using a high dielectric layer, such as Al₂O₃, HfO₂, Ta₂O₅, ZrO₂, La₂O₃or TiO₂, or a combination of them. Furthermore, a silicon oxide layer may be used instead of the blocking oxide layer 103. The gate electrode 104 may be formed using polysilicon doped with an impurity. The gate electrode 104 may be formed using transfer metal nitride such as TiN, TaN, TiCN, TaCN, TiSiN, TaSiN, WN or RuTiN. The buffer layer 102 is preferably formed to a thickness of 20 Å to 1000 Å.
Referring to FIG. 3, the gate electrode 104, the blocking oxide layer 103, the buffer layer 102 and the gate insulating layer 101 are sequentially partially etched by an etch process, forming a gate pattern. An ion implant process is performed to form a source region 105 and a drain region 106 in the exposed semiconductor substrate 100.
Referring to FIG. 4, an etch process is performed to recess the sides of the exposed buffer layer 102, thus forming a space. It is preferred that the recessed depth be 1/20 to ½ or less of the length of a gate pattern.
A charge trap layer 107 is then deposited on the entire surface. The charge trap layer 107 is preferably formed to completely gap fill the empty space formed by etching the buffer layer 102. Furthermore, the charge trap layer 107 may be formed using a silicon nitride layer or metal oxide layer.
The process of forming the source region 105 and the drain region 106 may be carried out posterior to the process of depositing the charge trap layer 107.
Referring to FIG. 5, an etch process is performed in such a manner that the charge trap layer 107 remains only at both sides of the buffer layer 102. That is, it is preferred that the charge trap layer 107 be physically separated by the buffer layer 102. Due to this, the charge trap layer 107 that traps electric charges is divided into two horizontally at both sides of the gate due to a layer having a physically different property, i.e., the buffer layer 102.
The process of forming the source region 105 and the drain region 106 may be performed posterior to the process of etching the charge trap layer 107.
In accordance with the invention, the charge trap layer that traps electric charges toward the source and drain is physically divided. It can fundamentally prevent the charges at both sides from being moved mutually. It is therefore possible to prevent interference between charges at both sides although the cell size is reduced.
Although the foregoing description has been made with reference to various embodiments, changes and modifications may be made by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A non-volatile memory device comprising:

a gate in which a gate insulating layer, a charge trap layer, a blocking oxide layer and a gate electrode are formed, respectively over a semiconductor substrate,

wherein the charge trap layer is physically divided by a buffer layer.

2. The non-volatile memory device of claim 1, wherein the charge trap layer is a silicon nitride layer or a metal oxide layer.

3. The non-volatile memory device of claim 1, wherein the buffer layer is a dielectric layer.

4. The non-volatile memory device of claim 3, wherein the dielectric layer is a silicon oxide layer or a silicon nitride layer.

5. The non-volatile memory device of claim 1, wherein the buffer layer has a width, which is less 1/10 than that of the gate.

6. The non-volatile memory device of claim 1, wherein the buffer layer has a thickness of 20 Å to 1000 Å.

7. A method of manufacturing a non-volatile memory device comprising the steps of:

depositing a gate insulating layer, a buffer layer, a blocking oxide layer and a gate electrode over a semiconductor substrate, respectively;

etching the gate electrode, the blocking oxide layer, the buffer layer and the gate insulating layer to form a gate;

performing an ion implant process to form source and drain regions within the semiconductor substrate;

selectively forming a recessed pattern of the buffer layer by selectively etching the buffer layer both sides; and

forming a charge trap layer in the recessed pattern of the buffer layer.

8. The method of claim 7, comprising forming the buffer layer using a silicon oxide layer or a silicon nitride layer.

9. The method of claim 7, comprising forming the buffer layer to a thickness of 20 Å to 1000 Å.

10. The method of claim 7, comprising forming the blocking oxide layer using a high dielectric layer.

11. The method of claim 10, wherein the high dielectric layer is selected from the group consisting of Al₂O₃, HfO₂, Ta₂O₅, ZrO₂, La₂O₃, TiO₂and combinations therein.

12. The method of claim 7, wherein in the selective etch process, the recessed thickness of each of both sides of the buffer layer to 1/20 to ½ of the gate width.

13. The method of claim 7, comprising forming the gate electrode using transfer metal nitride or polysilicon doped with an impurity.

14. The method of claim 13, wherein the transfer metal nitride is TiN, TaN, TiCN, TaCN, TiSiN, TaSiN, WN or RuTiN.

15. The method of claim 7, wherein the step of forming the charge trap layer comprises the steps of:

depositing a charge trap material over the recessed pattern of the buffer layer, the gate and the semiconductor substrate; and

etching the charge trap material wherein the charge trap material remain only the recessed pattern of the buffer layer.

13. The method of claim 15, comprising performing the ion implant process is after the step of depositing the charge trap material or the step of forming the charge trap layer.