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US20070181995A1 - Circuit board structure embedded with semiconductor chips - Google Patents

Circuit board structure embedded with semiconductor chips Download PDF

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Publication number
US20070181995A1
US20070181995A1 US11/544,199 US54419906A US2007181995A1 US 20070181995 A1 US20070181995 A1 US 20070181995A1 US 54419906 A US54419906 A US 54419906A US 2007181995 A1 US2007181995 A1 US 2007181995A1
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United States
Prior art keywords
circuit
layer
circuit board
dielectric layer
build
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
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US11/544,199
Inventor
Shih Ping Hsu
Chung Cheng Lien
Shang Wei Chen
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Phoenix Precision Technology Corp
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Phoenix Precision Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Phoenix Precision Technology Corp filed Critical Phoenix Precision Technology Corp
Assigned to PHOENIX PRECISION TECHNOLOGY CORPORATION reassignment PHOENIX PRECISION TECHNOLOGY CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHEN, SHANG WEI, HSU, SHIH PING, LIEN, CHUNG CHENG
Publication of US20070181995A1 publication Critical patent/US20070181995A1/en
Priority to US12/427,668 priority Critical patent/US7863729B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H05K2201/09518—Deep blind vias, i.e. blind vias connecting the surface circuit to circuit layers deeper than the first buried circuit layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09809—Coaxial layout
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated

Definitions

  • This invention relates to circuit board structures, and more particularly, to a circuit board structure having hollow conductive vias for electrically connecting semiconductor chips and circuitry embedded in the circuit board structure.
  • a ball grid array (BGA) technique is one of the most advanced semiconductor packaging techniques.
  • the BGA technique includes installing a semiconductor chip on a package substrate, and installing a plurality of array disposed solder balls on a rear surface of the package substrate by using a self-alignment technique. Therefore, a number of I/O connection terminals per unit area on a carrying member carried with the semiconductor chip is increased, and an integration demand for semiconductor chips is requested.
  • the semiconductor chip is electrically connected via these solder balls to external devices.
  • the semiconductor packaging technique of the prior art when manufacturing the semiconductor device, first adheres the semiconductor chip to a front surface of the package substrate, then performs wire bonding or flip chip packaging process on the semiconductor chip, and finally installs on the rear surface of the package substrate the solder balls, which electrically connect the semiconductor chip to the external devices.
  • the semiconductor device manufactured by such a semiconductor package technique has increased number of I/O connection terminals and meets the requirement of high pin count, the electric characteristics of the semiconductor device, when operating at a high frequency, are severely restricted due to too long a conductive connection route.
  • the semiconductor packaging technique of the prior art needs to perform many times of connecting interface processes, so that a manufacturing process for the semiconductor device is complicated.
  • FIG. 1 is a cross sectional view of a package member having a substrate embedded with semiconductor chips according to the prior art.
  • the package member comprises a carrying board 10 . At least a cavity 100 a is formed on a surface 100 of the carrying board 10 .
  • the package member further comprises at least a semiconductor chip 11 installed on the carrying board 10 and received in the cavity 100 a.
  • a plurality of electrode pads 110 are formed on the semiconductor chip 11 .
  • the package member further comprises a circuit build-up structure 12 formed on the carrying board 10 and electrically connected via a plurality of conductive vias 120 to the electrode pads 110 .
  • the semiconductor chip 11 comprises an active surface 11 a and a non-active surface 11 b opposing to the active surface 11 a.
  • the electrode pads 110 are installed on the active surface 11 a.
  • the non-active surface 11 b is formed in the cavity 100 a and adhered to the carrying board 10 by the use of an adhesive 13 .
  • the circuit build-up structure 12 comprises at least a dielectric layer 121 , a circuit layer 122 interlacing with the dielectric layer 121 , and a plurality of conductive vias 120 passing through the dielectric layer 121 and electrically connected to the circuit layer 122 and the electrode pads 110 .
  • a plurality of electric connection terminals 123 are further formed on an outmost surface of the circuit layer 122 of the circuit build-up structure 12 .
  • a solder mask 124 is further formed on the outmost surface of the circuit layer 122 .
  • the solder mask 124 comprises a plurality of openings for exposure of the electric connection terminals 123 .
  • the electric connection terminals 123 are installed for plantation of a plurality of conductive elements such as solder balls 125 . Therefore, the semiconductor chip 11 installed on the carrying board 10 and received in the cavity 100 a can be electrically connected via the electrode pads 110 , the circuit build-up structure 12 and the solder balls 125 to the external device.
  • the circuit layer 122 is electrically connected via the conductive vias 120 directly to the semiconductor chip 11 , and the conductive vias 120 are formed by plated copper in vias formed in an insulating layer, the vias being fully filled by the plated copper.
  • CTE coefficients of thermal expansion
  • composed components such as the insulating layer and a protection layer for protecting the semiconductor chip
  • thermal expansion of the composed components are different from each other. In result, a thermal stress is produced in the package member, the formed circuit structure is likely separated from the electrode pads 110 of the semiconductor chip 11 due to the thermal stress, and the package member is thus malfunctioned.
  • the conductive vias 120 for connection of circuitry are formed to have a stack structure.
  • the composed units surrounding the conductive vias 120 have different CTEs, and thermal stress produced in the package member are therefore mismatched, the circuit structure is easily separated from the electrode pads 120 of the semiconductor chip 11 . In result, the demand of fine pitch can not be attained and the package member has poor reliability.
  • the circuit board structure includes a supporting board having at least a cavity; at least a semiconductor chip embedded in the cavity of the supporting board, the semiconductor chip having an active surface having a plurality of the electrode pads; a protection layer formed on the active surface of the semiconductor chip, the protection layer having a plurality of openings corresponding to the electrode pads for exposure of the electrode pads of the semiconductor chip; a metal layer formed on surfaces of the electrode pads exposed from the openings of the protection layer; a dielectric layer formed on the supporting board and the protection layer surface, the dielectric layer having another plurality of openings corresponding to the electrode pads for exposure of the metal layer on the electrode pads of the semiconductor chip; a circuit layer formed on the dielectric layer, a plurality of hollow conductive vias being formed in the another openings of the dielectric layer and electrically connected to the circuit layer, allowing the circuit layer to be electrically connected via the hollow conductive vias to the metal layer on the electrode pads of the semiconductor chip.
  • a buffer metal layer is further installed between the metal layer and the hollow conductive vias.
  • the circuit board structure further includes a circuit build-up structure formed on the dielectric layer and circuit layer.
  • a plurality of fully-plated metal vias are formed in the circuit build-up structure and electrically connected to the circuit layer.
  • At least an electrical conductive pad is formed on the circuit build-up structure.
  • the circuit build-up structure includes a dielectric layer, a circuit layer stacked on the dielectric layer, and a fully-plated metal via formed in the dielectric layer.
  • the circuit build-up structure surface includes a solder mask having a plurality of openings for exposure of the electrical conductive pad of the circuit build-up structure.
  • the fully-plated metal via of the circuit build-up structure is extended to a bottom portion of the hollow conductive vias of the circuit layer.
  • the semiconductor chips are received in the cavities of the supporting board, then a circuit manufacturing process is preformed on the supporting board and the semiconductor chips to form the dielectric layer and the circuit layer, and last the hollow conductive vias are formed in the dielectric layer for electrically connecting the circuit layer to the electrode pads of the semiconductor chips. Therefore, through the installation of the hollow conductive vias, the composed units, such as the dielectric layer and the protection layer, both of which surround the hollow conductive vias, have approximately the same CTE, solve the problem that the dielectric layers formed in and outside of the hollow conductive vias have mismatched CTE.
  • the dielectric layers inside and outside of the hollow conductive vias are made of the same material, a thermal stress is greatly reduced, ensuring that the semiconductor chips will not be separated from the circuit build-up structure formed on the semiconductor chips and improve the electric quality of an electric produce having the circuit board structure.
  • a circuit build-up structure can be further formed on the dielectric layer and the circuit layer by using a circuit build-up manufacturing process, and the fully-plated metal vias of the circuit build-up structure are designed to extend to the hollow conductive vias of the circuit layer, so as to form a structure having stacked vias, which can be applied to a fine pitch circuit board. Therefore, the electric connection route is shortened, and a circuit layout is diversified.
  • FIG. 1 is a cross sectional view of a package member having a substrate embedded with semiconductor chips according to the prior art
  • FIG. 2 is a cross sectional view of a circuit board structure embedded with semiconductor chips of a first embodiment according to the present invention
  • FIG. 3 is a cross sectional view of a circuit board structure embedded with semiconductor chips of a second embodiment according to the present invention.
  • FIG. 4 is a cross sectional view of a circuit board structure embedded with semiconductor chips of a third embodiment according to the present invention.
  • FIG. 5 is a cross sectional view of a circuit board structure embedded with semiconductor chips of a fourth embodiment according to the present invention.
  • FIG. 6 is a cross sectional view of a circuit board structure embedded with semiconductor chips of a fifth embodiment according to the present invention.
  • FIG. 7 is a cross sectional view of a circuit board structure embedded with semiconductor chips of a sixth embodiment according to the present invention.
  • FIG. 2 is a cross sectional view of a circuit board structure embedded with semiconductor chips of a first embodiment according to the present invention.
  • the circuit board structure comprises a supporting board 20 , at least a semiconductor chip 21 , a protection layer 22 , a metal layer 23 , a dielectric layer 24 , a circuit layer 25 and a hollow conductive via 250 .
  • the supporting board 20 is a circuit board or a core board, which the circuit board has completed a former circuit manufacturing process.
  • the core board is made of a metal or non-metal material. At least a cavity 200 is formed in the supporting board 20 for receiving the semiconductor chip 21 .
  • the semiconductor chip 21 comprises an active surface 21 a and a non-active surface 21 b opposing to the active surface 21 a.
  • a plurality of the electrode pads 210 are formed on the active surface 21 a.
  • the protection layer 22 is formed on the active surface 21 a of the semiconductor chip 21 .
  • a plurality of openings 220 are formed in the protection layer 22 and positionally corresponding to the electrode pads 210 for exposure of the electrode pads 210 .
  • the metal layer 23 is formed on surfaces of the electrode pads 210 formed in the openings 220 of the protection layer 22 .
  • the metal layer 23 is a barrier layer such as a nickel/gold layer, for protecting the electrode pads 210 , which are installed under the metal layer 23 .
  • the dielectric layer 24 is formed on the supporting board 20 and the active surface 21 a of the semiconductor chip 21 . Another plurality of openings 240 are formed in the dielectric layer 24 and positionally corresponding to the electrode pads 210 for exposure of the electrode pads 210 .
  • the dielectric layer 24 comprises epoxy resin, polyimide, cyanate ester, glass fiber, bismaleimide Triazine (BT) or a combination of epoxy resin and fiber glass.
  • the circuit layer 25 is formed on the dielectric layer 24 .
  • a plurality of hollow conductive vias 250 are formed in the openings 240 of the dielectric layer 24 and electrically connected to the circuit layer 25 . Therefore, the circuit layer 25 can be electrically connected via the hollow conductive vias 250 to the electrode pads 210 of the semiconductor chip 21 .
  • the circuit layer 25 is a patterned copper layer, which is manufactured by a convention process known by those skilled, further description of the patterned copper layer hereby omitted.
  • the circuit board structure further comprises a solder mask 26 .
  • Another plurality of openings are formed in the solder mask 26 for exposure of electrical conductive pads (not shown) formed in the circuit layer 25 .
  • the hollow conductive vias 250 are fully filled by solder mask 26 .
  • a plurality of conductive components such as solder balls are then installed on the electrical conductive pads. Therefore, the semiconductor chip 21 can be electrically connected to the external devices.
  • a conductive structure formed in the openings 240 of the dielectric layer 24 is the hollow conductive vias 250 .
  • the installation of the hollow conductive vias 250 make the dielectric layer 24 , the solder mask 26 and the protection layer 22 , all of which surround the hollow conductive vias 250 , have matched CTE, so that the thermal stress is reduced, the circuit layer 25 is prevented from being separated from the electrode pads 210 of the semiconductor chip 21 , the circuit board structure is ensured to function normally.
  • the solder mask 26 , the dielectric layer 24 and the protection layer 22 are made of materials having approximately the same CTE.
  • areas surrounding the hollow conductive via 250 have approximately the same CTE, and the thermal stress generated by the circuit board structure in operation is greatly reduced.
  • FIG. 3 is a cross sectional view of a circuit board structure embedded with semiconductor chips of a second embodiment according to the present invention.
  • the circuit board structure of the second embodiment further comprises a buffer metal layer 30 .
  • the buffer metal layer 30 is formed between the hollow conductive via 250 and the metal layer 23 .
  • the buffer metal layer 30 is a copper layer. Therefore, if the metal layer 23 in not thick enough, the thickened buffer metal layer 30 can serve as a stop layer for a laser ablating process for forming the openings (i.e. blind vias) of the dielectric layer 24 , and the electrode pads 210 covered under the buffer metal layer 30 can be protected from damages.
  • FIG. 4 is a cross sectional view of a circuit board structure embedded with semiconductor chips of a third embodiment according to the present invention.
  • the circuit board structure of the third embodiment further comprises a circuit build-up structure 40 formed on the dielectric layer 24 and the circuit layer 25 .
  • the circuit build-up structure 40 comprises at least a dielectric layer 400 , a circuit layer 402 stacked on the dielectric layer 400 , and a fully-plated metal via 404 formed in the dielectric layer 400 for electrically connecting the circuit layer 402 to the circuit layer 25 .
  • a fully-plated metal via 404 formed in the dielectric layer 400 for electrically connecting the circuit layer 402 to the circuit layer 25 .
  • another hollow conductive via (not shown) can be used for serving as an electric signal transmission route between the circuit layer 402 and the circuit layer 25 .
  • the dielectric layer 400 is fully filled in the hollow conductive via 250 .
  • the dielectric layers 24 and 400 and the protection layer 22 have approximately the same CTE, preventing the circuit layer 402 from being separated from the electrode pads 210 due to a thermal stress resulting from the dielectric layers 24 and 400 and the protection layer 22 if the dielectric layers 24 and 400 and the protection layer 22 have mismatched CTEs.
  • the circuit build-up structure 40 further comprises a plurality of electrical conductive pads (not shown) formed on the circuit layer 402 .
  • a solder mask 26 is further formed on an external surface of the circuit build-up structure 40 for protecting circuitry under the solder mask 26 .
  • a plurality of openings are further formed for exposure of the electrical conductive pads of the circuit build-up structure 40 .
  • Conductive elements (such as solder balls) can then be installed on the electrical conductive pads, for completing the electrical conductive of the semiconductor chip 21 to an external device.
  • FIG. 5 is a cross sectional view of a circuit board structure embedded with semiconductor chips of a fourth embodiment according to the present invention.
  • the circuit board structure of the fourth embodiment further comprises a buffer metal layer 30 .
  • the buffer metal layer 30 is formed between the metal layer 23 and the hollow conductive via 250 .
  • the buffer metal layer 30 has functionalities the same as those of the buffer metal layer 30 of the second embodiment, further description hereby omitted.
  • FIG. 6 is a cross sectional view of a circuit board structure embedded with semiconductor chips of a fifth embodiment according to the present invention.
  • the circuit board structure of the fifth embodiment further comprises another fully-plated metal via 406 .
  • the another fully-plated metal via 406 is electrically connected to a bottom portion of the hollow conductive vias 250 formed in the circuit layer 25 in the beginning, so as to form a structure having stacked vias, which can be applied to a fine pitch circuit board. Therefore, the electric connection route is shortened, and a circuit layout is diversified.
  • FIG. 7 is a cross sectional view of a circuit board structure embedded with semiconductor chips of a sixth embodiment according to the present invention.
  • the circuit board structure of the sixth embodiment further comprises a buffer metal layer 30 .
  • the buffer metal layer 30 is formed between the metal layer 23 and the hollow conductive via 250 .
  • the buffer metal layer 30 has functionalities the same as those of the buffer metal layer 30 of the second embodiment, further description hereby omitted.
  • the semiconductor chips are received in the cavities of the supporting board, then a circuit manufacturing process is preformed on the supporting board and the semiconductor chips to form the dielectric layer and the circuit layer, and last the hollow conductive vias are formed in the dielectric layer for electrically connecting the circuit layer to the electrode pads of the semiconductor chips. Therefore, through the installation of the hollow conductive vias, the composed units, such as the dielectric layer and the protection layer, both of which surround the hollow conductive vias, have approximately the same CTE, solve the problem that the dielectric layers formed in and outside of the hollow conductive vias have mismatched CTE.
  • the dielectric layers inside and outside of the hollow conductive vias are made of the same material, a thermal stress is greatly reduced, ensuring that the semiconductor chips will not be separated from the circuit build-up structure formed on the semiconductor chips and improve the electric quality of an electric produce having the circuit board structure.
  • a circuit build-up structure can be further formed on the dielectric layer and the circuit layer by using a circuit build-up manufacturing process, and the fully-plated metal vias of the circuit build-up structure are designed to extend to the hollow conductive vias of the circuit layer, so as to form a structure having stacked vias, which can be applied to a fine pitch circuit board. Therefore, the electric connection route is shortened, and a circuit layout is diversified.

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Abstract

A circuit board structure embedded with semiconductor chips is proposed. A semiconductor chip is received in a cavity of a supporting board. A dielectric layer and a circuit layer are formed on the supporting board and the semiconductor chip. A plurality of hollow conductive vias are formed in the dielectric layer for electrically connecting the circuit layer to the semiconductor chip. By providing the hollow conductive vias of present invention, the separating results of different coefficients of expansion and thermal stress are prevented, and thus electrical function of products is ensured.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This application claims benefit under 35 USC 119 to Taiwan Application No. 095104315, filed Feb. 9, 2006.
    • FIELD OF THE INVENTION
  • This invention relates to circuit board structures, and more particularly, to a circuit board structure having hollow conductive vias for electrically connecting semiconductor chips and circuitry embedded in the circuit board structure.
    • BACKGROUND OF THE INVENTION
  • With the rapid development of semiconductor packaging techniques, semiconductor devices are brought to the market in various package types. In a process to manufacturing a semiconductor device, first a semiconductor chip is installed on a package substrate or a lead frame, then the semiconductor chip is electrically connected to the package substrate or the lead frame, and finally an encapsulant is covered on the semiconductor chip and the package substrate or the lead frame. A ball grid array (BGA) technique is one of the most advanced semiconductor packaging techniques. The BGA technique includes installing a semiconductor chip on a package substrate, and installing a plurality of array disposed solder balls on a rear surface of the package substrate by using a self-alignment technique. Therefore, a number of I/O connection terminals per unit area on a carrying member carried with the semiconductor chip is increased, and an integration demand for semiconductor chips is requested. The semiconductor chip is electrically connected via these solder balls to external devices.
  • The semiconductor packaging technique of the prior art, when manufacturing the semiconductor device, first adheres the semiconductor chip to a front surface of the package substrate, then performs wire bonding or flip chip packaging process on the semiconductor chip, and finally installs on the rear surface of the package substrate the solder balls, which electrically connect the semiconductor chip to the external devices. Although the semiconductor device manufactured by such a semiconductor package technique has increased number of I/O connection terminals and meets the requirement of high pin count, the electric characteristics of the semiconductor device, when operating at a high frequency, are severely restricted due to too long a conductive connection route. Moreover, the semiconductor packaging technique of the prior art needs to perform many times of connecting interface processes, so that a manufacturing process for the semiconductor device is complicated.
  • In order to solve the drawbacks of the prior art, R&D personnel for the semiconductor device try not to install the semiconductor chip on the package substrate, but embed the semiconductor chip into the package substrate instead, to shorten the conductive connection route, reduce signal loss and distortion, and improve the performance of the semiconductor device while operating at the high frequency.
  • FIG. 1 is a cross sectional view of a package member having a substrate embedded with semiconductor chips according to the prior art. The package member comprises a carrying board 10. At least a cavity 100 a is formed on a surface 100 of the carrying board 10. The package member further comprises at least a semiconductor chip 11 installed on the carrying board 10 and received in the cavity 100 a. A plurality of electrode pads 110 are formed on the semiconductor chip 11. The package member further comprises a circuit build-up structure 12 formed on the carrying board 10 and electrically connected via a plurality of conductive vias 120 to the electrode pads 110.
  • The semiconductor chip 11 comprises an active surface 11 a and a non-active surface 11 b opposing to the active surface 11 a. The electrode pads 110 are installed on the active surface 11 a. The non-active surface 11 b is formed in the cavity 100 a and adhered to the carrying board 10 by the use of an adhesive 13.
  • The circuit build-up structure 12 comprises at least a dielectric layer 121, a circuit layer 122 interlacing with the dielectric layer 121, and a plurality of conductive vias 120 passing through the dielectric layer 121 and electrically connected to the circuit layer 122 and the electrode pads 110. A plurality of electric connection terminals 123 are further formed on an outmost surface of the circuit layer 122 of the circuit build-up structure 12. A solder mask 124 is further formed on the outmost surface of the circuit layer 122. The solder mask 124 comprises a plurality of openings for exposure of the electric connection terminals 123. The electric connection terminals 123 are installed for plantation of a plurality of conductive elements such as solder balls 125. Therefore, the semiconductor chip 11 installed on the carrying board 10 and received in the cavity 100 a can be electrically connected via the electrode pads 110, the circuit build-up structure 12 and the solder balls 125 to the external device.
  • As described above, in the package member of the prior art, the circuit layer 122 is electrically connected via the conductive vias 120 directly to the semiconductor chip 11, and the conductive vias 120 are formed by plated copper in vias formed in an insulating layer, the vias being fully filled by the plated copper. However, because coefficients of thermal expansion (CTE) of composed components (such as the insulating layer and a protection layer for protecting the semiconductor chip) surrounding the conductive vias 120 are mismatched, thermal expansion of the composed components are different from each other. In result, a thermal stress is produced in the package member, the formed circuit structure is likely separated from the electrode pads 110 of the semiconductor chip 11 due to the thermal stress, and the package member is thus malfunctioned.
  • Moreover, in order to satisfy the demand of fine pitch and reduction of signal transmission route, the conductive vias 120 for connection of circuitry are formed to have a stack structure. However, because the composed units surrounding the conductive vias 120 have different CTEs, and thermal stress produced in the package member are therefore mismatched, the circuit structure is easily separated from the electrode pads 120 of the semiconductor chip 11. In result, the demand of fine pitch can not be attained and the package member has poor reliability.
  • Therefore, how to provide an electric connection structure of a circuit board embedded with semiconductor chips to overcome the drawbacks of the prior art has becoming one of the most urgent issues in the art.
    • SUMMARY OF THE INVENTION
  • In views of the above-mentioned problems of the prior art, it is a primary objective of the present invention to provide a circuit board structure embedded with semiconductor chips, for improving electric characteristics of a product having the circuit board structure and preventing electric pads of the semiconductor chips from being separated from a circuit build-up structure.
  • It is another objective of the present invention to provide a circuit board structure embedded with semiconductor chips, for increasing the yield and reliability of the product.
  • It is a further objective of the present invention to provide a circuit board structure embedded with semiconductor chips. Compared to the prior art, the circuit board structure of the present invention has a shorter electric transmission route and diversified circuit layout.
  • To achieve the above-mentioned and other objectives, a circuit board structure embedded with semiconductor chips. The circuit board structure includes a supporting board having at least a cavity; at least a semiconductor chip embedded in the cavity of the supporting board, the semiconductor chip having an active surface having a plurality of the electrode pads; a protection layer formed on the active surface of the semiconductor chip, the protection layer having a plurality of openings corresponding to the electrode pads for exposure of the electrode pads of the semiconductor chip; a metal layer formed on surfaces of the electrode pads exposed from the openings of the protection layer; a dielectric layer formed on the supporting board and the protection layer surface, the dielectric layer having another plurality of openings corresponding to the electrode pads for exposure of the metal layer on the electrode pads of the semiconductor chip; a circuit layer formed on the dielectric layer, a plurality of hollow conductive vias being formed in the another openings of the dielectric layer and electrically connected to the circuit layer, allowing the circuit layer to be electrically connected via the hollow conductive vias to the metal layer on the electrode pads of the semiconductor chip.
  • According to another embodiment, a buffer metal layer is further installed between the metal layer and the hollow conductive vias.
  • According to another embodiment, the circuit board structure further includes a circuit build-up structure formed on the dielectric layer and circuit layer. A plurality of fully-plated metal vias are formed in the circuit build-up structure and electrically connected to the circuit layer. At least an electrical conductive pad is formed on the circuit build-up structure. The circuit build-up structure includes a dielectric layer, a circuit layer stacked on the dielectric layer, and a fully-plated metal via formed in the dielectric layer. The circuit build-up structure surface includes a solder mask having a plurality of openings for exposure of the electrical conductive pad of the circuit build-up structure.
  • According to another embodiment, the fully-plated metal via of the circuit build-up structure is extended to a bottom portion of the hollow conductive vias of the circuit layer.
  • In summary, in the circuit board structure embedded with semiconductor chips the semiconductor chips are received in the cavities of the supporting board, then a circuit manufacturing process is preformed on the supporting board and the semiconductor chips to form the dielectric layer and the circuit layer, and last the hollow conductive vias are formed in the dielectric layer for electrically connecting the circuit layer to the electrode pads of the semiconductor chips. Therefore, through the installation of the hollow conductive vias, the composed units, such as the dielectric layer and the protection layer, both of which surround the hollow conductive vias, have approximately the same CTE, solve the problem that the dielectric layers formed in and outside of the hollow conductive vias have mismatched CTE. Moreover, because the dielectric layers inside and outside of the hollow conductive vias are made of the same material, a thermal stress is greatly reduced, ensuring that the semiconductor chips will not be separated from the circuit build-up structure formed on the semiconductor chips and improve the electric quality of an electric produce having the circuit board structure.
  • Further, a circuit build-up structure can be further formed on the dielectric layer and the circuit layer by using a circuit build-up manufacturing process, and the fully-plated metal vias of the circuit build-up structure are designed to extend to the hollow conductive vias of the circuit layer, so as to form a structure having stacked vias, which can be applied to a fine pitch circuit board. Therefore, the electric connection route is shortened, and a circuit layout is diversified.
    • BRIEF DESCRIPTION OF DRAWINGS
  • The invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein:
  • FIG. 1 is a cross sectional view of a package member having a substrate embedded with semiconductor chips according to the prior art;
  • FIG. 2 is a cross sectional view of a circuit board structure embedded with semiconductor chips of a first embodiment according to the present invention;
  • FIG. 3 is a cross sectional view of a circuit board structure embedded with semiconductor chips of a second embodiment according to the present invention;
  • FIG. 4 is a cross sectional view of a circuit board structure embedded with semiconductor chips of a third embodiment according to the present invention;
  • FIG. 5 is a cross sectional view of a circuit board structure embedded with semiconductor chips of a fourth embodiment according to the present invention;
  • FIG. 6 is a cross sectional view of a circuit board structure embedded with semiconductor chips of a fifth embodiment according to the present invention; and
  • FIG. 7 is a cross sectional view of a circuit board structure embedded with semiconductor chips of a sixth embodiment according to the present invention.
    •  DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
  • The following illustrative embodiments are provided to illustrate the disclosure of the present invention, these and other advantages and effects can be apparently understood by those in the art after reading the disclosure of this specification. The present invention can also be performed or applied by other different embodiments. The details of the specification may be on the basis of different points and applications, and numerous modifications and variations can be devised without departing from the spirit of the present invention.
    • First Embodiment
  • FIG. 2 is a cross sectional view of a circuit board structure embedded with semiconductor chips of a first embodiment according to the present invention. The circuit board structure comprises a supporting board 20, at least a semiconductor chip 21, a protection layer 22, a metal layer 23, a dielectric layer 24, a circuit layer 25 and a hollow conductive via 250.
  • The supporting board 20 is a circuit board or a core board, which the circuit board has completed a former circuit manufacturing process. The core board is made of a metal or non-metal material. At least a cavity 200 is formed in the supporting board 20 for receiving the semiconductor chip 21.
  • The semiconductor chip 21 comprises an active surface 21 a and a non-active surface 21 b opposing to the active surface 21 a. A plurality of the electrode pads 210 are formed on the active surface 21 a.
  • The protection layer 22 is formed on the active surface 21 a of the semiconductor chip 21. A plurality of openings 220 are formed in the protection layer 22 and positionally corresponding to the electrode pads 210 for exposure of the electrode pads 210.
  • The metal layer 23 is formed on surfaces of the electrode pads 210 formed in the openings 220 of the protection layer 22. The metal layer 23 is a barrier layer such as a nickel/gold layer, for protecting the electrode pads 210, which are installed under the metal layer 23.
  • The dielectric layer 24 is formed on the supporting board 20 and the active surface 21 a of the semiconductor chip 21. Another plurality of openings 240 are formed in the dielectric layer 24 and positionally corresponding to the electrode pads 210 for exposure of the electrode pads 210. According to the first embodiment, the dielectric layer 24 comprises epoxy resin, polyimide, cyanate ester, glass fiber, bismaleimide Triazine (BT) or a combination of epoxy resin and fiber glass.
  • The circuit layer 25 is formed on the dielectric layer 24. A plurality of hollow conductive vias 250 are formed in the openings 240 of the dielectric layer 24 and electrically connected to the circuit layer 25. Therefore, the circuit layer 25 can be electrically connected via the hollow conductive vias 250 to the electrode pads 210 of the semiconductor chip 21. The circuit layer 25 is a patterned copper layer, which is manufactured by a convention process known by those skilled, further description of the patterned copper layer hereby omitted.
  • The circuit board structure further comprises a solder mask 26. Another plurality of openings (not shown) are formed in the solder mask 26 for exposure of electrical conductive pads (not shown) formed in the circuit layer 25. The hollow conductive vias 250 are fully filled by solder mask 26. A plurality of conductive components such as solder balls are then installed on the electrical conductive pads. Therefore, the semiconductor chip 21 can be electrically connected to the external devices.
  • One of the characteristics of the circuit board structure embedded with semiconductor chips of the present invention is that a conductive structure formed in the openings 240 of the dielectric layer 24 is the hollow conductive vias 250. The installation of the hollow conductive vias 250 make the dielectric layer 24, the solder mask 26 and the protection layer 22, all of which surround the hollow conductive vias 250, have matched CTE, so that the thermal stress is reduced, the circuit layer 25 is prevented from being separated from the electrode pads 210 of the semiconductor chip 21, the circuit board structure is ensured to function normally. Preferably, the solder mask 26, the dielectric layer 24 and the protection layer 22 are made of materials having approximately the same CTE. Thus, areas surrounding the hollow conductive via 250 have approximately the same CTE, and the thermal stress generated by the circuit board structure in operation is greatly reduced.
    • Second Embodiment
  • FIG. 3 is a cross sectional view of a circuit board structure embedded with semiconductor chips of a second embodiment according to the present invention.
  • Compared with the circuit board structure of the first embodiment, the circuit board structure of the second embodiment further comprises a buffer metal layer 30.
  • The buffer metal layer 30 is formed between the hollow conductive via 250 and the metal layer 23. According to the second embodiment, the buffer metal layer 30 is a copper layer. Therefore, if the metal layer 23 in not thick enough, the thickened buffer metal layer 30 can serve as a stop layer for a laser ablating process for forming the openings (i.e. blind vias) of the dielectric layer 24, and the electrode pads 210 covered under the buffer metal layer 30 can be protected from damages.
    • Third Embodiment
  • FIG. 4 is a cross sectional view of a circuit board structure embedded with semiconductor chips of a third embodiment according to the present invention.
  • Compared with the circuit board structure of the first embodiment, the circuit board structure of the third embodiment further comprises a circuit build-up structure 40 formed on the dielectric layer 24 and the circuit layer 25.
  • The circuit build-up structure 40 comprises at least a dielectric layer 400, a circuit layer 402 stacked on the dielectric layer 400, and a fully-plated metal via 404 formed in the dielectric layer 400 for electrically connecting the circuit layer 402 to the circuit layer 25. Of course, another hollow conductive via (not shown) can be used for serving as an electric signal transmission route between the circuit layer 402 and the circuit layer 25.
  • The dielectric layer 400 is fully filled in the hollow conductive via 250. Through the design of the hollow conductive via 250, the dielectric layers 24 and 400 and the protection layer 22 have approximately the same CTE, preventing the circuit layer 402 from being separated from the electrode pads 210 due to a thermal stress resulting from the dielectric layers 24 and 400 and the protection layer 22 if the dielectric layers 24 and 400 and the protection layer 22 have mismatched CTEs.
  • The circuit build-up structure 40 further comprises a plurality of electrical conductive pads (not shown) formed on the circuit layer 402. A solder mask 26 is further formed on an external surface of the circuit build-up structure 40 for protecting circuitry under the solder mask 26. A plurality of openings (not shown) are further formed for exposure of the electrical conductive pads of the circuit build-up structure 40. Conductive elements (such as solder balls) can then be installed on the electrical conductive pads, for completing the electrical conductive of the semiconductor chip 21 to an external device.
    • Fourth Embodiment
  • FIG. 5 is a cross sectional view of a circuit board structure embedded with semiconductor chips of a fourth embodiment according to the present invention.
  • Compared with the circuit board structure of the third embodiment, the circuit board structure of the fourth embodiment further comprises a buffer metal layer 30.
  • The buffer metal layer 30 is formed between the metal layer 23 and the hollow conductive via 250. The buffer metal layer 30 has functionalities the same as those of the buffer metal layer 30 of the second embodiment, further description hereby omitted.
    • Fifth Embodiment
  • FIG. 6 is a cross sectional view of a circuit board structure embedded with semiconductor chips of a fifth embodiment according to the present invention.
  • Compared with the circuit board structure of the third embodiment, the circuit board structure of the fifth embodiment further comprises another fully-plated metal via 406.
  • The another fully-plated metal via 406 is electrically connected to a bottom portion of the hollow conductive vias 250 formed in the circuit layer 25 in the beginning, so as to form a structure having stacked vias, which can be applied to a fine pitch circuit board. Therefore, the electric connection route is shortened, and a circuit layout is diversified.
    • Sixth Embodiment
  • FIG. 7 is a cross sectional view of a circuit board structure embedded with semiconductor chips of a sixth embodiment according to the present invention.
  • Compared with the circuit board structure of the fifth embodiment, the circuit board structure of the sixth embodiment further comprises a buffer metal layer 30.
  • The buffer metal layer 30 is formed between the metal layer 23 and the hollow conductive via 250. The buffer metal layer 30 has functionalities the same as those of the buffer metal layer 30 of the second embodiment, further description hereby omitted.
  • In summary, in the circuit board structure embedded with semiconductor chips the semiconductor chips are received in the cavities of the supporting board, then a circuit manufacturing process is preformed on the supporting board and the semiconductor chips to form the dielectric layer and the circuit layer, and last the hollow conductive vias are formed in the dielectric layer for electrically connecting the circuit layer to the electrode pads of the semiconductor chips. Therefore, through the installation of the hollow conductive vias, the composed units, such as the dielectric layer and the protection layer, both of which surround the hollow conductive vias, have approximately the same CTE, solve the problem that the dielectric layers formed in and outside of the hollow conductive vias have mismatched CTE. Moreover, because the dielectric layers inside and outside of the hollow conductive vias are made of the same material, a thermal stress is greatly reduced, ensuring that the semiconductor chips will not be separated from the circuit build-up structure formed on the semiconductor chips and improve the electric quality of an electric produce having the circuit board structure.
  • Further, a circuit build-up structure can be further formed on the dielectric layer and the circuit layer by using a circuit build-up manufacturing process, and the fully-plated metal vias of the circuit build-up structure are designed to extend to the hollow conductive vias of the circuit layer, so as to form a structure having stacked vias, which can be applied to a fine pitch circuit board. Therefore, the electric connection route is shortened, and a circuit layout is diversified.
  • The foregoing descriptions of the detailed embodiments are only illustrated to disclose the features and functions of the present invention and not restrictive of the scope of the present invention. It should be understood to those in the art that all modifications and variations according to the spirit and principle in the disclosure of the present invention should fall within the scope of the appended claims.

Claims (12)

1. A circuit board structure embedded with semiconductor chips, the circuit board structure comprising:
a supporting board having at least a cavity;
at least a semiconductor chip embedded in the cavity of the supporting board, the semiconductor chip having an active surface having a plurality of the electrode pads;
a protection layer formed on the active surface of the semiconductor chip, the protection layer having a plurality of openings corresponding to the electrode pads for exposure of the electrode pads of the semiconductor chip;
a metal layer formed on surfaces of the electrode pads exposed from the openings of the protection layer;
a dielectric layer formed on the supporting board and the protection layer surface, the dielectric layer having another plurality of openings corresponding to the electrode pads for exposure of the metal layer on the electrode pads of the semiconductor chip; and
a circuit layer formed on the dielectric layer, a plurality of hollow conductive vias being formed in the another openings of the dielectric layer and electrically connected to the circuit layer, allowing the circuit layer to be electrically connected via the hollow conductive vias to the metal layer on the electrode pads of the semiconductor chip.
2. The circuit board structure of claim 1, wherein supporting board is a circuit board or a core board, which the circuit board has completed a former circuit manufacturing process.
3. The circuit board structure of claim 2, wherein the core board is made of metal or nonmetal materials.
4. The circuit board structure of claim 1 further comprising a buffer metal layer formed between the metal layer and the hollow conductive vias.
5. The circuit board structure of claim 4 further comprising a circuit build-up structure formed on the dielectric layer and the circuit layer, a plurality of fully-plated metal vias being formed in the circuit build-up structure and electrically connected to the circuit layer, an electrical conductive pad being formed on the circuit build-up structure.
6. The circuit board structure of claim 5 further comprising a solder mask formed on an external surface of the circuit build-up structure, the solder mask having a mask opening for exposure of the electrical conductive pad of the circuit build-up structure.
7. The circuit board structure of claim 5, wherein the circuit build-up structure comprises at least a dielectric layer, a circuit layer stacked on the dielectric layer, and a fully-plated metal via formed in the dielectric layer.
8. The circuit board structure of claim 5, wherein the fully-plated metal via is extended to a bottom portion of the hollow conductive vias of the circuit layer.
9. The circuit board structure of claim 1 further comprising a circuit build-up structure formed on the dielectric layer and the circuit layer, a plurality of fully-plated metal vias being formed in the circuit build-up structure and electrically connected to the circuit layer, an electrical conductive pad being formed on the circuit build-up structure.
10. The circuit board structure of claim 9 further comprising a solder mask formed on an external surface of the circuit build-up structure, the solder mask having a mask opening for exposure of the electrical conductive pad of the circuit build-up structure.
11. The circuit board structure of claim 9, wherein the circuit build-up structure comprises at least a dielectric layer, a circuit layer stacked on the dielectric layer, and a fully-plated metal via formed in the dielectric layer.
12. The circuit board structure of claim 9, wherein the fully-plated metal via is extended to a bottom portion of the hollow conductive vias of the circuit layer.
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US7863729B2 (en) 2011-01-04
TWI310968B (en) 2009-06-11
US20090200658A1 (en) 2009-08-13

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