+

US20070096271A1 - Substrate frame - Google Patents

Substrate frame Download PDF

Info

Publication number
US20070096271A1
US20070096271A1 US11/642,583 US64258306A US2007096271A1 US 20070096271 A1 US20070096271 A1 US 20070096271A1 US 64258306 A US64258306 A US 64258306A US 2007096271 A1 US2007096271 A1 US 2007096271A1
Authority
US
United States
Prior art keywords
wiring
wiring substrate
substrate
pads
substrate frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/642,583
Inventor
Norio Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to US11/642,583 priority Critical patent/US20070096271A1/en
Publication of US20070096271A1 publication Critical patent/US20070096271A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/1016—Shape being a cuboid
    • H01L2924/10162—Shape being a cuboid with a square active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09063—Holes or slots in insulating substrate not used for electrical connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
    • H05K2201/2009—Reinforced areas, e.g. for a specific part of a flexible printed circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15—Position of the PCB during processing
    • H05K2203/1545—Continuous processing, i.e. involving rolls moving a band-like or solid carrier along a continuous production path
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49121—Beam lead frame or beam lead device
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24273—Structurally defined web or sheet [e.g., overall dimension, etc.] including aperture
    • Y10T428/24298—Noncircular aperture [e.g., slit, diamond, rectangular, etc.]
    • Y10T428/24314—Slit or elongated

Definitions

  • the present invention relates to a substrate frame for connecting to external terminals the electrodes of semiconductor chips mounted on the substrate frame and a method of making semiconductor devices using the substrate frame.
  • Japanese patent application Kokai No. 11-87386 discloses such a semiconductor device as shown in FIGS. 2 ( a ) and 2 ( b ), wherein a semiconductor chip 2 is mounted on the first surface of a wiring substrate 1 with a conductive or insulative adhesive 3 , with the circuit forming surface facing up.
  • a plurality of pads or connecting electrodes 1 a and their wirings are formed on the first surface of the wiring substrate 1 .
  • the pads 1 a are exposed but the wirings and the other area are covered by a solder resist.
  • a plurality of wires 4 connect the pads 1 a and the pads 2 a of the semiconductor chip 2 .
  • the semiconductor chip 2 , the adhesive 3 , and the wires 4 are covered by a resin such as epoxy resin.
  • a plurality of pads and their wirings are formed on the second surface opposed to the first surface of the wiring substrate 1 . Similarly to the first surface, the pads are exposed but the wirings and the other area are covered by a solder resist. A plurality of external terminals or solder balls 6 are joined to the pads on the second surface. It is understood that the wirings on the first and second surfaces are connected via through-holes.
  • a substrate frame 10 is prepared by bonding a pair of copper foils on opposite surfaces of an insulating board and forming a row of wiring substrate regions 11 at predetermined intervals on each surface.
  • both the surfaces are etched to form wiring patterns that include pads on the first and second surfaces of a wiring substrate 1 ( FIG. 2 ( a )) and through holes provided at predetermined locations for connecting the wiring patterns on the first and second surfaces.
  • a nickel-gold (NiAu) electrolytic plating is applied to the interiors of the through holes for connecting the wiring patters and to the pads for increasing the bonding property with the wires 4 and the solder balls 6 .
  • a solder resist is applied to the wiring patterns and the other area but the pads.
  • a plurality of slits 12 are provided between the wiring substrate regions 11 and have a length less than that of the wiring substrate regions 11 .
  • a plurality of slits 14 are provided in the ear portions 13 of the substrate frame 10 and have a length less that that of the wiring substrate regions 11 .
  • These slits 12 and 14 are formed by a router process.
  • a semiconductor chip 2 is bonded to a central mounting area 11 a of the wiring substrate region 11 with a bond 3 .
  • the pads 1 a of the wiring substrate region 11 and the pads 2 a of the semiconductor chip 2 are connected with wires 4 .
  • the semiconductor chip 2 , the bond 3 , and the wires 4 within a package area 11 b are enclosed with a resinous mass 5 .
  • a plurality of solder balls 6 are joined to the pads on the second surface of the wiring substrate region 11 .
  • the ear portions at the four corners of the wiring substrate region 11 are punched off to provide individual semiconductor devices.
  • the conventional semiconductor device suffers from the following disadvantages.
  • a pair of lead patters are formed between the wiring substrate region 11 and the ear portion 13 of the substrate frame 10 for electroplating the wiring pattern.
  • the punching at the four corners of the wiring substrate region 11 can damage the cut face, lowering the reliability.
  • the punching may be replaced by cutting the four corners with a rotary saw.
  • the saw cutting requires cutting in the vertical and lateral directions, lowering the productivity, especially, of large BGA.
  • a substrate frame comprising an insulative board having a pair of ear portions extending along its longitudinal edges; a plurality of wiring substrate regions arranged on the insulative board between the ear portions at predetermined intervals; and a plurality of grooves provided around the wiring substrate regions from which wiring patterns are removed.
  • the grooves may be made by boundaries of said wiring substrate regions for punching to provide individual semiconductor devices.
  • FIG. 1 is a plan view of a substrate frame according to the first embodiment of the invention
  • FIG. 2 ( a ) is a perspective view of a conventional semiconductor device
  • FIG. 2 ( b ) is a sectional view taken along line A-A of FIG. 2 ( a );
  • FIG. 2 ( c ) is a plan view of a substrate frame for the semiconductor device
  • FIG. 3 ( a ) is a plan view of a substrate frame according to the second embodiment of the invention.
  • FIG. 3 ( b ) is a sectional view taken along line B-B of FIG. 3 ( a ).
  • a substrate frame 10 A is provided to replace the substrate frame 10 in FIG. 2 ( c ). Similarly to the substrate frame 10 , this frame 10 A is made by bonding a pair of copper foils to opposite surfaces of an insulative board and forming a row of wiring substrate regions 11 at predetermined intervals on each surface. The opposite surfaces of each wiring substrate region 11 are etched to form wiring patterns that include pads 1 a and 1 b on the first and second surfaces of the wiring substrate 1 and through-holes provided at predetermined locations for connecting the wiring patterns on the first and second surfaces.
  • the interiors of the through-holes are plated to connect the wiring patterns but a nickel-gold electrolytic plating is applied to the pads 1 a and 1 b to increase the bonding property with the wires and solder balls.
  • a solder resist is coated on the wiring patterns and the other area except for the pads 1 a and 1 b.
  • a plurality of slits 15 are provided between the wiring substrate regions 11 of the substrate frame 10 A and have a length greater than that of the wiring substrate regions 11 , extending across the ear portions 13 of the substrate frame 10 A. Thus, the slits 15 separate the adjacent wiring substrate regions 11 . These slits 15 are made by a router process.
  • a plurality of semiconductor chips 2 are bonded to the central mounting areas 11 a of wiring substrate regions 11 with a bond 3 ( FIG. 2 ( a )). Then, the pads 1 a of a wiring substrate region 11 and the pads 2 a of a semiconductor chip 2 are connected with bonding wires 4 . Then, the semiconductor chip 2 , the bond 3 , and the wires 4 within a package area 11 b are enclosed with a resinous mass 5 . The solder balls 6 are joined to the pads 1 b on the second surface of the wiring substrate region 11 . Then, the ear portions 13 of the substrate frame 10 A are cut off with a rotary saw to provide individual semiconductor devices.
  • the wiring substrate regions 11 of the substrate frame 10 A are separated completely by the slits 15 .
  • a substrate frame 10 B is used to replace the substrate frame 10 of FIG. 2 ( c ).
  • this substrate frame 10 B is made by bonding a pair of copper foils to opposite surfaces of an insulative board 10 a to form a both sided substrate and forming thereon a row of wiring substrate regions 11 at predetermined intervals.
  • the copper foils 10 b of the both sided substrate are etched to form wiring patterns that include pads 1 a and 1 b on the first and second surfaces of the wiring substrate 1 and through-holes at predetermined locations for connecting the wiring patterns on the first and second surfaces.
  • the interiors of the through-holes are plated to connect the wiring patterns electrically.
  • a solder resist 10 c is coated over the wiring patterns and the other areas except for the pads 1 a and 1 b , to which a nickel-gold electrolytic plating is applied to increase the bonding property with the wire and the solder balls.
  • a plurality of slits 17 are formed between the wiring substrate regions 11 by a router process to reduce the processing stress.
  • a groove 18 is provided around each wiring substrate region 11 by removing the copper foil 10 b and the solder resist 10 c in a predetermined width.
  • a both sided substrate is prepared by bonding a pair of copper foils 10 b to opposite surfaces of an insulative board 10 a.
  • the copper foils 10 c on the opposite sides are etched by the photolithographic technology to form wiring patterns that include wiring substrate regions 11 provided at predetermined intervals.
  • the wiring patterns also include pads 1 a and 1 b , and lead patterns for electrolytic plating.
  • a plurality of through-holes are provided to connect the wiring patterns on the opposite sides of the wiring substrate 1 .
  • a plurality of holes 16 are provided in the ear portions 13 for transportation.
  • a solder resist 10 c is coated to the area other than the pads 1 a and 1 b and the grooves 18 , and a nickel-gold electrolytic plating is applied to the pads 1 a and 1 b.
  • a semiconductor chip 2 is bonded with a bond 3 to a central mounting area 11 a of the wiring substrate region 11 , and the pads 1 a of the wiring substrate region 11 and the pad 2 a of the semiconductor chip 2 are connected with wires 4 .
  • solder balls 6 are joined to the pads 1 b on the second surface of the wiring substrate region 11 .
  • the grooves 18 of the wiring substrate regions 11 are punched with a metal mold to provide individual semiconductor devices.
  • the substrate frame 10 B has the grooves 18 from which the wiring patterns have been removed so that individual semiconductor devices are separated without any damage to the cut surfaces merely by punching the grooves 18 .
  • the substrate frame 10 A or 10 B may be applied to a multi-layer substrate having three or more wiring layers.
  • the wire bonding between the wiring substrate 1 and the semiconductor chip 2 may be replaced by the flip chip bonding.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Structure Of Printed Boards (AREA)
  • Wire Bonding (AREA)

Abstract

A substrate frame includes an insulative board (10 a) having a pair of ear portions (13) extending along its longitudinal edges; a plurality of wiring substrate regions (11) arranged on the insulative board (10 a) between the ear portions (13) at predetermined intervals; and a plurality of grooves (18) provided around said wiring substrate regions (11) from which wiring patterns are removed.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This is a divisional application of prior application Ser. No. 10/911,477 filed Aug. 5, 2004.
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to a substrate frame for connecting to external terminals the electrodes of semiconductor chips mounted on the substrate frame and a method of making semiconductor devices using the substrate frame.
  • 2. Description of the Related Art
  • Japanese patent application Kokai No. 11-87386 discloses such a semiconductor device as shown in FIGS. 2(a) and 2(b), wherein a semiconductor chip 2 is mounted on the first surface of a wiring substrate 1 with a conductive or insulative adhesive 3, with the circuit forming surface facing up. A plurality of pads or connecting electrodes 1 a and their wirings (not shown) are formed on the first surface of the wiring substrate 1. The pads 1 a are exposed but the wirings and the other area are covered by a solder resist. A plurality of wires 4 connect the pads 1 a and the pads 2 a of the semiconductor chip 2. The semiconductor chip 2, the adhesive 3, and the wires 4 are covered by a resin such as epoxy resin.
  • A plurality of pads and their wirings are formed on the second surface opposed to the first surface of the wiring substrate 1. Similarly to the first surface, the pads are exposed but the wirings and the other area are covered by a solder resist. A plurality of external terminals or solder balls 6 are joined to the pads on the second surface. It is understood that the wirings on the first and second surfaces are connected via through-holes.
  • How to make such a semiconductor device will be described.
  • As shown in FIG. 2(c), a substrate frame 10 is prepared by bonding a pair of copper foils on opposite surfaces of an insulating board and forming a row of wiring substrate regions 11 at predetermined intervals on each surface. On each wiring substrate, both the surfaces are etched to form wiring patterns that include pads on the first and second surfaces of a wiring substrate 1 (FIG. 2(a)) and through holes provided at predetermined locations for connecting the wiring patterns on the first and second surfaces. A nickel-gold (NiAu) electrolytic plating is applied to the interiors of the through holes for connecting the wiring patters and to the pads for increasing the bonding property with the wires 4 and the solder balls 6. A solder resist is applied to the wiring patterns and the other area but the pads.
  • A plurality of slits 12 are provided between the wiring substrate regions 11 and have a length less than that of the wiring substrate regions 11. A plurality of slits 14 are provided in the ear portions 13 of the substrate frame 10 and have a length less that that of the wiring substrate regions 11. These slits 12 and 14 are formed by a router process. A semiconductor chip 2 is bonded to a central mounting area 11 a of the wiring substrate region 11 with a bond 3. Then, the pads 1 a of the wiring substrate region 11 and the pads 2 a of the semiconductor chip 2 are connected with wires 4. Then, the semiconductor chip 2, the bond 3, and the wires 4 within a package area 11 bare enclosed with a resinous mass 5. A plurality of solder balls 6 are joined to the pads on the second surface of the wiring substrate region 11. Finally, the ear portions at the four corners of the wiring substrate region 11 are punched off to provide individual semiconductor devices.
  • However, the conventional semiconductor device suffers from the following disadvantages.
  • A pair of lead patters are formed between the wiring substrate region 11 and the ear portion 13 of the substrate frame 10 for electroplating the wiring pattern. The punching at the four corners of the wiring substrate region 11 can damage the cut face, lowering the reliability. The punching may be replaced by cutting the four corners with a rotary saw. The saw cutting, however, requires cutting in the vertical and lateral directions, lowering the productivity, especially, of large BGA.
    • SUMMARY OF THE INVENTION
  • Accordingly, it is an object of the invention to provide a substrate frame having the improved productivity.
  • According to the invention there is provided a substrate frame comprising an insulative board having a pair of ear portions extending along its longitudinal edges; a plurality of wiring substrate regions arranged on the insulative board between the ear portions at predetermined intervals; and a plurality of grooves provided around the wiring substrate regions from which wiring patterns are removed.
  • The grooves may be made by boundaries of said wiring substrate regions for punching to provide individual semiconductor devices.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a plan view of a substrate frame according to the first embodiment of the invention;
  • FIG. 2(a) is a perspective view of a conventional semiconductor device;
  • FIG. 2(b) is a sectional view taken along line A-A of FIG. 2(a);
  • FIG. 2(c) is a plan view of a substrate frame for the semiconductor device;
  • FIG. 3(a) is a plan view of a substrate frame according to the second embodiment of the invention;
  • FIG. 3(b) is a sectional view taken along line B-B of FIG. 3(a).
    • DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment
  • In FIG. 1, a substrate frame 10A is provided to replace the substrate frame 10 in FIG. 2(c). Similarly to the substrate frame 10, this frame 10A is made by bonding a pair of copper foils to opposite surfaces of an insulative board and forming a row of wiring substrate regions 11 at predetermined intervals on each surface. The opposite surfaces of each wiring substrate region 11 are etched to form wiring patterns that include pads 1 a and 1 b on the first and second surfaces of the wiring substrate 1 and through-holes provided at predetermined locations for connecting the wiring patterns on the first and second surfaces. The interiors of the through-holes are plated to connect the wiring patterns but a nickel-gold electrolytic plating is applied to the pads 1 a and 1 b to increase the bonding property with the wires and solder balls. A solder resist is coated on the wiring patterns and the other area except for the pads 1 a and 1 b.
  • A plurality of slits 15 are provided between the wiring substrate regions 11 of the substrate frame 10A and have a length greater than that of the wiring substrate regions 11, extending across the ear portions 13 of the substrate frame 10A. Thus, the slits 15 separate the adjacent wiring substrate regions 11. These slits 15 are made by a router process.
  • How to make semiconductor devices with the substrate frame 10A will be described below.
  • A plurality of semiconductor chips 2 are bonded to the central mounting areas 11 a of wiring substrate regions 11 with a bond 3 (FIG. 2(a)). Then, the pads 1 a of a wiring substrate region 11 and the pads 2 a of a semiconductor chip 2 are connected with bonding wires 4. Then, the semiconductor chip 2, the bond 3, and the wires 4 within a package area 11 bare enclosed with a resinous mass 5. The solder balls 6 are joined to the pads 1 b on the second surface of the wiring substrate region 11. Then, the ear portions 13 of the substrate frame 10A are cut off with a rotary saw to provide individual semiconductor devices.
  • As has been described above, the wiring substrate regions 11 of the substrate frame 10A are separated completely by the slits 15. Thus, it is possible to provide individual semiconductor devices by cutting in only one direction without damage to the cut surface.
    • Second Embodiment
  • In FIG. 3(a), a substrate frame 10B is used to replace the substrate frame 10 of FIG. 2(c). Similarly to the substrate frame 10, this substrate frame 10B is made by bonding a pair of copper foils to opposite surfaces of an insulative board 10 a to form a both sided substrate and forming thereon a row of wiring substrate regions 11 at predetermined intervals. The copper foils 10 b of the both sided substrate are etched to form wiring patterns that include pads 1 a and 1 b on the first and second surfaces of the wiring substrate 1 and through-holes at predetermined locations for connecting the wiring patterns on the first and second surfaces. The interiors of the through-holes are plated to connect the wiring patterns electrically.
  • Then, a solder resist 10 c is coated over the wiring patterns and the other areas except for the pads 1 a and 1 b, to which a nickel-gold electrolytic plating is applied to increase the bonding property with the wire and the solder balls. A plurality of slits 17 are formed between the wiring substrate regions 11 by a router process to reduce the processing stress. A groove 18 is provided around each wiring substrate region 11 by removing the copper foil 10 b and the solder resist 10 c in a predetermined width.
  • How to make semiconductor devices with the substrate frame 10B will be described below.
  • (1) A both sided substrate is prepared by bonding a pair of copper foils 10 b to opposite surfaces of an insulative board 10 a. The copper foils 10 c on the opposite sides are etched by the photolithographic technology to form wiring patterns that include wiring substrate regions 11 provided at predetermined intervals. The wiring patterns also include pads 1 a and 1 b, and lead patterns for electrolytic plating.
  • (2) A plurality of through-holes are provided to connect the wiring patterns on the opposite sides of the wiring substrate 1. A plurality of holes 16 are provided in the ear portions 13 for transportation. A solder resist 10 c is coated to the area other than the pads 1 a and 1 b and the grooves 18, and a nickel-gold electrolytic plating is applied to the pads 1 a and 1 b.
  • (3) The area other than the groove 18 is covered with an etching mask, and the wiring patter at the groove 18 (part of the lead pattern for electrolytic plating) is removed by etching.
  • (4) The etching mask is removed, and slits 17 are formed between the wiring substrate regions 11 by the router process to complete the substrate frame 10B.
  • (5) A semiconductor chip 2 is bonded with a bond 3 to a central mounting area 11 a of the wiring substrate region 11, and the pads 1 a of the wiring substrate region 11 and the pad 2 a of the semiconductor chip 2 are connected with wires 4.
  • (6) The semiconductor chip 2, the bond 3, and the wires 4 within a package area 11 bare enclosed with a resin 5. Solder balls 6 are joined to the pads 1 b on the second surface of the wiring substrate region 11.
  • (7) The grooves 18 of the wiring substrate regions 11 are punched with a metal mold to provide individual semiconductor devices.
  • As has been described above, the substrate frame 10B has the grooves 18 from which the wiring patterns have been removed so that individual semiconductor devices are separated without any damage to the cut surfaces merely by punching the grooves 18.
  • The substrate frame 10A or 10B may be applied to a multi-layer substrate having three or more wiring layers. The wire bonding between the wiring substrate 1 and the semiconductor chip 2 may be replaced by the flip chip bonding.

Claims (3)

1. A substrate frame comprising:
an insulative board having a pair of ear portions extending along its longitudinal edges;
a plurality of wiring substrate regions arranged on said insulative board between said ear portions at predetermined intervals; and
a plurality of grooves provided around said wiring substrate regions from which wiring patterns are removed.
2. The substrate frame according to claim 1, wherein said grooves are made by boundries of said wiring substrate regions.
3. The substrate frame according to claim 1, wherein said grooves are made suitable for punching to provide individual semiconductor devices.
US11/642,583 2003-09-01 2006-12-21 Substrate frame Abandoned US20070096271A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/642,583 US20070096271A1 (en) 2003-09-01 2006-12-21 Substrate frame

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2003308424A JP2005079365A (en) 2003-09-01 2003-09-01 Substrate frame and method for manufacturing semiconductor device using this
JP2003-308424 2003-09-01
US10/911,477 US7171744B2 (en) 2003-09-01 2004-08-05 Substrate frame
US11/642,583 US20070096271A1 (en) 2003-09-01 2006-12-21 Substrate frame

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US10/911,477 Division US7171744B2 (en) 2003-09-01 2004-08-05 Substrate frame

Publications (1)

Publication Number Publication Date
US20070096271A1 true US20070096271A1 (en) 2007-05-03

Family

ID=34214166

Family Applications (2)

Application Number Title Priority Date Filing Date
US10/911,477 Expired - Fee Related US7171744B2 (en) 2003-09-01 2004-08-05 Substrate frame
US11/642,583 Abandoned US20070096271A1 (en) 2003-09-01 2006-12-21 Substrate frame

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US10/911,477 Expired - Fee Related US7171744B2 (en) 2003-09-01 2004-08-05 Substrate frame

Country Status (2)

Country Link
US (2) US7171744B2 (en)
JP (1) JP2005079365A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090050923A1 (en) * 2007-08-21 2009-02-26 Samsung Electro-Mechanics Co., Ltd. Light emitting diode package

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3895570B2 (en) * 2000-12-28 2007-03-22 株式会社ルネサステクノロジ Semiconductor device
JP4070135B2 (en) * 2004-05-11 2008-04-02 沖電気工業株式会社 Tape carrier, semiconductor device manufacturing method, and semiconductor device
CN101101882A (en) * 2006-07-05 2008-01-09 阎跃军 Substrate resin packaging method
JP2010016291A (en) * 2008-07-07 2010-01-21 Shinko Electric Ind Co Ltd Wiring board and method of manufacturing semiconductor device
JP5298714B2 (en) * 2008-09-05 2013-09-25 富士通セミコンダクター株式会社 Manufacturing method of semiconductor device
CN103359863A (en) * 2012-03-28 2013-10-23 江苏卡特新能源有限公司 Sewage treatment method for biomass diesel production
JP2014107433A (en) * 2012-11-28 2014-06-09 Ibiden Co Ltd Multiple piece forming substrate

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6111306A (en) * 1993-12-06 2000-08-29 Fujitsu Limited Semiconductor device and method of producing the same and semiconductor device unit and method of producing the same
US6303985B1 (en) * 1998-11-12 2001-10-16 Micron Technology, Inc. Semiconductor lead frame and package with stiffened mounting paddle
US20020197826A1 (en) * 2001-06-21 2002-12-26 Advanced Semiconductor Engineering, Inc. Singulation method used in leadless packaging process
US6731013B2 (en) * 2000-06-28 2004-05-04 Sharp Kabushiki Kaisha Wiring substrate, semiconductor device and package stack semiconductor device
US6773961B1 (en) * 2003-08-15 2004-08-10 Advanced Semiconductor Engineering Inc. Singulation method used in leadless packaging process
US6841414B1 (en) * 2002-06-19 2005-01-11 Amkor Technology, Inc. Saw and etch singulation method for a chip package
US6969918B1 (en) * 2001-08-30 2005-11-29 Micron Technology, Inc. System for fabricating semiconductor components using mold cavities having runners configured to minimize venting
US7019388B2 (en) * 2002-12-26 2006-03-28 Renesas Technology Corp. Semiconductor device

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07135281A (en) 1993-11-11 1995-05-23 Hitachi Ltd Method for manufacturing semiconductor device
JPH10209361A (en) 1997-01-17 1998-08-07 Fuji Electric Co Ltd Multiple lead frame
JP3398580B2 (en) 1997-09-13 2003-04-21 株式会社東芝 Semiconductor device manufacturing method and substrate frame
US7030474B1 (en) * 1998-06-24 2006-04-18 Amkor Technology, Inc. Plastic integrated circuit package and method and leadframe for making the package
US7112474B1 (en) * 1998-06-24 2006-09-26 Amkor Technology, Inc. Method of making an integrated circuit package
US7005326B1 (en) * 1998-06-24 2006-02-28 Amkor Technology, Inc. Method of making an integrated circuit package
US6281568B1 (en) * 1998-10-21 2001-08-28 Amkor Technology, Inc. Plastic integrated circuit device package and leadframe having partially undercut leads and die pad
KR100403142B1 (en) * 1999-10-15 2003-10-30 앰코 테크놀로지 코리아 주식회사 semiconductor package
KR100379089B1 (en) * 1999-10-15 2003-04-08 앰코 테크놀로지 코리아 주식회사 leadframe and semiconductor package using it
KR20010037247A (en) * 1999-10-15 2001-05-07 마이클 디. 오브라이언 Semiconductor package
US6198163B1 (en) * 1999-10-18 2001-03-06 Amkor Technology, Inc. Thin leadframe-type semiconductor package having heat sink with recess and exposed surface
US7042068B2 (en) * 2000-04-27 2006-05-09 Amkor Technology, Inc. Leadframe and semiconductor package made using the leadframe
JP4417541B2 (en) * 2000-10-23 2010-02-17 ローム株式会社 Semiconductor device and manufacturing method thereof
US6847099B1 (en) * 2003-02-05 2005-01-25 Amkor Technology Inc. Offset etched corner leads for semiconductor package
US7008825B1 (en) * 2003-05-27 2006-03-07 Amkor Technology, Inc. Leadframe strip having enhanced testability
US7087986B1 (en) * 2004-06-18 2006-08-08 National Semiconductor Corporation Solder pad configuration for use in a micro-array integrated circuit package

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6111306A (en) * 1993-12-06 2000-08-29 Fujitsu Limited Semiconductor device and method of producing the same and semiconductor device unit and method of producing the same
US6303985B1 (en) * 1998-11-12 2001-10-16 Micron Technology, Inc. Semiconductor lead frame and package with stiffened mounting paddle
US6731013B2 (en) * 2000-06-28 2004-05-04 Sharp Kabushiki Kaisha Wiring substrate, semiconductor device and package stack semiconductor device
US20020197826A1 (en) * 2001-06-21 2002-12-26 Advanced Semiconductor Engineering, Inc. Singulation method used in leadless packaging process
US6969918B1 (en) * 2001-08-30 2005-11-29 Micron Technology, Inc. System for fabricating semiconductor components using mold cavities having runners configured to minimize venting
US6841414B1 (en) * 2002-06-19 2005-01-11 Amkor Technology, Inc. Saw and etch singulation method for a chip package
US7019388B2 (en) * 2002-12-26 2006-03-28 Renesas Technology Corp. Semiconductor device
US6773961B1 (en) * 2003-08-15 2004-08-10 Advanced Semiconductor Engineering Inc. Singulation method used in leadless packaging process

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090050923A1 (en) * 2007-08-21 2009-02-26 Samsung Electro-Mechanics Co., Ltd. Light emitting diode package
US8168997B2 (en) * 2007-08-21 2012-05-01 Samsung Led Co., Ltd. Light emitting diode package

Also Published As

Publication number Publication date
US20050048259A1 (en) 2005-03-03
US7171744B2 (en) 2007-02-06
JP2005079365A (en) 2005-03-24

Similar Documents

Publication Publication Date Title
US6586274B2 (en) Semiconductor device, substrate for a semiconductor device, method of manufacture thereof, and electronic instrument
US6534391B1 (en) Semiconductor package having substrate with laser-formed aperture through solder mask layer
US6607942B1 (en) Method of fabricating as grooved heat spreader for stress reduction in an IC package
US6589810B1 (en) BGA package and method of fabrication
US20140252613A1 (en) Semiconductor device
US20050051882A1 (en) Stacked chip package having upper chip provided with trenches and method of manufacturing the same
US20070096271A1 (en) Substrate frame
EP2026641A2 (en) Oblong peripheral solder ball pads on a printed circuit board for mounting a ball grid array package
US7180182B2 (en) Semiconductor component
US7065869B2 (en) Method for plating of printed circuit board strip
JPH0922963A (en) Manufacture of board frame for mounting of semiconductor circuit element
US5406119A (en) Lead frame
KR100346899B1 (en) A Semiconductor device and a method of making the same
JPH10256417A (en) Manufacture of semiconductor package
US6896173B2 (en) Method of fabricating circuit substrate
US5946195A (en) Semiconductor device, method of making the same and mounting the same, circuit board and flexible substrate
US6444494B1 (en) Process of packaging a semiconductor device with reinforced film substrate
JPH11340609A (en) Manufacture of printed wiring board and manufacture of unit wiring board
US6504239B1 (en) Semiconductor device having dummy pattern that relieves stress
JP2798108B2 (en) Hybrid integrated circuit device
JP4159631B2 (en) Manufacturing method of semiconductor package
JPH0547836A (en) Semiconductor device mounting structure
KR100320447B1 (en) Method for Manufacturing Semiconductor Package
KR100247641B1 (en) Stacked ball grid array package and its manufacturing method
JP3508739B2 (en) Interposer board

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION

点击 这是indexloc提供的php浏览器服务，不要输入任何密码和下载