US20070050505A1

US20070050505A1 - Apparatus and method for data transfer control

Info

Publication number: US20070050505A1
Application number: US11/333,327
Authority: US
Inventors: Hideyuki Unno; Masaki Ukai; Naozumi Aoki
Original assignee: Fujitsu Ltd
Current assignee: Fujitsu Ltd
Priority date: 2005-08-31
Filing date: 2006-01-18
Publication date: 2007-03-01
Also published as: EP1760600A1; KR20070025901A; JP2007066109A; DE602006015137D1; CN1924843A; CN100547574C; EP1760600B1; KR100692475B1

Abstract

An apparatus for controlling data transfer performed with a computer connected to a data bus, which performs data transfer in one direction, the apparatus includes a data transfer controlling unit that controls the data transfer with the computer by setting a data bandwidth of an input bus to be greater than a data bandwidth of an output bus, where the input bus transfers data to be input to the computer, and the output bus transfers data output by the computer.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention relates to an apparatus and a method for controlling data transfer with a computer that is connected to a bus which transfers data in one direction.
2. Description of the Related Art
In recent years, due to progress in semiconductor packaging technology, it has become possible to package a higher computing capacity in a smaller computer node. For example, due to high-density of semiconductors, processing capacity per CPU (Central Processing Unit) LSI (Large Scale Integration) is increasing every year. Therefore, larger amount of data is input to and output from even smaller computer node.
In other words, with an increase in an amount of transfer data, a data signal line (such as bus) having even bigger band was needed for even smaller computer nodes, thereby creating a problem of a relative increase in the implementation cost of the data path.
In view of this problem, Japanese Patent Application Laid-open Publication No. H8-63429 discloses a bidirectional bus and an apparatus connected to a bus through which data flows in and out (hereinafter, “bidirectional bus”), in which an amount of data transfer of the bidirectional bus is monitored, and a ratio of a transfer capacity of an amount of data that is input to the apparatus and an amount of data that is output from the apparatus is controlled, thereby eliminating a need to increase a data band width of the bidirectional bus, and suppressing the implementation cost of the data path.
However, because the bidirectional bus according to the conventional technology mentioned above switches a direction of transmission, physical transmission-conditions are strict, and hence, it has become difficult to sufficiently increase the transfer rate. Therefore, in recent buses that require high-rate transmission, the one directional bus needs to be used in most cases.
However, many of one directional buses that are used for data transfer between a CPU and a memory, such as an input bus and an output bus, are separate data transfer paths respectively. Therefore, using a method such as that disclosed in Japanese Patent Application Laid-open Publication No. H8-63429, it was not possible to change a data bandwidth of each bus. Consequently, with an improvement in a processing capacity of the CPU, it was necessary to increase a data band width of the one directional bus, and path cost was enormous.
Moreover, as mentioned in PC WATCH IMPRESS, [online], [searched on Aug. 23, 2005], the Internet<URL: http//pc.watch.impress.co.jp/docs/2005/0211/kaigai155.htm>, setting a data bandwidth of the output bus to be greater than a data bandwidth of the input bus is effective for some kind of computer application. However, usually, the amount of the input data in a general computer node (particularly, a computer node that has a swap type data cache) tends to be greater than the amount of the output data, this method is not effective in a general computer node.
In other words, suppressing the implementation cost of the data path and performing efficient data transfer between the computer nodes becomes an extremely important issue for the computer node connected to the one directional bus.

SUMMARY OF THE INVENTION

It is an object of the present invention to at least solve the problems in the conventional technology.
According to an aspect of the present invention, an apparatus for controlling data transfer performed with a computer connected to a data bus, which performs data transfer in one direction, the apparatus includes a data transfer controlling unit that controls the data transfer with the computer by setting a data bandwidth of an input bus to be greater than a data bandwidth of an output bus, where the input bus transfers data to be input to the computer, and the output bus transfers data output by the computer.
According to another aspect of the present invention, a method for controlling data transfer performed with a computer connected to a data bus, which performs data transfer in one direction, the method including acquiring data to be input to the computer; and transmitting acquired data to the computer by setting a data bandwidth of an input bus to be greater than a data bandwidth of an output bus, where the input bus transfers data to be input to the computer, and the output bus transfers data output by the computer.
According to still another aspect of the present invention, a method for controlling data transfer performed with a computer connected to a bus, which performs data transfer in one direction, the method includes acquiring data output from the computer; and transmitting acquired data to other equipment by setting a data bandwidth of an output bus to be smaller than a data bandwidth of an input bus, wherein the input bus transfers data to be input to the computer, and the output bus transfers data output by the computer.
The above and other objects, features, advantages and technical and industrial significance of this invention will be better understood by reading the following detailed description of presently preferred embodiments of the invention, when considered in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a computer system according to the present embodiment;
FIG. 2 is a functional block diagram of a structure of a buffer section;
FIG. 3 is an example of a data structure of each packet in a long version transfer;
FIG. 4 is an example of a data structure of each packet in a short version transfer; and
FIG. 5 is an example of packet transfer in the long version transfer and the short version transfer.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Exemplary embodiments of the present invention are described below in detail with reference to the accompanying diagrams.
To start with, characteristics of the present invention are described. In the present invention, a data bandwidth of an input bus for transferring data to be input to a computer node and an output bus for transferring data that is output from the computer node is let to be asymmetric. Specifically, the data bandwidth of the input bus is kept greater than the data bandwidth of the output bus.
Here, the reason for letting the data band width of the input/output bus to be asymmetric is that a data band required in the computer node is not equal for an input and an output, and normally, there is a strong tendency that the amount of data input is more than the amount of data output. Furthermore, in a case where the computer node has a swap type data cache, this tendency is obvious.
Thus, focusing attention on data band of the input/output data that is required at the computer node, by setting the data band width of the input bus to be greater than the data band width of the output bus, it is possible to use effectively resources required for a data path, as well as to suppress an implementation cost of the data path.
Next, a structure of a computer system according to the present embodiment is described with reference to FIG. 1. As shown in FIG. 1, the computer system includes computer nodes 10 and 20, input buses 30 a to 30 c, output buses 40 a to 40 c, buffer sections 50 a to 50 f, a cross bar mechanism 60, and a main storage unit 70.
The computer node 10 acquires data that is transferred from the input bus 30 a, performs a predetermined calculation, and transfers output data such as calculation result either to the main storage unit 70 or to the computer node 20 using the output bus 40 a. Similar to the computer node 10, the computer node 20 acquires data that is transferred from the input bus 30 b, performs a predetermined calculation, and transfers output data such as calculation result either to the main storage unit 70 or to the computer node 10 using the output bus 40 b.
The input buses 30 a to 30 c and the output buses 40 a to 40 c are buses for which a direction of transfer of data is one directional. Concretely, the input bus 30 a transfers data from the cross bar mechanism 60 to the computer node 10, the input bus 30 b transfers data from the cross bar mechanism 60 to the computer node 20, and the input bus 30 c transfers data from the main storage unit 70 to the cross bar mechanism 60.
Moreover, the output bus 40 a transfers data from the computer node 10 to the cross bar mechanism 60, the output bus 40 b transfers data from the computer node 20 to the cross bar mechanism 60, and the output bus 40 c transfers data from the cross bar mechanism 60 to the main storage unit 70.
The cross bar mechanism 60 switches the path dynamically while exchanging data between the computer nodes 10 and 20, and the main storage unit 70. The main storage unit 70 stores user data and programs that are used in the computer nodes 10 and 20. Although omitted in FIG. 1, the main storage unit 70 is connected to an auxiliary storage unit etc.
Further, if a data band width of the input bus 30 a is w_ain and a data band width of the output bus 40 a is w_aout, in the present invention, each data bandwidth is set such that w_ain>w_aout. Moreover, if a data bandwidth of the input bus 30 b is w_bin and a data bandwidth of the output bus 40 b is w_bout, in the present invention, each data band width is set such that w_bin>w_bout.
Furthermore, focusing attention on a data transfer path of the computer system shown in FIG. 1, data output from the computer node 20 and the main storage unit 70 is sometimes transferred to the computer node 10. Therefore, in the present invention, the data bandwidth of the input bus 30 a is set such that w_ain>w_bout+w_mout. Here, “w_mout” is a data bandwidth of the input bus 30 c.
Moreover, because data output from the computer node 10 and the main storage unit 70 is sometimes transferred to the computer node 20, in the present invention, the data band width of the input bus 30 c is set as w_bin>w_aout+w_mout.
In the present embodiment, as an example, a ratio of each data bandwidth is set as

- w_ain, w_bin=5
- w_aout, w_bout=3
- w_min (data band width of the input bus 30 c), w_mout=4×n (n>1)
- w_xb (transfer capacity of internal bus in the cross bar mechanism)=4.
  When the ratio of each data band is set in this manner, for example, a ratio of w_ain and w_aout becomes 5 to 3.

The buffer sections 50 a to 50 f store data output from each unit. Further, the buffer sections 50 a to 50 d include a mechanism that absorbs an inconsistency due to asymmetric data bandwidth of the input buses 30 a and 30 b, and the output buses 40 a and 40 b.
A structure of the buffer section 50 a is described next. Buffer sections 50 b to 50 d are similar to the buffer section 50 a, and the description thereof is omitted. FIG. 2 is a functional block diagram of the buffer section. As shown in FIG. 2, the buffer section 50 a includes a switch 51, a data buffer 52, a selector 53, a packet creating unit 54, and a controlling section 55.
The switch 51 assigns data acquired from the cross bar mechanism 60 to various recording areas of the data buffer 52. The data buffer 52 has a plurality of storage areas, and stores data temporarily in the storage areas. Each storage area with a respective entry is indicated below. Moreover, as shown in FIG. 2, each entry can store 32 byte (4 byte×8) data.
The selector 53 selects an entry that is subjected to data acquisition, from a plurality of entries included in the data buffer 52 and acquires data from the entry selected. The selector 53 transfers the data acquired from the entry to the packet creating unit 54.
The packet creating unit 54 creates a packet based on the data received from the selector 53, and sends the packet created to the computer node 10. Further, the packet creating unit 54 changes a transfer rate of a packet based on a data storage condition of the data buffer 52, and transfers the packet whose transfer rate is changed, to the computer node. The controlling section 55 continuously monitors the data storage condition of the data buffer 52, and the packet creating unit 54 acquires information related to the data storage condition of the data buffer 52 from the controlling section 55.
The controlling section 55 controls various units of the buffer section 50 a; that is, the switch 51, the selector 53, and the packet creating unit 54. In other words, the switch 51 assigns data to each entry that is a destination for data recording, based on an instruction from the controlling section 55. The selector 53 acquires data from an entry selected, based on an instruction of the controlling section 55, and transfers the data acquired to the packet creating unit 54.
A packet created by the packet creating unit 54 is described next. In the present embodiment, the packet creating unit 54 creates two types of packets. Specifically, when no data is stored in each entry of the data buffer 52, and the switch 51 records new data in an entry, the packet creating unit 54 converts the newly recorded data as is into packets, and transmits the packets converted to the computer node 10 one after another.
For example, when the switch 51 records data as a 4 byte cycle in the entry, the packet creating unit 54 creates packets that has data of 4 byte per packet and transmits the packets created to the computer node 10. Transmission of a packet group that includes 4 byte data per packet is referred to below as a long version transfer.
FIG. 3 is an example of a data structure of each packet in the long version transfer. In the example shown in FIG. 3, the long version transfer includes nine packets, and header information is stored in a header packet (first packet). The header information includes transfer rate identification information that enables a receiving side (for example, a computer node) to identify uniquely that each packet information shown in FIG. 3 is a long version transfer. The packet creating unit 54 creates the transfer rate identification information at the time of creating the packet, and stores in the header packet.
Moreover, at the beginning of each of the first to the ninth packets, identification information for identifying information stored in the packet is added. In other words, according to the identification information, the receiving side can judge whether data stored in the packet is header information or user data.
Another type of packet is described next. When data is stored in each entry of the data buffer 52, and the switch 51 records new data in an entry, the packet creating unit 54 increases a transfer rate of the packet.
For example, when the switch 51 records data as a 4 byte cycle in the entry (data is supposed to be stored in this entry), the packet creating unit 54 creates packets with 5 byte data per packet, and transmits the packets created to the computer node 10. Transmission of a packet group that includes 5 byte data per packet is referred to below as a short version transfer.
FIG. 4 is an example of a data structure of each packet in the short version transfer. In the example shown in FIG. 4, the short version transfer includes seven packets, and header information and user data is stored in a header packet (first packet). The header information includes transfer rate identification information that enables a receiving side (for example., computer node) to identify uniquely that each packet information shown in FIG. 4 is a short version transfer. The packet creating unit 54 creates the transfer rate identification information at the time of creating the packet, and stores in the header packet.
Moreover, at the beginning of each of the first to the seventh packets, identification information for identifying the information stored in the packet is added. In other words, according to the identification information, the receiving side can judge whether data stored in the packet is header information or user data (sometimes data includes header information and user data, as in packets shown in FIG. 4). Further, because data of nine packets in the long version transfer is transferred in seven packets in the short version transfer (transferred by increasing the transfer rate), user data (WORD 0 to WORD 7) is stored spreading over various packets.
For example, in FIG. 3, user data WORD 0 is stored in the second packet, and in FIG. 4, user data WORD 0 is spread over the first packet and the second packet.
FIG. 5 is an example of packet transfer in the long version transfer and the short version transfer. As shown in FIG. 5, in a first half of the packet transfer, data is not stored in the data buffer 52, and hence, the buffer section 50 a performs the packet transfer by the long version transfer. But in a second half, data is already stored in the data buffer, and hence, the buffer section 50 a performs the packet transfer by the short version transfer by increasing the transfer rate.
Further, although a detail description is omitted here, the buffer sections 50 b and 50 d use a mechanism similar to the mechanism of the buffer section 50 a, and transfer the data output from the computer nodes 10 and 20 to the cross bar mechanism 60.
In other words, the buffer sections 50 b and 50 d record into the data buffer the data output from the computer node 10 or 20, and based on the data storage condition of the data buffer, the packet creating unit 54 changes the transfer rate of the packet transferred to the cross bar mechanism 60.
As mentioned above, the computer system according to the present embodiment controls the data transfer in each unit by setting the data bandwidth of the input bus 30 a to be greater than the data bandwidth of the output bus 40 a, and the data bandwidth of the input bus 30 b to be greater than the data bandwidth of the output bus 40 b. Moreover, by providing the buffer section 50 a and 50 d to absorb the inconsistency caused due to asymmetrically setting the data bandwidth of each bus, effective use of the data path that has limited resources, and efficient data transfer with the computer node is possible.
According to an aspect of the present invention, it is possible to perform cost-effective and efficient data transmission to a computer connected to a one-directional data bus.
Moreover, it is possible to perform normal data transmission to the computer.
Furthermore, it is possible to deal appropriately with an inconsistency in the data transfer due to asymmetric data bandwidth of the input bus and the output bus.
Moreover, even when the input data is not accumulated and data to be input to the computer is acquired newly, it is possible to perform efficient data transmission to the computer.
Furthermore, even when the input data is accumulated and data to be input to the computer is acquired newly, it is possible to perform efficient data transmission to the computer.
According to another aspect of the present invention, it is possible to perform the data transmission normally from the computer to other equipment.
Moreover, in case of data transfer to the other equipment, it is possible to deal appropriately with an inconsistency in the data transfer due to asymmetric data bandwidth of the input bus and the output bus.
Furthermore, even when the input data is not accumulated and data to be input to the computer is acquired newly, it is possible to perform efficient data transmission from the computer to the other equipment.
Moreover, even when the input data is accumulated and data to be input to the computer is acquired newly, it is possible to perform efficient data transmission from the computer to the other equipment.
Although the invention has been described with respect to a specific embodiment for a complete and clear disclosure, the appended claims are not to be thus limited but are to be construed as embodying all modifications and alternative constructions that may occur to one skilled in the art that fairly fall within the basic teaching herein set forth.

Claims

1. An apparatus for controlling data transfer performed with a computer connected to a data bus, which performs data transfer in one direction, the apparatus comprising:

a data transfer controlling unit that controls the data transfer with the computer by setting a data bandwidth of an input bus to be greater than a data bandwidth of an output bus, wherein the input bus transfers data to be input to the computer.

2. The apparatus-according to claim 1, further comprising:

an input data recording unit that records data to be input to the computer, and compensates for a difference in a transfer rate of the data to be input to the computer, and wherein

the data transfer controlling unit transmits said data to the computer.

3. The apparatus according to claim 2, wherein

the data transfer controlling unit changes the transfer rate based on a storage condition of the recorded data.

4. The apparatus according to claim 3, wherein

when the input data is not accumulated in the input data recording unit, and new data to be input to the computer is recorded, the data transfer controlling unit transmits the new data to the computer without changing the transfer rate.

5. The apparatus according to claim 3, wherein

when the input data is accumulated in the input data recording unit, and new data to be input to the computer is recorded, the data transfer controlling unit transmits the new data to the computer by increasing the transfer rate.

6. The apparatus according to claim 3, wherein

the data transfer controlling unit adds to the data to be transmitted, identification information that identifies the transfer rate of the data.

7. The apparatus according to claim 1, further comprising:

an output data recording unit that temporarily records data output by the computer, and compensates for a difference in a transfer rate of the data transferred from the computer to an other equipment, and wherein

the data transfer controlling unit transmits recorded data to the other equipment.

8. The apparatus according to claim 7, wherein

9. The apparatus according to claim 8, wherein

when the output data is not accumulated in the output data recording unit, and new data to be output by the computer is recorded, the data transfer controlling unit transmits the new data to the other equipment without changing the transfer rate.

10. The apparatus according to claim 8, wherein

when the output data is accumulated in the output data recording unit, and new data to be output by the computer is recorded, the data transfer controlling unit transmits the new data to the other equipment by increasing the transfer rate.

11. The apparatus according to claim 7, wherein

12. A method for controlling data transfer performed with a computer connected to a data bus, which performs data transfer in one direction, the method comprising:

acquiring data to be input to the computer; and

transmitting acquired data to the computer by setting a data bandwidth of an input bus to be greater than a data bandwidth of an output bus.

13. The method according to claim 12, further comprising:

recording temporarily in an input data recording unit, data to be input to the computer; and

compensating for a difference in a transfer rate of the data to be input to the computer, and wherein

the act of transmitting includes transmitting recorded data to the computer.

14. The method according to claim 13, wherein

the act of transmitting includes changing the transfer rate based on a storage condition of the recorded data.

15. The method according to claim 14, wherein

when the input data is not accumulated in the input data recording unit, and new data to be input to the computer is recorded, the act of transmitting includes transmitting the new data to the computer without changing the transfer rate.

16. The method according to claim 14, wherein

when the input data is accumulated in the input data recording unit, and new data to be input to the computer is recorded, the act of transmitting includes transmitting the new data to the computer by increasing the transfer rate.

17. The apparatus according to claim 14, wherein

the act of transmitting includes adding to the data to be transmitted, identification information that identifies the transfer rate of the data.

18. A method for controlling data transfer performed with a computer connected to a bus, which performs data transfer in one direction, the method comprising:

acquiring data output from the computer; and

transmitting acquired data to other equipment by setting a data bandwidth of an output bus to be smaller than a data bandwidth of an input bus.

19. The method according to claim 18, further comprising:

recording temporarily in an output data recording unit, data output by the computer; and

compensating for a difference in a transfer rate of the data transferred from the computer to an other equipment, and wherein

the act of transmitting includes transmitting recorded data to the other equipment.

20. The method according to claim 19, wherein

21. The method according to claim 20, wherein

when the output data is not accumulated in the output data recording unit, and new data to be output by the computer is recorded, the act of transmitting includes transmitting the new data to the other equipment without changing the transfer rate.

22. The method according to claim 20, wherein

when the output data is accumulated in the output data recording unit, and new data to be output by the computer is recorded, the act of transmitting includes transmitting the new data to the other equipment by increasing the transfer rate.

23. The apparatus according to claim 20, wherein the act of transmitting includes adding to the data to be transmitted, identification information that identifies the transfer rate of the data.