US20060211175A1 - Heatsink apparatus and thermally-conductive intermediate material for dissipating heat in semiconductor packages - Google Patents
Heatsink apparatus and thermally-conductive intermediate material for dissipating heat in semiconductor packages Download PDFInfo
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- US20060211175A1 US20060211175A1 US11/439,609 US43960906A US2006211175A1 US 20060211175 A1 US20060211175 A1 US 20060211175A1 US 43960906 A US43960906 A US 43960906A US 2006211175 A1 US2006211175 A1 US 2006211175A1
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
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- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
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- H01L24/42—Wire connectors; Manufacturing methods related thereto
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- H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
- H10F39/80—Constructional details of image sensors
- H10F39/804—Containers or encapsulations
Definitions
- Integrated circuits are fabricated on the surface of a semiconductor wafer in layers and later singulated into individual semiconductor devices, or “dies.” Since the material of a semiconductor wafer—commonly silicon—tends to be relatively fragile and brittle, dies are often packages in a protecting housing, or “package,” before the dies are interconnected with a circuit board. Packages may fall into any of a variety of package categories. Two such categories are exposed-die packages and non-leaded wirebond packages.
- FIG. 1 shows a cross-sectional side view of an exposed-die package 100 , such as a PowerPad® package or a plastic package.
- the package 100 comprises a die 102 coupled to a leadframe die pad 104 of a leadframe 106 by way of a die attach material 103 (e.g., epoxy).
- the die 102 is electrically coupled to the leadframe 106 using bond wires 108 .
- the die 102 , the bond wires 108 , the die attach material 103 and portions of the leadframe 106 are encapsulated in a mold compound 110 .
- the leadframe 106 comprises a plurality of leads 112 that protrude from the mold compound 110 . At least some of the leads 112 may be electrically coupled to a circuit board 114 .
- the die 102 In this way, electrical signals are transferred between the die 102 and the board 114 . Further, at least a portion of the die pad 104 is exposed from a surface 118 of the mold compound 110 and is in contact with the board 314 . As such, heat is transferred away from the die 102 and toward the board 114 by way of the die pad 104 . Thus, the board 114 acts as a heatsink for the package 100 .
- FIG. 2 shows a cross-sectional side-view of an exemplary non-leaded wirebond package 200 (e.g., quad-flat no-lead package, small-outline no-lead package).
- the term “non-leaded” connotes a lack of leads protruding from the package 200 , as found in the package 100 of FIG. 1 .
- the package 200 comprises a die 202 coupled to a leadframe die pad 204 of a leadframe 201 by way of a die attach material 203 (e.g., epoxy).
- the die 202 is electrically coupled to the leadframe 201 using bond wires 208 .
- the die 202 , the die attach material 203 , the bond wires 208 and portions of the leadframe 201 are encapsulated in a mold compound 210 .
- the non-leaded package 200 does not comprise any leads.
- the die 202 trades electrical signals with a circuit board 214 by way of peripheral portions 216 (“peripherals”) of the leadframe 201 .
- the peripherals 216 do not protrude from the mold compound 210 as do the leads 112 from the compound 110 ; instead, the peripherals 216 are exposed from a surface 218 of the mold compound 210 .
- the die pad 204 also may be exposed from the surface 218 .
- the die pad 204 is exposed from the surface 218 and is in contact with the board 214 , heat is transferred away from the die 202 and to the board 214 by way of the die pad 204 .
- the board 214 acts as a heatsink for the package 200 .
- circuit boards coupled to such packages may have a design flaw or some other limitation that prevents adequate heat dissipation away from the package.
- a device containing the circuit board may overheat and either be destroyed or thrust into a state of thermal shutdown.
- Some packages may comprise heatsinks coupled to the package mold compound (e.g., mold compounds 210 , 310 ) to help dissipate heat away from the package.
- package mold compounds usually do not have adequate levels of thermal conductivity to compensate for the overheating effect described above.
- One exemplary embodiment may be a semiconductor package comprising a die adjacent a lead frame die pad, said lead frame die pad adapted to dissipate heat from the die.
- the package further comprises a thermally-conductive material abutting the die and a heatsink abutting the thermally-conductive material, said heatsink facing a direction opposite from the lead frame die pad.
- FIG. 1 shows an exposed-die package coupled to a circuit board
- FIG. 2 shows a non-leaded wirebond package coupled to a circuit board
- FIG. 3 shows an exposed-die package comprising a heatsink apparatus and intermediate material, in accordance with embodiments of the invention
- FIG. 4 shows a non-leaded wirebond package comprising a heatsink apparatus and intermediate material, in accordance with embodiments of the invention
- FIG. 5 shows a flow diagram of a process that may be used to implement the configurations of FIGS. 3 and 4 , in accordance with embodiments of the invention
- FIGS. 6 a and 6 b show heatsink apparatus matrices that may be coupled to dies still on a semiconductor wafer, in accordance with embodiments of the invention.
- FIG. 6 c shows a matrix from FIG. 6 a and/or FIG. 6 b coupling to dies still on a semiconductor wafer, in accordance with embodiments of the invention.
- a thermally conductive heatsink apparatus that may be incorporated into any of a variety of semiconductor packages to substantially enhance package thermal dissipation.
- a thermally conductive heatsink apparatus is coupled to an interposer or some other intermediate material abutting a die in a package.
- the intermediate material is used to minimize mechanical stress caused by the die as a result of multiple thermal expansion rates in the die. Because the intermediate material also is thermally conductive, heat is transferred from the die to the heatsink apparatus by way of the intermediate material. In this way, heat is effectively dissipated from the package.
- FIG. 3 and 4 show the heatsink apparatus incorporated into an exposed-die package and a non-leaded wirebond package, respectively, although the heatsink apparatus may be used in any type of package (e.g., wirebond, flip-chip) to enhance heat dissipation.
- package e.g., wirebond, flip-chip
- FIG. 3 shows an exposed die package 300 comprising a chip (i.e., die) 302 electrically coupled to a leadframe 304 by way of bond wires 306 .
- the die 302 is physically coupled to a leadframe die pad 298 of the leadframe 304 by way of a die attach material 308 (e.g., solder, epoxy).
- the die 302 may be electrically coupled to a circuit board 311 by way of bond wires 301 and leads 296 .
- An intermediate material 310 abuts the die 302 and a heatsink apparatus 312 abuts the intermediate material 310 .
- the intermediate material 310 may be any of a variety of thermally conductive materials, such as an interposer (e.g., adhesive heat conductive tape), a liquid die attach, film die attach, solder alloy, or mold die attach.
- the heatsink apparatus 312 may be metal (e.g., copper), thermally-conductive plastic or any other suitably thermally conductive material.
- the die 302 , the die attach material 308 , the intermediate material 310 , and portions of the lead frame 304 and the heatsink apparatus 312 may be encapsulated in and protected by a mold compound 303 .
- the heatsink apparatus 312 may prevent a device containing the package 300 and/or the circuit board 311 from overheating, being thrust into thermal shutdown, or otherwise becoming damaged.
- FIG. 4 shows yet another exemplary embodiment of the heatsink apparatus described above.
- a non-leaded wirebond package 400 e.g., a quad-flat no-lead or small-outline no-lead package
- the die 402 is physically coupled to a leadframe die pad 403 of the leadframe 404 by way of a die attach material 408 (e.g., epoxy).
- An intermediate material 410 abuts the die 402 and a heatsink apparatus 412 abuts the intermediate material 410 .
- the intermediate material 410 may be any of a variety of thermally conductive materials, such as an interposer (e.g., adhesive heat conductive tape), a liquid die attach, a film die attach, solder alloy, or a mold die attach.
- the heatsink apparatus 412 may be a metal (e.g., copper), a thermally-conductive plastic or any other such material.
- the die 402 , the die attach material 408 , the intermediate material 410 , and portions of the lead frame 404 and the heatsink apparatus 412 may be encapsulated in and protected by a mold compound 420 .
- the heatsink apparatus 412 may prevent a device containing the package 400 and the circuit board 411 from overheating, being thrust into thermal shutdown, or otherwise becoming damaged.
- a heatsink apparatus may be incorporated into a package using any of a variety of techniques, depending on the intermediate materials used to couple the heatsink apparatus to the package die.
- FIG. 5 shows one exemplary process that may be used to implement a heatsink apparatus and intermediate material into any type of package. The process may be begun by depositing thermally-conductive material (“intermediate material”) onto a suitable surface of a heatsink apparatus and/or a package die (block 500 ).
- the intermediate material may be any suitable, thermally-conductive material, such as liquid die attach, film die attach, an interposer (e.g., adhesive heat conductive tape), or a mold compound, although the scope of disclosure is not limited to these materials.
- the process then may be continued by coupling the heatsink apparatus to the package die, with the intermediate material sandwiched therebetween (block 502 ). In this way, heat may be dissipated from the chip to the heatsink by way of the intermediate material.
- the process comprises the optional step of holding together the heatsink apparatus and the die using a vacuum, clamps, or other suitable tool until the mold compound is cured (block 504 ).
- the process may further be continued by depositing a mold compound into the package (block 506 ).
- the process may be completed by curing the mold compound (block 508 ). This process may be performed in any order, and one or more steps may be removed.
- the process of FIG. 5 may be used to couple a heatsink apparatus to a die that has already been singulated from a semiconductor wafer or leadframe strip.
- the process of FIG. 5 also may be used in situations where the dies have not yet been singulated from a semiconductor wafer or leadframe/substrate strip.
- multiple heatsink apparatuses may simultaneously be coupled to multiple package dies (i.e., the process of FIG. 5 may be performed en masse on several dies of a wafer or leadframe/substrate strip).
- These multiple heatsink apparatuses may be coupled to multiple dies on a wafer or leadframe/substrate strip by arranging the apparatuses in a matrix pattern to match the pattern of the dies on the wafer.
- a matrix pattern to match the pattern of the dies on the wafer.
- FIGS. 6 a and 6 b each show a top-down view of a matrix 600 , 602 comprising multiple heatsink apparatuses 604 , 606 , respectively.
- Each matrix 600 , 602 comprises multiple apertures 601 fixed between at least some of the heatsink apparatuses 604 , 606 .
- the apertures 601 may be of any shape, such as a substantially rectangular shape or a cross shape.
- a matrix may comprise singulation lines to aid in die separation, such as singulation lines 610 on the matrix 600 .
- a matrix 600 (or matrix 602 ) may be coupled to a wafer 608 comprising multiple dies 615 .
- the apparatuses 604 of the matrix 600 may be coupled to the dies 615 of the wafer 608 using the process of FIG. 5 .
- the apertures 601 may be used to deposit a mold compound onto the dies 615 . After the mold compound has been cured, the wafer 608 may be singulated such that at least some of the dies 615 are separated from each other.
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Abstract
A semiconductor package comprising a die adjacent a lead frame die pad, said lead frame die pad adapted to dissipate heat from the die. The package further comprises a thermally-conductive material abutting the die and a heatsink abutting the thermally-conductive material, said heatsink facing a direction opposite from the lead frame die pad.
Description
- Integrated circuits are fabricated on the surface of a semiconductor wafer in layers and later singulated into individual semiconductor devices, or “dies.” Since the material of a semiconductor wafer—commonly silicon—tends to be relatively fragile and brittle, dies are often packages in a protecting housing, or “package,” before the dies are interconnected with a circuit board. Packages may fall into any of a variety of package categories. Two such categories are exposed-die packages and non-leaded wirebond packages.
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FIG. 1 shows a cross-sectional side view of an exposed-die package 100, such as a PowerPad® package or a plastic package. Thepackage 100 comprises a die 102 coupled to aleadframe die pad 104 of aleadframe 106 by way of a die attach material 103 (e.g., epoxy). The die 102 is electrically coupled to theleadframe 106 usingbond wires 108. The die 102, thebond wires 108, the dieattach material 103 and portions of theleadframe 106 are encapsulated in amold compound 110. Theleadframe 106 comprises a plurality ofleads 112 that protrude from themold compound 110. At least some of theleads 112 may be electrically coupled to acircuit board 114. In this way, electrical signals are transferred between thedie 102 and theboard 114. Further, at least a portion of thedie pad 104 is exposed from asurface 118 of themold compound 110 and is in contact with the board 314. As such, heat is transferred away from the die 102 and toward theboard 114 by way of thedie pad 104. Thus, theboard 114 acts as a heatsink for thepackage 100. -
FIG. 2 shows a cross-sectional side-view of an exemplary non-leaded wirebond package 200 (e.g., quad-flat no-lead package, small-outline no-lead package). The term “non-leaded” connotes a lack of leads protruding from thepackage 200, as found in thepackage 100 ofFIG. 1 . Thepackage 200 comprises a die 202 coupled to a leadframe diepad 204 of aleadframe 201 by way of a die attach material 203 (e.g., epoxy). The die 202 is electrically coupled to theleadframe 201 usingbond wires 208. The die 202, the dieattach material 203, thebond wires 208 and portions of theleadframe 201 are encapsulated in amold compound 210. As previously mentioned, unlike theleaded package 100, the non-leadedpackage 200 does not comprise any leads. Instead, the die 202 trades electrical signals with acircuit board 214 by way of peripheral portions 216 (“peripherals”) of theleadframe 201. Theperipherals 216 do not protrude from themold compound 210 as do theleads 112 from thecompound 110; instead, theperipherals 216 are exposed from asurface 218 of themold compound 210. The diepad 204 also may be exposed from thesurface 218. As such, because thedie pad 204 is exposed from thesurface 218 and is in contact with theboard 214, heat is transferred away from thedie 202 and to theboard 214 by way of thedie pad 204. Thus, theboard 214 acts as a heatsink for thepackage 200. - In some cases, circuit boards coupled to such packages (e.g.,
boards 114 and 214) may have a design flaw or some other limitation that prevents adequate heat dissipation away from the package. In such cases, a device containing the circuit board may overheat and either be destroyed or thrust into a state of thermal shutdown. Some packages may comprise heatsinks coupled to the package mold compound (e.g.,mold compounds 210, 310) to help dissipate heat away from the package. However, package mold compounds usually do not have adequate levels of thermal conductivity to compensate for the overheating effect described above. - The problems noted above are solved in large part by a heatsink apparatus and thermally-conductive intermediate material for dissipating heat in semiconductor packages. One exemplary embodiment may be a semiconductor package comprising a die adjacent a lead frame die pad, said lead frame die pad adapted to dissipate heat from the die. The package further comprises a thermally-conductive material abutting the die and a heatsink abutting the thermally-conductive material, said heatsink facing a direction opposite from the lead frame die pad.
- For a detailed description of exemplary embodiments of the invention, reference will now be made to the accompanying drawings in which:
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FIG. 1 shows an exposed-die package coupled to a circuit board; -
FIG. 2 shows a non-leaded wirebond package coupled to a circuit board; -
FIG. 3 shows an exposed-die package comprising a heatsink apparatus and intermediate material, in accordance with embodiments of the invention; -
FIG. 4 shows a non-leaded wirebond package comprising a heatsink apparatus and intermediate material, in accordance with embodiments of the invention; -
FIG. 5 shows a flow diagram of a process that may be used to implement the configurations ofFIGS. 3 and 4 , in accordance with embodiments of the invention; -
FIGS. 6 a and 6 b show heatsink apparatus matrices that may be coupled to dies still on a semiconductor wafer, in accordance with embodiments of the invention; and -
FIG. 6 c shows a matrix fromFIG. 6 a and/orFIG. 6 b coupling to dies still on a semiconductor wafer, in accordance with embodiments of the invention. - Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, companies may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to. . . .” Also, the term “couple” or “couples” is intended to mean either an indirect or direct electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.
- The following discussion is directed to various embodiments of the invention. Although one or more of these embodiments may be preferred, the embodiments disclosed should not be interpreted, or otherwise used, as limiting the scope of the disclosure, including the claims. In addition, one skilled in the art will understand that the following description has broad application, and the discussion of any embodiment is meant only to be exemplary of that embodiment, and not intended to intimate that the scope of the disclosure, including the claims, is limited to that embodiment.
- Disclosed herein is a heatsink apparatus that may be incorporated into any of a variety of semiconductor packages to substantially enhance package thermal dissipation. Specifically, a thermally conductive heatsink apparatus is coupled to an interposer or some other intermediate material abutting a die in a package. The intermediate material is used to minimize mechanical stress caused by the die as a result of multiple thermal expansion rates in the die. Because the intermediate material also is thermally conductive, heat is transferred from the die to the heatsink apparatus by way of the intermediate material. In this way, heat is effectively dissipated from the package.
FIGS. 3 and 4 show the heatsink apparatus incorporated into an exposed-die package and a non-leaded wirebond package, respectively, although the heatsink apparatus may be used in any type of package (e.g., wirebond, flip-chip) to enhance heat dissipation. - In particular,
FIG. 3 shows an exposeddie package 300 comprising a chip (i.e., die) 302 electrically coupled to aleadframe 304 by way of bond wires 306. The die 302 is physically coupled to a leadframe diepad 298 of theleadframe 304 by way of a die attach material 308 (e.g., solder, epoxy). The die 302 may be electrically coupled to acircuit board 311 by way ofbond wires 301 and leads 296. Anintermediate material 310 abuts the die 302 and aheatsink apparatus 312 abuts theintermediate material 310. Theintermediate material 310 may be any of a variety of thermally conductive materials, such as an interposer (e.g., adhesive heat conductive tape), a liquid die attach, film die attach, solder alloy, or mold die attach. Theheatsink apparatus 312 may be metal (e.g., copper), thermally-conductive plastic or any other suitably thermally conductive material. Thedie 302, the die attachmaterial 308, theintermediate material 310, and portions of thelead frame 304 and theheatsink apparatus 312 may be encapsulated in and protected by amold compound 303. Because there exists little thermal resistance between the die 302 and the heatsink apparatus 312 (i.e., theintermediate material 310 is thermally conductive), theheatsink apparatus 312 may prevent a device containing thepackage 300 and/or thecircuit board 311 from overheating, being thrust into thermal shutdown, or otherwise becoming damaged. -
FIG. 4 shows yet another exemplary embodiment of the heatsink apparatus described above. Specifically,FIG. 4 shows a non-leaded wirebond package 400 (e.g., a quad-flat no-lead or small-outline no-lead package) comprising adie 402 electrically coupled to acircuit board 411 by way of aleadframe 404 andbond wires 406. Thedie 402 is physically coupled to aleadframe die pad 403 of theleadframe 404 by way of a die attach material 408 (e.g., epoxy). Anintermediate material 410 abuts thedie 402 and aheatsink apparatus 412 abuts theintermediate material 410. Theintermediate material 410 may be any of a variety of thermally conductive materials, such as an interposer (e.g., adhesive heat conductive tape), a liquid die attach, a film die attach, solder alloy, or a mold die attach. Theheatsink apparatus 412 may be a metal (e.g., copper), a thermally-conductive plastic or any other such material. Thedie 402, the die attachmaterial 408, theintermediate material 410, and portions of thelead frame 404 and theheatsink apparatus 412 may be encapsulated in and protected by amold compound 420. Because there exists little thermal resistance between the die 402 and the heatsink apparatus 412 (i.e., theintermediate material 410 is thermally conductive), theheatsink apparatus 412 may prevent a device containing thepackage 400 and thecircuit board 411 from overheating, being thrust into thermal shutdown, or otherwise becoming damaged. - A heatsink apparatus may be incorporated into a package using any of a variety of techniques, depending on the intermediate materials used to couple the heatsink apparatus to the package die.
FIG. 5 shows one exemplary process that may be used to implement a heatsink apparatus and intermediate material into any type of package. The process may be begun by depositing thermally-conductive material (“intermediate material”) onto a suitable surface of a heatsink apparatus and/or a package die (block 500). As mentioned above, the intermediate material may be any suitable, thermally-conductive material, such as liquid die attach, film die attach, an interposer (e.g., adhesive heat conductive tape), or a mold compound, although the scope of disclosure is not limited to these materials. The process then may be continued by coupling the heatsink apparatus to the package die, with the intermediate material sandwiched therebetween (block 502). In this way, heat may be dissipated from the chip to the heatsink by way of the intermediate material. In cases where the intermediate material is a mold compound, the process comprises the optional step of holding together the heatsink apparatus and the die using a vacuum, clamps, or other suitable tool until the mold compound is cured (block 504). The process may further be continued by depositing a mold compound into the package (block 506). The process may be completed by curing the mold compound (block 508). This process may be performed in any order, and one or more steps may be removed. - In many cases, the process of
FIG. 5 may be used to couple a heatsink apparatus to a die that has already been singulated from a semiconductor wafer or leadframe strip. However, the process ofFIG. 5 also may be used in situations where the dies have not yet been singulated from a semiconductor wafer or leadframe/substrate strip. In these cases, multiple heatsink apparatuses may simultaneously be coupled to multiple package dies (i.e., the process ofFIG. 5 may be performed en masse on several dies of a wafer or leadframe/substrate strip). These multiple heatsink apparatuses may be coupled to multiple dies on a wafer or leadframe/substrate strip by arranging the apparatuses in a matrix pattern to match the pattern of the dies on the wafer. Although the scope of disclosure is not limited to any particular pattern, two exemplary patterns are shown inFIGS. 6 a and 6 b. -
FIGS. 6 a and 6 b each show a top-down view of amatrix 600, 602 comprisingmultiple heatsink apparatuses 604, 606, respectively. Eachmatrix 600, 602 comprisesmultiple apertures 601 fixed between at least some of theheatsink apparatuses 604, 606. Theapertures 601 may be of any shape, such as a substantially rectangular shape or a cross shape. In at least some embodiments, a matrix may comprise singulation lines to aid in die separation, such assingulation lines 610 on thematrix 600. As shown inFIG. 6 c, a matrix 600 (or matrix 602) may be coupled to awafer 608 comprising multiple dies 615. Theapparatuses 604 of thematrix 600 may be coupled to the dies 615 of thewafer 608 using the process ofFIG. 5 . Theapertures 601 may be used to deposit a mold compound onto the dies 615. After the mold compound has been cured, thewafer 608 may be singulated such that at least some of the dies 615 are separated from each other. - The above discussion is meant to be illustrative of the principles and various embodiments of the present invention. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. For example, while the above embodiments illustrates the heatsink apparatus incorporated into an exposed-die package and a non-leaded wirebond package, the heatsink apparatus also may be used in any other type of package to enhance heat dissipation. It is intended that the following claims be interpreted to embrace all such variations and modifications.
Claims (16)
1. A semiconductor package, comprising:
a die adjacent a lead frame die pad, said lead frame die pad adapted to dissipate heat from the die;
a thermally-conductive material abutting the die; and
a heatsink abutting the thermally-conductive material on an opposite side of said die from said lead frame die pad.
2. The semiconductor package of claim 1 , wherein the thermally-conductive material is a material selected from a group consisting of liquid attach, film attach, solder alloy, mold compound and interposer material.
3. The semiconductor package of claim 2 , wherein the interposer material is an adhesive, thermally-conductive tape.
4. The semiconductor package of claim 1 , wherein the heatsink is made of metal.
5. The semiconductor package of claim 1 , wherein the heatsink is made of thermally-conductive plastic.
6. The semiconductor package of claim 1 , wherein the lead frame die pad is adapted to dissipate heat from the die by transferring the heat to an adjacent circuit board.
7. The semiconductor package of claim 1 , wherein at least a portion of the package is encapsulated in a mold compound.
8. The semiconductor package of claim 1 , wherein the intermediate material reduces mechanical stress caused by multiple thermal expansion rates of the die.
9. The semiconductor package of claim 1 , further comprising a lead electrically coupled to the die, said lead adapted to transfer electrical signals between the die and a circuit board.
10. The semiconductor package of claim 1 , wherein the package is non-leaded.
11. The semiconductor package of claim 10 , wherein the package is selected from a group consisting of quad-flat no-lead packages and small-outline no-lead packages.
12-17. (canceled)
18. An apparatus, comprising:
a plurality of heatsinks, at least one of said heatsinks adapted to couple to a thermally-conductive material abutting a die on a semiconductor wafer; and
an aperture between at least some of the heatsinks, said aperture adapted to facilitate the deposition of a mold compound.
19. The apparatus of claim 18 , further comprising singulation lines.
20. The apparatus of claim 18 , wherein the aperture has a shape selected from a group consisting of a substantially rectangular shape and a cross shape.
21. The apparatus of claim 18 , wherein the thermally-conductive material reduces mechanical stress caused by varying thermal expansion rates of the die.
Priority Applications (1)
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US11/439,609 US20060211175A1 (en) | 2004-08-23 | 2006-05-24 | Heatsink apparatus and thermally-conductive intermediate material for dissipating heat in semiconductor packages |
Applications Claiming Priority (2)
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US10/923,920 US7074653B2 (en) | 2004-08-23 | 2004-08-23 | Heatsink apparatus and thermally-conductive intermediate material for dissipating heat in semiconductor packages |
US11/439,609 US20060211175A1 (en) | 2004-08-23 | 2006-05-24 | Heatsink apparatus and thermally-conductive intermediate material for dissipating heat in semiconductor packages |
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US10/923,920 Division US7074653B2 (en) | 2004-08-23 | 2004-08-23 | Heatsink apparatus and thermally-conductive intermediate material for dissipating heat in semiconductor packages |
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US20060211175A1 true US20060211175A1 (en) | 2006-09-21 |
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US10/923,920 Expired - Lifetime US7074653B2 (en) | 2004-08-23 | 2004-08-23 | Heatsink apparatus and thermally-conductive intermediate material for dissipating heat in semiconductor packages |
US11/239,020 Abandoned US20060038202A1 (en) | 2004-08-23 | 2005-09-29 | Heatsink apparatus and thermally-conductive intermediate material for dissipating heat in semiconductor packages |
US11/439,609 Abandoned US20060211175A1 (en) | 2004-08-23 | 2006-05-24 | Heatsink apparatus and thermally-conductive intermediate material for dissipating heat in semiconductor packages |
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US10/923,920 Expired - Lifetime US7074653B2 (en) | 2004-08-23 | 2004-08-23 | Heatsink apparatus and thermally-conductive intermediate material for dissipating heat in semiconductor packages |
US11/239,020 Abandoned US20060038202A1 (en) | 2004-08-23 | 2005-09-29 | Heatsink apparatus and thermally-conductive intermediate material for dissipating heat in semiconductor packages |
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Families Citing this family (10)
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US7554179B2 (en) * | 2005-02-08 | 2009-06-30 | Stats Chippac Ltd. | Multi-leadframe semiconductor package and method of manufacture |
SG131789A1 (en) * | 2005-10-14 | 2007-05-28 | St Microelectronics Asia | Semiconductor package with position member and method of manufacturing the same |
US20070290303A1 (en) * | 2006-06-07 | 2007-12-20 | Texas Instruments Deutschland Gmbh | Dual leadframe semiconductor device package |
US20080054496A1 (en) * | 2006-08-30 | 2008-03-06 | Neill Thornton | High temperature operating package and circuit design |
US8067256B2 (en) * | 2007-09-28 | 2011-11-29 | Intel Corporation | Method of making microelectronic package using integrated heat spreader stiffener panel and microelectronic package formed according to the method |
JP5155890B2 (en) | 2008-06-12 | 2013-03-06 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
US8994176B2 (en) | 2012-12-13 | 2015-03-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for package with interposers |
US9852961B2 (en) * | 2013-08-28 | 2017-12-26 | Infineon Technologies Ag | Packaged semiconductor device having an encapsulated semiconductor chip |
CN109427698B (en) * | 2017-09-04 | 2023-08-29 | 恩智浦美国有限公司 | Method for assembling QFP type semiconductor device |
US10361631B2 (en) * | 2017-10-05 | 2019-07-23 | Monolithic Power Systems, Inc. | Symmetrical power stages for high power integrated circuits |
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US6326678B1 (en) * | 1993-09-03 | 2001-12-04 | Asat, Limited | Molded plastic package with heat sink and enhanced electrical performance |
JPH0846098A (en) * | 1994-07-22 | 1996-02-16 | Internatl Business Mach Corp <Ibm> | Equipment and method for forming direct heat conduction path |
TW452956B (en) * | 2000-01-04 | 2001-09-01 | Siliconware Precision Industries Co Ltd | Heat dissipation structure of BGA semiconductor package |
TW518733B (en) * | 2000-04-08 | 2003-01-21 | Advanced Semiconductor Eng | Attaching method of heat sink for chip package |
-
2004
- 2004-08-23 US US10/923,920 patent/US7074653B2/en not_active Expired - Lifetime
-
2005
- 2005-09-29 US US11/239,020 patent/US20060038202A1/en not_active Abandoned
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US20060038202A1 (en) | 2006-02-23 |
US7074653B2 (en) | 2006-07-11 |
US20060038282A1 (en) | 2006-02-23 |
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