+

US20060197164A1 - Epitaxially deposited source/drain - Google Patents

Epitaxially deposited source/drain Download PDF

Info

Publication number
US20060197164A1
US20060197164A1 US11/408,133 US40813306A US2006197164A1 US 20060197164 A1 US20060197164 A1 US 20060197164A1 US 40813306 A US40813306 A US 40813306A US 2006197164 A1 US2006197164 A1 US 2006197164A1
Authority
US
United States
Prior art keywords
source
drain
transistor
drain extension
gate electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/408,133
Inventor
Nick Lindert
Anand Murthy
Justin Brask
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tahoe Research Ltd
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to US11/408,133 priority Critical patent/US20060197164A1/en
Publication of US20060197164A1 publication Critical patent/US20060197164A1/en
Assigned to TAHOE RESEARCH, LTD. reassignment TAHOE RESEARCH, LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INTEL CORPORATION
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0275—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D44/00—Charge transfer devices
    • H10D44/40—Charge-coupled devices [CCD]
    • H10D44/45—Charge-coupled devices [CCD] having field effect produced by insulated gate electrodes 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling

Definitions

  • This invention relates generally to metal oxide semiconductor field effect transistors.
  • Metal oxide semiconductor field effect transistors include a gate that is self-aligned with a source/drain.
  • the source/drain may include a deeper or heavily doped region and a shallower and lightly doped region, sometimes called a tip or source/drain extension.
  • Gate underlap is the amount by which the source/drain material diffuses under the gate after ion implantation and subsequent heat processing. After implantation, the material that is implanted is exposed to heat which causes the material to move downwardly into the substrate and, to a lesser extent, laterally under the gate. Thus, in a system using an ion implanted source/drain extension, the amount of underdiffusion is determined as a function of junction depth.
  • the minimum tip junction depths are determined by the necessary gate underlap.
  • the shallower the source/drain extension generally the shorter the gate lengths that may be utilized without increasing off-state leakage currents.
  • Extension doping under the gate edge is needed to ensure a low resistance path between the inversion layer under the gate and the highly doped source/drain extension region. The low resistance is needed for a high drive currents, which are critical for high circuit switching speeds.
  • FIG. 1 is a greatly enlarged, cross-sectional view at one stage of manufacture
  • FIG. 2 is an enlarged, cross-sectional view at a subsequent stage of manufacture in accordance with one embodiment of the present invention
  • FIG. 3 is an enlarged, cross-sectional view at still a subsequent stage of manufacture in accordance with one embodiment of the present invention
  • FIG. 4 is an enlarged, cross-sectional view at a subsequent stage of manufacture in accordance with one embodiment of the present invention.
  • FIG. 5 is an enlarged, cross-sectional view at still a subsequent stage of manufacture in accordance with one embodiment of the present invention.
  • a heavily doped semiconductor substrate 12 may be covered by a sacrificial, undoped, or lightly doped epitaxial silicon layer 18 .
  • the layer 18 may be less than 500 Angstroms thick in one embodiment.
  • a gate electrode structure including a gate 16 formed over a gate dielectric 14 may be defined on the epitaxial silicon layer 18 .
  • the selective deposition of the sacrificial epitaxial silicon layer 18 may be carried out, for example, using dichlorosilane-based chemistry in a single wafer chemical vapor deposition reactor, such as an Epsilon 3000 epitaxial reactor, available from ASM International NV, Bilthoven, Netherlands.
  • the film may be deposited with gas flows of 150-200 sccm of dichlorosilane, 100-150 sccm of HCl, 20 slm of H 2 at 825° C. in a processed pressure of 20 Torr. Under these processing conditions, a deposition rate of 10-15 nanometers per minute may be achieved for silicon on exposed substrate while achieving selectivity to spacer and oxide regions. Other deposition techniques may also be used.
  • the arrangement shown in FIG. 1 is sometimes called a delta doped transistor. Because there is relatively high doping below the epitaxial layer 18 , a large delta or change in concentration occurs at the interface between the substrate 12 and the epitaxial silicon layer 18 .
  • the structure shown in FIG. 1 may be covered by a spacer material and then anisotropically etched to form the sidewall spacers 28 shown in FIG. 2 .
  • Some limited etching of the epitaxial silicon 18 may occur at the same time depending on the selectivity of the spacer etch.
  • a selective wet etch may remove the exposed portions of the epitaxial silicon layer 18 and may continue etching under the gate 16 to achieve the undercut structure shown in FIG. 3 .
  • the extent of gate 16 undercut can be controlled by adjusting the etch time.
  • the epitaxial silicon layer 18 may be selectively etched with a variety of hydroxide-based solutions, for example. However, for high selectivity of the undoped or lightly doped layer 18 to the heavily doped substrate 12 , relatively mild processing conditions may be employed.
  • an aqueous ammonium hydroxide solution in the concentration range of 2 to 10 percent by volume at 20° C. may be used together with sonication.
  • the sonication may be provided by a transducer that dissipates ultra or megasonic energy with a power of 0.5 to 5 watts per cm 2 in one embodiment of the present invention. Since the delta doped transistor has a heavily doped region below the undoped region, it may serve as an etch stop layer for the wet etch.
  • a doped selective epitaxial silicon layer 50 may be grown.
  • a shallow, highly doped source/drain extension 50 a laterally extends the desired distance under the gate 16 edge and the sidewall spacer 28 , as shown in FIG. 4 .
  • a thicker source/drain region 50 b is aligned with the edge of the spacer 28 and extends away from the spacer 28 .
  • the spacer 28 enables the length of the extension 50 a to be tailored and allows the thickness of the layer 50 to expand without shorting to the gate 16 .
  • the thicker region 50 b reduces resistance of the region 50 and brings the lower resistance region close to the edge of the gate 16 .
  • the source/drain extension 50 a and raised source/drain 50 b may be formed by selectively depositing epitaxial boron doped silicon or silicon germanium with a germanium concentration of up to 30 percent, as one example.
  • a highly doped silicon germanium film with a deposition rate of 20 nanometers per minute, a boron concentration of 1E20 cm ⁇ 3 , and a germanium concentration of 20 percent may be achieved in one embodiment.
  • a low resistivity of 0.7-0.9 mOhm-cm results from the high boron concentration of the film.
  • Low resistivity provide the benefit of high conductivity in the extension and source/drain regions in some embodiments. This lowered resistivity may reduce the external resistance.
  • the larger unit cell of the silicon germanium present in source/drain regions 50 b may exert compressive strain on the channel, which in turn may result in enhanced mobility and transistor performance in some embodiments.
  • the source/drain 50 b and source/drain extension 50 a may be formed using in situ phosphorus doped silicon deposited in one embodiment.
  • the silicon may be deposited selectively under processing conditions of 100 sccm of dichlorosilane, 25-50 sccm HCl, 200-300 sccm of 1 percent PH 3 with a H 2 gas carrier flow of 20 slm at 750° C. and 20 Torr.
  • a phosphorous concentration of 2E20 cm ⁇ 3 with a resistivity of 0.4-0.6 mOhm-cm may be achieved in the deposited film in one embodiment.
  • a second thin spacer 34 may be formed using conventional techniques as shown in FIG. 5 .
  • a deep source/drain 32 may be formed by ion implantation using the spacers 28 and 34 and the gate 16 as a mask. The annealing of the deep source/drain 32 may be done in a way that reduces or minimizes the dopant diffusion including the dopant in the layer 50 .
  • the characteristics of the shallow source/drain extensions 50 a and the degree by which they underlap the gate 16 may be independent of the characteristics of the deep source/drain junction 32 .
  • the extent of extension underlap of the gate 16 of the source/drain extension 50 a may be controlled as desired.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

An epitaxially deposited source/drain extension may be formed for a metal oxide semiconductor field effect transistor. A sacrificial layer may be formed and etched away to undercut under the gate electrode. Then a source/drain extension of epitaxial silicon may be deposited to extend under the edges of the gate electrode. As a result, the extent by which the source/drain extension extends under the gate may be controlled by controlling the etching of the sacrificial material. Its thickness and depth may be controlled by controlling the deposition process. Moreover, the characteristics of the source/drain extension may be controlled independently of those of the subsequently formed deep or heavily doped source/drain junction.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application is a divisional of U.S. patent application Ser. No. 10/692,696, filed on Oct. 24, 2003.
    • BACKGROUND
  • This invention relates generally to metal oxide semiconductor field effect transistors.
  • Metal oxide semiconductor field effect transistors include a gate that is self-aligned with a source/drain. The source/drain may include a deeper or heavily doped region and a shallower and lightly doped region, sometimes called a tip or source/drain extension.
  • Gate underlap is the amount by which the source/drain material diffuses under the gate after ion implantation and subsequent heat processing. After implantation, the material that is implanted is exposed to heat which causes the material to move downwardly into the substrate and, to a lesser extent, laterally under the gate. Thus, in a system using an ion implanted source/drain extension, the amount of underdiffusion is determined as a function of junction depth.
  • It is desirable to have relatively shallow junction depth for the source/drain extension to support smaller transistor dimensions. Usually, in source/drain extension implantation techniques, the minimum tip junction depths are determined by the necessary gate underlap.
  • The shallower the source/drain extension, generally the shorter the gate lengths that may be utilized without increasing off-state leakage currents. Extension doping under the gate edge is needed to ensure a low resistance path between the inversion layer under the gate and the highly doped source/drain extension region. The low resistance is needed for a high drive currents, which are critical for high circuit switching speeds.
  • Thus, there is a need for better ways to make source/drain junctions of field effect transistors.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a greatly enlarged, cross-sectional view at one stage of manufacture;
  • FIG. 2 is an enlarged, cross-sectional view at a subsequent stage of manufacture in accordance with one embodiment of the present invention;
  • FIG. 3 is an enlarged, cross-sectional view at still a subsequent stage of manufacture in accordance with one embodiment of the present invention;
  • FIG. 4 is an enlarged, cross-sectional view at a subsequent stage of manufacture in accordance with one embodiment of the present invention; and
  • FIG. 5 is an enlarged, cross-sectional view at still a subsequent stage of manufacture in accordance with one embodiment of the present invention.
    • DETAILED DESCRIPTION
  • Referring to FIG. 1, a heavily doped semiconductor substrate 12 may be covered by a sacrificial, undoped, or lightly doped epitaxial silicon layer 18. The layer 18 may be less than 500 Angstroms thick in one embodiment. A gate electrode structure including a gate 16 formed over a gate dielectric 14 may be defined on the epitaxial silicon layer 18.
  • The selective deposition of the sacrificial epitaxial silicon layer 18 may be carried out, for example, using dichlorosilane-based chemistry in a single wafer chemical vapor deposition reactor, such as an Epsilon 3000 epitaxial reactor, available from ASM International NV, Bilthoven, Netherlands. The film may be deposited with gas flows of 150-200 sccm of dichlorosilane, 100-150 sccm of HCl, 20 slm of H2 at 825° C. in a processed pressure of 20 Torr. Under these processing conditions, a deposition rate of 10-15 nanometers per minute may be achieved for silicon on exposed substrate while achieving selectivity to spacer and oxide regions. Other deposition techniques may also be used.
  • The arrangement shown in FIG. 1 is sometimes called a delta doped transistor. Because there is relatively high doping below the epitaxial layer 18, a large delta or change in concentration occurs at the interface between the substrate 12 and the epitaxial silicon layer 18.
  • The structure shown in FIG. 1 may be covered by a spacer material and then anisotropically etched to form the sidewall spacers 28 shown in FIG. 2. Some limited etching of the epitaxial silicon 18 may occur at the same time depending on the selectivity of the spacer etch.
  • After spacer formation, a selective wet etch may remove the exposed portions of the epitaxial silicon layer 18 and may continue etching under the gate 16 to achieve the undercut structure shown in FIG. 3. The extent of gate 16 undercut can be controlled by adjusting the etch time.
  • The epitaxial silicon layer 18 may be selectively etched with a variety of hydroxide-based solutions, for example. However, for high selectivity of the undoped or lightly doped layer 18 to the heavily doped substrate 12, relatively mild processing conditions may be employed.
  • In one embodiment, an aqueous ammonium hydroxide solution in the concentration range of 2 to 10 percent by volume at 20° C. may be used together with sonication. The sonication may be provided by a transducer that dissipates ultra or megasonic energy with a power of 0.5 to 5 watts per cm2 in one embodiment of the present invention. Since the delta doped transistor has a heavily doped region below the undoped region, it may serve as an etch stop layer for the wet etch.
  • After the wet etch undercut, a doped selective epitaxial silicon layer 50 may be grown. A shallow, highly doped source/drain extension 50 a laterally extends the desired distance under the gate 16 edge and the sidewall spacer 28, as shown in FIG. 4. A thicker source/drain region 50 b is aligned with the edge of the spacer 28 and extends away from the spacer 28. The spacer 28 enables the length of the extension 50 a to be tailored and allows the thickness of the layer 50 to expand without shorting to the gate 16. The thicker region 50 b reduces resistance of the region 50 and brings the lower resistance region close to the edge of the gate 16.
  • In forming the P-type MOS (PMOS) transistor, the source/drain extension 50 a and raised source/drain 50 b may be formed by selectively depositing epitaxial boron doped silicon or silicon germanium with a germanium concentration of up to 30 percent, as one example. Under the processing conditions of 100 sccm of dichlorosilane, 20 slm H2, 750-800° C., 20 Torr, 150-200 sccm HCl, diborane flow of 150-200 sccm and GeH4 flow of 150-200 sccm, a highly doped silicon germanium film with a deposition rate of 20 nanometers per minute, a boron concentration of 1E20 cm−3, and a germanium concentration of 20 percent may be achieved in one embodiment. A low resistivity of 0.7-0.9 mOhm-cm results from the high boron concentration of the film.
  • Low resistivity provide the benefit of high conductivity in the extension and source/drain regions in some embodiments. This lowered resistivity may reduce the external resistance. The larger unit cell of the silicon germanium present in source/drain regions 50 b may exert compressive strain on the channel, which in turn may result in enhanced mobility and transistor performance in some embodiments.
  • In the N-type transistor (NMOS), the source/drain 50 b and source/drain extension 50 a may be formed using in situ phosphorus doped silicon deposited in one embodiment. The silicon may be deposited selectively under processing conditions of 100 sccm of dichlorosilane, 25-50 sccm HCl, 200-300 sccm of 1 percent PH3 with a H2 gas carrier flow of 20 slm at 750° C. and 20 Torr. A phosphorous concentration of 2E20 cm−3 with a resistivity of 0.4-0.6 mOhm-cm may be achieved in the deposited film in one embodiment.
  • Thereafter, a second thin spacer 34 may be formed using conventional techniques as shown in FIG. 5. A deep source/drain 32 may be formed by ion implantation using the spacers 28 and 34 and the gate 16 as a mask. The annealing of the deep source/drain 32 may be done in a way that reduces or minimizes the dopant diffusion including the dopant in the layer 50.
  • The characteristics of the shallow source/drain extensions 50 a and the degree by which they underlap the gate 16 may be independent of the characteristics of the deep source/drain junction 32. The extent of extension underlap of the gate 16 of the source/drain extension 50 a may be controlled as desired.
  • While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.

Claims (7)

1. A field effect transistor comprising:
a substrate;
a doped epitaxial semiconductor material formed over said substrate; and
a gate electrode formed over said doped epitaxial semiconductor material, said doped epitaxial semiconductor material extending under said gate electrode.
2. The transistor of claim 1 including a source/drain having a source/drain extension, said source/drain extension being formed of said doped epitaxial semiconductor material and extends under the edges of the gate electrode.
3. The transistor of claim 2 wherein said material has a first thickness near said gate electrode and a second thickness spaced from said gate electrode, said second thickness being greater than said first thickness.
4. The transistor of claim 3 including a sidewall spacer, said material extending under said sidewall spacer.
5. The transistor of claim 4 wherein said second thickness is aligned with said sidewall spacer.
6. The transistor of claim 1 wherein said transistor is a delta doped transistor.
7. The transistor of claim 1 including an ion implanted source/drain under said doped epitaxial semiconductor material.
US11/408,133 2003-10-24 2006-04-20 Epitaxially deposited source/drain Abandoned US20060197164A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/408,133 US20060197164A1 (en) 2003-10-24 2006-04-20 Epitaxially deposited source/drain

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/692,696 US7060576B2 (en) 2003-10-24 2003-10-24 Epitaxially deposited source/drain
US11/408,133 US20060197164A1 (en) 2003-10-24 2006-04-20 Epitaxially deposited source/drain

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US10/692,696 Division US7060576B2 (en) 2003-10-24 2003-10-24 Epitaxially deposited source/drain

Publications (1)

Publication Number Publication Date
US20060197164A1 true US20060197164A1 (en) 2006-09-07

Family

ID=34522194

Family Applications (2)

Application Number Title Priority Date Filing Date
US10/692,696 Expired - Lifetime US7060576B2 (en) 2003-10-24 2003-10-24 Epitaxially deposited source/drain
US11/408,133 Abandoned US20060197164A1 (en) 2003-10-24 2006-04-20 Epitaxially deposited source/drain

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US10/692,696 Expired - Lifetime US7060576B2 (en) 2003-10-24 2003-10-24 Epitaxially deposited source/drain

Country Status (6)

Country Link
US (2) US7060576B2 (en)
KR (1) KR100841806B1 (en)
CN (1) CN1898785B (en)
DE (1) DE112004002017B4 (en)
TW (1) TWI260776B (en)
WO (1) WO2005041288A1 (en)

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060199346A1 (en) * 2004-09-30 2006-09-07 Texas Instruments Incorporated Source/Drain Extensions Having Highly Activated and Extremely Abrupt Junctions
US20060289856A1 (en) * 2005-06-22 2006-12-28 Fujitsu Limited Semiconductor device and production method thereof
US20070012913A1 (en) * 2005-06-22 2007-01-18 Fujitsu Limited Semiconductor device and production method thereof
US20080067545A1 (en) * 2006-09-20 2008-03-20 Samsung Electronics Co., Ltd Semiconductor device including field effect transistor and method of forming the same
US20110168982A1 (en) * 2010-01-08 2011-07-14 International Business Machines Corporation Nanowire pin tunnel field effect devices
US20120138900A1 (en) * 2009-12-04 2012-06-07 International Business Machines Corporation Omega Shaped Nanowire Tunnel Field Effect Transistors
US8520430B2 (en) 2010-04-13 2013-08-27 International Business Machines Corporation Nanowire circuits in matched devices
US8536563B2 (en) 2010-09-17 2013-09-17 International Business Machines Corporation Nanowire field effect transistors
US8586966B2 (en) 2010-08-16 2013-11-19 International Business Machines Corporation Contacts for nanowire field effect transistors
US8680589B2 (en) 2009-12-04 2014-03-25 International Business Machines Corporation Omega shaped nanowire field effect transistors
US8723162B2 (en) 2010-05-12 2014-05-13 International Business Machines Corporation Nanowire tunnel field effect transistors
US8772755B2 (en) 2010-05-10 2014-07-08 International Business Machines Corporation Directionally etched nanowire field effect transistors
US20140299919A1 (en) * 2012-07-19 2014-10-09 Haizhou Yin Semiconductor device and method for manufacturing the same
US9184301B2 (en) 2009-12-04 2015-11-10 Globalfoundries Inc. Planar and nanowire field effect transistors
US20160056261A1 (en) * 2014-08-22 2016-02-25 Globalfoundries Inc. Embedded sigma-shaped semiconductor alloys formed in transistors
TWI839469B (en) * 2019-03-28 2024-04-21 美商英特爾股份有限公司 Source or drain structures with low resistivity

Families Citing this family (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8994104B2 (en) 1999-09-28 2015-03-31 Intel Corporation Contact resistance reduction employing germanium overlayer pre-contact metalization
TWI463526B (en) * 2004-06-24 2014-12-01 Ibm Method for improving stress-induced CMOS components and components prepared by the method
US7122435B2 (en) * 2004-08-02 2006-10-17 Texas Instruments Incorporated Methods, systems and structures for forming improved transistors
US7332439B2 (en) * 2004-09-29 2008-02-19 Intel Corporation Metal gate transistors with epitaxial source and drain regions
US20060151808A1 (en) * 2005-01-12 2006-07-13 Chien-Hao Chen MOSFET device with localized stressor
US7494858B2 (en) 2005-06-30 2009-02-24 Intel Corporation Transistor with improved tip profile and method of manufacture thereof
US7525160B2 (en) * 2005-12-27 2009-04-28 Intel Corporation Multigate device with recessed strain regions
US7943456B2 (en) * 2008-12-31 2011-05-17 Texas Instruments Incorporated Selective wet etch process for CMOS ICs having embedded strain inducing regions and integrated circuits therefrom
US9318571B2 (en) * 2009-02-23 2016-04-19 United Microelectronics Corp. Gate structure and method for trimming spacers
US8598003B2 (en) * 2009-12-21 2013-12-03 Intel Corporation Semiconductor device having doped epitaxial region and its methods of fabrication
US20120126341A1 (en) * 2010-11-23 2012-05-24 Microchip Technology Incorporated Using low pressure epi to enable low rdson fet
US8901537B2 (en) 2010-12-21 2014-12-02 Intel Corporation Transistors with high concentration of boron doped germanium
US9484432B2 (en) 2010-12-21 2016-11-01 Intel Corporation Contact resistance reduction employing germanium overlayer pre-contact metalization
US8466502B2 (en) 2011-03-24 2013-06-18 United Microelectronics Corp. Metal-gate CMOS device
US8445363B2 (en) 2011-04-21 2013-05-21 United Microelectronics Corp. Method of fabricating an epitaxial layer
US8324059B2 (en) 2011-04-25 2012-12-04 United Microelectronics Corp. Method of fabricating a semiconductor structure
US8426284B2 (en) 2011-05-11 2013-04-23 United Microelectronics Corp. Manufacturing method for semiconductor structure
US8481391B2 (en) 2011-05-18 2013-07-09 United Microelectronics Corp. Process for manufacturing stress-providing structure and semiconductor device with such stress-providing structure
US8431460B2 (en) 2011-05-27 2013-04-30 United Microelectronics Corp. Method for fabricating semiconductor device
CN102891175B (en) * 2011-07-19 2016-03-16 中芯国际集成电路制造(北京)有限公司 Semiconductor device and manufacture method thereof
US9263566B2 (en) 2011-07-19 2016-02-16 Semiconductor Manufacturing International (Beijing) Corporation Semiconductor device and manufacturing method thereof
CN102891178A (en) 2011-07-19 2013-01-23 中芯国际集成电路制造(北京)有限公司 Semiconductor device and manufacturing method thereof
CN102891176B (en) * 2011-07-19 2016-06-01 中芯国际集成电路制造(北京)有限公司 Semiconductor device and manufacture method thereof
US8716750B2 (en) 2011-07-25 2014-05-06 United Microelectronics Corp. Semiconductor device having epitaxial structures
US8575043B2 (en) 2011-07-26 2013-11-05 United Microelectronics Corp. Semiconductor device and manufacturing method thereof
US8647941B2 (en) 2011-08-17 2014-02-11 United Microelectronics Corp. Method of forming semiconductor device
US8674433B2 (en) 2011-08-24 2014-03-18 United Microelectronics Corp. Semiconductor process
US8476169B2 (en) 2011-10-17 2013-07-02 United Microelectronics Corp. Method of making strained silicon channel semiconductor structure
US8691659B2 (en) 2011-10-26 2014-04-08 United Microelectronics Corp. Method for forming void-free dielectric layer
US8754448B2 (en) 2011-11-01 2014-06-17 United Microelectronics Corp. Semiconductor device having epitaxial layer
US8647953B2 (en) 2011-11-17 2014-02-11 United Microelectronics Corp. Method for fabricating first and second epitaxial cap layers
US8709930B2 (en) 2011-11-25 2014-04-29 United Microelectronics Corp. Semiconductor process
CN103247530B (en) * 2012-02-10 2015-12-16 中芯国际集成电路制造(上海)有限公司 A kind of manufacture method of semiconductor device
US20130214358A1 (en) 2012-02-17 2013-08-22 International Business Machines Corporation Low external resistance etsoi transistors
US9136348B2 (en) 2012-03-12 2015-09-15 United Microelectronics Corp. Semiconductor structure and fabrication method thereof
US9202914B2 (en) 2012-03-14 2015-12-01 United Microelectronics Corporation Semiconductor device and method for fabricating the same
US8664069B2 (en) 2012-04-05 2014-03-04 United Microelectronics Corp. Semiconductor structure and process thereof
US8866230B2 (en) 2012-04-26 2014-10-21 United Microelectronics Corp. Semiconductor devices
US8835243B2 (en) 2012-05-04 2014-09-16 United Microelectronics Corp. Semiconductor process
US8951876B2 (en) 2012-06-20 2015-02-10 United Microelectronics Corp. Semiconductor device and manufacturing method thereof
US8796695B2 (en) 2012-06-22 2014-08-05 United Microelectronics Corp. Multi-gate field-effect transistor and process thereof
US8710632B2 (en) 2012-09-07 2014-04-29 United Microelectronics Corp. Compound semiconductor epitaxial structure and method for fabricating the same
US9117925B2 (en) 2013-01-31 2015-08-25 United Microelectronics Corp. Epitaxial process
US8753902B1 (en) 2013-03-13 2014-06-17 United Microelectronics Corp. Method of controlling etching process for forming epitaxial structure
US9034705B2 (en) 2013-03-26 2015-05-19 United Microelectronics Corp. Method of forming semiconductor device
US9064893B2 (en) 2013-05-13 2015-06-23 United Microelectronics Corp. Gradient dopant of strained substrate manufacturing method of semiconductor device
US9076652B2 (en) 2013-05-27 2015-07-07 United Microelectronics Corp. Semiconductor process for modifying shape of recess
US8853060B1 (en) 2013-05-27 2014-10-07 United Microelectronics Corp. Epitaxial process
US8765546B1 (en) 2013-06-24 2014-07-01 United Microelectronics Corp. Method for fabricating fin-shaped field-effect transistor
US9412842B2 (en) 2013-07-03 2016-08-09 Samsung Electronics Co., Ltd. Method for fabricating semiconductor device
US8895396B1 (en) 2013-07-11 2014-11-25 United Microelectronics Corp. Epitaxial Process of forming stress inducing epitaxial layers in source and drain regions of PMOS and NMOS structures
US8981487B2 (en) 2013-07-31 2015-03-17 United Microelectronics Corp. Fin-shaped field-effect transistor (FinFET)
US9324830B2 (en) 2014-03-27 2016-04-26 International Business Machines Corporation Self-aligned contact process enabled by low temperature
US9831341B2 (en) * 2014-06-16 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for integrated circuit
US9627512B2 (en) * 2014-08-13 2017-04-18 Taiwan Semiconductor Manufacturing Company Ltd. Field effect transistor with non-doped channel
KR102326316B1 (en) * 2015-04-10 2021-11-16 삼성전자주식회사 Semiconductor dievices and methods of manufacturing the same
US9805989B1 (en) 2016-09-22 2017-10-31 International Business Machines Corporation Sacrificial cap for forming semiconductor contact
CN112582476B (en) * 2020-12-09 2022-05-06 全芯智造技术有限公司 Semiconductor device and method of forming the same

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6015740A (en) * 1997-02-10 2000-01-18 Advanced Micro Devices, Inc. Method of fabricating CMOS devices with ultra-shallow junctions and reduced drain area
US6214679B1 (en) * 1999-12-30 2001-04-10 Intel Corporation Cobalt salicidation method on a silicon germanium film
US20020001926A1 (en) * 2000-06-20 2002-01-03 Taiji Noda Semiconductor device and method for fabricating the same
US6403434B1 (en) * 2001-02-09 2002-06-11 Advanced Micro Devices, Inc. Process for manufacturing MOS transistors having elevated source and drain regions and a high-k gate dielectric
US6403433B1 (en) * 1999-09-16 2002-06-11 Advanced Micro Devices, Inc. Source/drain doping technique for ultra-thin-body SOI MOS transistors
US6406951B1 (en) * 2001-02-12 2002-06-18 Advanced Micro Devices, Inc. Fabrication of fully depleted field effect transistor with raised source and drain in SOI technology
US20030139001A1 (en) * 2002-01-23 2003-07-24 Snyder John P. Field effect transistor having source and/or drain forming schottky or schottky-like contact with strained semiconductor substrate
US6605498B1 (en) * 2002-03-29 2003-08-12 Intel Corporation Semiconductor transistor having a backfilled channel material
US20050079691A1 (en) * 2003-10-10 2005-04-14 Applied Materials, Inc. Methods of selective deposition of heavily doped epitaxial SiGe
US6887762B1 (en) * 1998-11-12 2005-05-03 Intel Corporation Method of fabricating a field effect transistor structure with abrupt source/drain junctions

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6313379A (en) 1986-07-04 1988-01-20 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device and manufacture thereof
US5384497A (en) * 1992-11-04 1995-01-24 At&T Corp. Low-skew signal routing in a programmable array
JP3761918B2 (en) 1994-09-13 2006-03-29 株式会社東芝 Manufacturing method of semiconductor device
KR980005893A (en) * 1996-06-21 1998-03-30 김주용 Method of manufacturing transistor of semiconductor device
US6159815A (en) * 1996-09-27 2000-12-12 Siemens Aktiengesellschaft Method of producing a MOS transistor
JP2967477B2 (en) * 1997-11-26 1999-10-25 日本電気株式会社 Method for manufacturing semiconductor device
US5998835A (en) * 1998-02-17 1999-12-07 International Business Machines Corporation High performance MOSFET device with raised source and drain
KR20010080432A (en) 1998-11-12 2001-08-22 피터 엔. 데트킨 Field effect transistor structure with abrupt source/drain junctions
US7391087B2 (en) * 1999-12-30 2008-06-24 Intel Corporation MOS transistor structure and method of fabrication
KR100416686B1 (en) * 2000-10-12 2004-01-31 주식회사 메디슨 Integrated circuit for generating high voltage pulse for use in a medical ultrasound diagnostic system

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6015740A (en) * 1997-02-10 2000-01-18 Advanced Micro Devices, Inc. Method of fabricating CMOS devices with ultra-shallow junctions and reduced drain area
US6887762B1 (en) * 1998-11-12 2005-05-03 Intel Corporation Method of fabricating a field effect transistor structure with abrupt source/drain junctions
US6403433B1 (en) * 1999-09-16 2002-06-11 Advanced Micro Devices, Inc. Source/drain doping technique for ultra-thin-body SOI MOS transistors
US6214679B1 (en) * 1999-12-30 2001-04-10 Intel Corporation Cobalt salicidation method on a silicon germanium film
US20020001926A1 (en) * 2000-06-20 2002-01-03 Taiji Noda Semiconductor device and method for fabricating the same
US6720632B2 (en) * 2000-06-20 2004-04-13 Matsushita Electric Industrial Co., Ltd. Semiconductor device having diffusion layer formed using dopant of large mass number
US6403434B1 (en) * 2001-02-09 2002-06-11 Advanced Micro Devices, Inc. Process for manufacturing MOS transistors having elevated source and drain regions and a high-k gate dielectric
US6406951B1 (en) * 2001-02-12 2002-06-18 Advanced Micro Devices, Inc. Fabrication of fully depleted field effect transistor with raised source and drain in SOI technology
US20030139001A1 (en) * 2002-01-23 2003-07-24 Snyder John P. Field effect transistor having source and/or drain forming schottky or schottky-like contact with strained semiconductor substrate
US6605498B1 (en) * 2002-03-29 2003-08-12 Intel Corporation Semiconductor transistor having a backfilled channel material
US20050079691A1 (en) * 2003-10-10 2005-04-14 Applied Materials, Inc. Methods of selective deposition of heavily doped epitaxial SiGe

Cited By (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060199346A1 (en) * 2004-09-30 2006-09-07 Texas Instruments Incorporated Source/Drain Extensions Having Highly Activated and Extremely Abrupt Junctions
US8164085B2 (en) 2005-06-22 2012-04-24 Fujitsu Semiconductor Limited Semiconductor device and production method thereof
US20060289856A1 (en) * 2005-06-22 2006-12-28 Fujitsu Limited Semiconductor device and production method thereof
US20070012913A1 (en) * 2005-06-22 2007-01-18 Fujitsu Limited Semiconductor device and production method thereof
US7579617B2 (en) * 2005-06-22 2009-08-25 Fujitsu Microelectronics Limited Semiconductor device and production method thereof
US20090280612A1 (en) * 2005-06-22 2009-11-12 Fujitsu Microelectronics Limited Semiconductor device and production method thereof
US7683362B2 (en) 2005-06-22 2010-03-23 Fujitsu Microelectronics Limited Semiconductor device and production method thereof
US20100129971A1 (en) * 2005-06-22 2010-05-27 Fujitsu Microelectronics Limited Semiconductor device and production method thereof
US7875521B2 (en) 2005-06-22 2011-01-25 Fujitsu Semiconductor Limited Semiconductor device and production method thereof
US20110049533A1 (en) * 2005-06-22 2011-03-03 Fujitsu Semiconductor Limited Semiconductor device and production method thereof
US7968414B2 (en) 2005-06-22 2011-06-28 Fujitsu Semiconductor Limited Semiconductor device and production method thereof
US20080067545A1 (en) * 2006-09-20 2008-03-20 Samsung Electronics Co., Ltd Semiconductor device including field effect transistor and method of forming the same
US8507892B2 (en) * 2009-12-04 2013-08-13 International Business Machines Corporation Omega shaped nanowire tunnel field effect transistors
US9184301B2 (en) 2009-12-04 2015-11-10 Globalfoundries Inc. Planar and nanowire field effect transistors
US20120138900A1 (en) * 2009-12-04 2012-06-07 International Business Machines Corporation Omega Shaped Nanowire Tunnel Field Effect Transistors
US8680589B2 (en) 2009-12-04 2014-03-25 International Business Machines Corporation Omega shaped nanowire field effect transistors
US9105482B2 (en) 2010-01-08 2015-08-11 International Business Machines Corporation Nanowire PIN tunnel field effect devices
US20110168982A1 (en) * 2010-01-08 2011-07-14 International Business Machines Corporation Nanowire pin tunnel field effect devices
US8722492B2 (en) 2010-01-08 2014-05-13 International Business Machines Corporation Nanowire pin tunnel field effect devices
US8520430B2 (en) 2010-04-13 2013-08-27 International Business Machines Corporation Nanowire circuits in matched devices
US8772755B2 (en) 2010-05-10 2014-07-08 International Business Machines Corporation Directionally etched nanowire field effect transistors
US8723162B2 (en) 2010-05-12 2014-05-13 International Business Machines Corporation Nanowire tunnel field effect transistors
US8586966B2 (en) 2010-08-16 2013-11-19 International Business Machines Corporation Contacts for nanowire field effect transistors
US8835231B2 (en) 2010-08-16 2014-09-16 International Business Machines Corporation Methods of forming contacts for nanowire field effect transistors
US8536563B2 (en) 2010-09-17 2013-09-17 International Business Machines Corporation Nanowire field effect transistors
US20140299919A1 (en) * 2012-07-19 2014-10-09 Haizhou Yin Semiconductor device and method for manufacturing the same
US9147762B2 (en) * 2012-07-19 2015-09-29 Institute of Microelectronics, Chinese Academy of Sciences Semiconductor device and method for manufacturing the same
US20160056261A1 (en) * 2014-08-22 2016-02-25 Globalfoundries Inc. Embedded sigma-shaped semiconductor alloys formed in transistors
TWI839469B (en) * 2019-03-28 2024-04-21 美商英特爾股份有限公司 Source or drain structures with low resistivity
US12027585B2 (en) 2019-03-28 2024-07-02 Intel Corporation Source or drain structures with low resistivity

Also Published As

Publication number Publication date
KR20060060058A (en) 2006-06-02
CN1898785B (en) 2011-09-07
CN1898785A (en) 2007-01-17
US7060576B2 (en) 2006-06-13
TW200515596A (en) 2005-05-01
DE112004002017T5 (en) 2006-08-31
DE112004002017B4 (en) 2009-03-05
KR100841806B1 (en) 2008-06-26
TWI260776B (en) 2006-08-21
WO2005041288A1 (en) 2005-05-06
US20050087801A1 (en) 2005-04-28

Similar Documents

Publication Publication Date Title
US7060576B2 (en) Epitaxially deposited source/drain
CN103560150B (en) Metal gate transistors with epitaxial source and drain regions
US7718500B2 (en) Formation of raised source/drain structures in NFET with embedded SiGe in PFET
US7402872B2 (en) Method for forming an integrated circuit
CN102656672B (en) There is multiple-grid semiconductor device and the manufacture method thereof of self-Aligned Epitaxial source and leakage
US6797556B2 (en) MOS transistor structure and method of fabrication
JP5030774B2 (en) Transistor formation method
US7410875B2 (en) Semiconductor structure and fabrication thereof
CN101202305B (en) Semiconductor device with improved source and drain and method of manufacturing the same
US20110127614A1 (en) Reducing the series resistance in sophisticated transistors by embedding metal silicide contact regions reliably into highly doped semiconductor material
US9209299B2 (en) Transistor device and fabrication method
KR20020091886A (en) A method of forming shallow junction using SiGe selective epitaxial growth
CN100561689C (en) Methods for forming transistors
US20080070360A1 (en) Method and structure for forming silicide contacts on embedded silicon germanium regions of cmos devices
KR100475034B1 (en) Most transistors with elevated source / drain regions and methods of manufacturing the same
WO2011052108A1 (en) Semiconductor device and method for manufacturing same
KR100286903B1 (en) a method for making MOS transistor
EP1905068A2 (en) Technique for reducing silicide non-uniformities by adapting avertical dopant profile
US20040238858A1 (en) Semiconductor device and a method of manufacturing the same

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION

AS Assignment

Owner name: TAHOE RESEARCH, LTD., IRELAND

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTEL CORPORATION;REEL/FRAME:061175/0176

Effective date: 20220718

点击 这是indexloc提供的php浏览器服务，不要输入任何密码和下载