US20060156104A1

US20060156104A1 - Wrapper testing circuits and method thereof for system-on-a-chip

Info

Publication number: US20060156104A1
Application number: US11/140,745
Authority: US
Inventors: Yeong-Jar Chang; Wen-Ching Wu; Kun-Lun Luo; Chia-Jen Lee
Original assignee: Industrial Technology Research Institute ITRI
Current assignee: Industrial Technology Research Institute ITRI
Priority date: 2004-12-29
Filing date: 2005-06-01
Publication date: 2006-07-13
Also published as: US7506231B2; TWI263058B; US20070255986A1; TW200622267A

Abstract

A wrapper testing circuit and method thereof for System-On-a-Chip is provided for electrical tests of core circuits of an integrated circuit. The testing circuit includes a decoding logic with an encoding table for receiving test signals and delivering control signals in response to the test signals according to the table; a plurality of registers for saving the control signals temporarily and delivering the control signals to the core circuits; a bypass circuit for delivering the test signals; and an instruction register for saving the test signals temporarily and refreshing the data in the registers and the bypass circuits after the decoding logic issues the control signals. The encoding of the control signals is completed in one period. Compared with the serial encoding in the prior art, test time is reduced.

Description

This application claims the benefit of Taiwan Patent Application No. 93141234, filed on Dec. 29, 2004, which is hereby incorporated by reference for all purposes as if fully set forth herein.

BACKGROUND

1. Field of Invention
The invention relates to a test circuit, and in particular to a test circuit that is applicable for system-on-a-chip and compliant with IEEE P1500 standard.
2. Related Art
Continuous development of integrated circuits has increased in the chip integrity such that integrating a complicated system on an independent System-On-a-Chip (SOC) has become an economic and feasible scheme. Chip integrated applications have thus also increased. System-On-a-Chip combines core circuits, such as the CPU, digital signal processor, memory, digital to analog converter, analog to digital converter, phase lock loop, and ASIC. However, the fault coverage greatly decreases. For verifying oneness of chips effectively, the Institute of Electrical & Electronic Engineers (IEEE) has provided a test scheme standard: IEEE P 1500 for System-On-a-Chip to solve the problem of low fault coverage.
The proposal of the P1500 standard is to plan a test architecture for core circuits. The standard must include: (a) define the testing interface between core circuits and System-On-a-Chip; (b) establish an access and isolation mechanism for core circuits such that the test patterns and procedures designed for these core circuits may be reused; (c) be capable of testing the connection between core circuits and testing User-Defined Logic (UDL); (d) integrate the core circuits compliant with P1500 standard into System-On-a-Chip by way of plug-and-play, and the testing between core circuits is need to cooperate with one another.
However, IEEE P1500 only establishes a standard for access and isolation mechanism including control mechanism of pin protocols and test modes for core circuits. However, the test access mechanism (TAM) of the system is reserved for system developers. Furthermore, the core circuits such as BIST, Scan, and IDDQ are reserved for designers. P1500 is in charge of supporting, activating, and controlling these test circuits for test operations.
In the test scheme of IEEE P1500, the core circuit is tested with the P1500 standard wrapper through the I/O ports of the access mechanism (TAM-source, TAM-link). The test data is delivered to the core circuit by way of TAM-source and WSI, and the test results are outputted from TAM-sink and WSO. The control signals necessary for the data transfer and test procedure are provided by a controller.
FIG. 1 illustrates the test scheme. The test circuit includes four registers 11˜14, multiplexers 15˜16, a bypass circuit 17, a decoder 18, and an instruction register 19 (Wrapper Instruction Register, WIR) to test the core circuit 10. The registers 11˜14 are Wrapper Boundary Registers (WBR), each composed of a plurality of Wrapper Boundary Cells (WBC). The number of the Wrapper Boundary Cells corresponds to the I/O pins of a chip. The instruction decoder 19 is a four-bit register.
The data path starts from Wrapper Serial Input (WSI) to Wrapper Serial output (WSO) passing through registers and multiplexers.
During the test process, the control signals (WIP Controls & Clocks) are employed to deliver instructions to the instruction register 19 (Wrapper Instruction Register, WIR). The decoder 18 decodes the instructions. Then, the decoded instructions together with the control signals change the data in the registers 11˜14 and the bypass circuit 17 for test operations.
P1500 establishes test circuits, which have a plurality of instruction registers, surrounding the core circuits to control the boundary scan circuits. However, additional time is necessary to determine the values of those registers. This increases the test time and test cost. Therefore, there is an urgent need to provide a test scheme to reduce the test time and cost effectively.
Furthermore, System-On-a-Chip has more advantages in terms of weight, volume, performance, and price than the conventional circuit board systems. If the testing scheme is not taken into consideration with system design, the test cost may exceed the manufacturing cost during mass production because the testing time is propositional to the circuit scale. Therefore, the test scheme for development of System-On-a-Chip is a main point during system design.

SUMMARY

Accordingly, the invention relates to a wrapper testing circuit of system-on-a-chip that substantially obviates one or more of the abovementioned problems resulting from the limitations and disadvantages of the related art.
In accordance with one embodiment, the wrapper testing circuit of system-on-a-chip for electrical tests of a core circuit of an integrated circuit includes a decoding logic having a signal encoding table for receiving a test signal and thereby issuing a control signal according to the encoding table; a plurality of Wrapper Boundary registers for temporarily storing the control signal and delivering the control to the core circuit; a bypass circuit for transferring the test signal; and an instruction register for temporarily storing the test signal and changing the data in the registers and the bypass circuit for testing the core circuit after the control signal is issued by the decoding logic.
In accordance with another embodiment, the wrapper testing circuit of system-on-a-chip for electrical tests of a core circuit of an integrated circuit includes a decoding logic having a signal encoding table for receiving a test signal and thereby issuing a control signal according to the encoding table; a plurality of Wrapper Boundary registers for temporarily storing the control signal and delivering control to the core circuit; a plurality of multiplexers for receiving the test signal and the control signal and outputting the control signal to the Wrapper Boundary register; a bypass circuit for transferring the test signal; and an instruction register for temporarily storing the test signal and changing the data in the registers and the bypass circuit for testing the core circuit after the control signal is issued by the decoding logic.
In accordance with another embodiment, the wrapper testing method of system-on-a-chip for electrical tests of a core circuit of an integrated circuit includes steps of providing an encoding table; inputting a test signal and thereby issuing a control signal according to the encoding table; storing the control signal temporarily and delivering the control signal to the core circuit; and storing the test signal temporarily and changing the test signal and the control signal stored temporarily for testing the core circuit after the control signal is issued.
The wrapper testing circuit in accordance with the invention provides an effective way to shorten test time, and thereby the test cost for SOC is reduced. Furthermore, the disclosed test scheme is compliant with P1500 standard.
In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the invention. It will be apparent, however, to one skilled in the art that the invention can be practiced without these specific details. In other instances, structures and devices are shown in block diagram form in order to avoid obscuring the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and other advantages of the invention will be more clearly understood from the following detailed description when taken in conjunction with the accompanying drawings, in which:
FIG. 1 illustrates the test scheme disclosed by IEEE P1500 standard;
FIG. 2 illustrates the test scheme for system-on-a-chip in accordance with the invention;
FIG. 3 illustrates another test scheme for system-on-a-chip in accordance with the invention; and
FIG. 4 illustrates the timing chart for system-on-a-chip in accordance with the invention.

DETAILED DESCRIPTION

Reference will now be made in greater detail to a preferred embodiment of the invention, an example of which is illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used throughout the drawings and the description to refer to the same or like parts. Reference in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment.
FIG. 2 illustrates the test scheme for system-on-a-chip in accordance with the invention. The test scheme utilizes a direct test mode to test the core circuit 20. The test circuit include registers 21˜24, multiplexers 25˜26, a bypass circuit 27, a wrapper instruction register 28, and decoding logic 29, whose operations and functions are given in detail as follows.
The decoding logic 29 has a signal encoding table, as shown in TABLE I, for receiving a test signal and outputting a control signal according to the signal encoding table as shown in TABLE I. The decoding logic 29 receives the test signals of TransferDR, ShiftWR, UpdateWR, and CaptureWR, and thereby decodes the control signals of Incore_ShiftWR, Incore_UpdateWR, Incore_CaptureWR for the registers 21˜24 after one clock. TransferDR, ShiftWR, UpdateWR, and CaptureWR are signal control lines for the peripheral circuits defined in P1500 standard, while Incore_ShiftWR, Incore_UpdateWR, Incore_CaptureWR are signal control lines after decoding.

Through the encoding table, the decoding logic 29 may reduce not only the instruction register quantity, but also the test time. It is known to those skilled in the art that the decoding logic 29 is composed of a plurality of logic gates, or an integrated circuit, in which the encoding is stored for encoding the test signal as the control signal.

TABLE I


					In-	In-	In-
Transfer	Shift	Update	Capture		Shift	Update	Capture
DR	WR	WR	WR	Instruction	WR	WR	WR	CL_WBY_MUX

0	0	0	0	Normal	0	0	0	0
0	0	0	1	Bypass	0	0	0	0
0	0	1	0	WCORETESTS	1	0	0	0
				scan in
0	0	1	1	WCORETESTS	0	1	1	1
				Execution
0	1	0	0	WCORETESTS	1	0	0	0
				scan out
0	1	0	1	WEXTEST	1	0	0	0
				scan in
0	1	1	0	WEXTEST	0	1	1	1
				Execution
0	1	1	1	WEXTEST	1	0	0	0
				Scan out

The registers 21˜24 store the control signals temporarily and deliver the control signals to the core circuit 20. The bypass circuit 27 delivers the test signals. The instruction register 28 stores the test signal temporarily and changes the data in the registers 21˜24 and the bypass circuit 27 for testing the core circuit after the decoding logic 29 issues the control signal.
The core circuit 20 has input ports and output ports (not shown in the figure). The registers 21˜24 are only for illustration and are not intended to limit the quantity. The registers 21˜24 are composed of a plurality of Wrapper Boundary Cells (WBC) corresponding to the input ports and output ports of the core circuit 20. The registers 21˜24 deliver the control signals. The multiplexer 25 connects to the registers 21 and 22, while the multiplexer 26 connects to the registers 23 and 24.
Refer to FIG. 3 illustrating another test scheme for system-on-a-chip in accordance with the invention. The test scheme utilizes fast test mode to test the core circuit 30.
The decoding logic 31 has a signal encoding table, as shown in TABLE I, for receiving a test signal and outputting a control signal according to the signal encoding table as shown in TABLE I. The decoding logic 31 receives the test signals of TransferDR, ShiftWR, UpdateWR, and CaptureWR, and thereby decodes the control signals of Incore_ShiftWR, Incore_UpdateWR, Incore_CaptureWR for the registers 32˜33 after one clock.
The test signals of TransferDR, ShiftWR, UpdateWR, and CaptureWR are delivered to the decoding logic 31 and the first multiplexer 34˜36, and the control signals of Incore_ShiftWR, Incore_UpdateWR, Incore_CaptureWR are thereby outputted after decoding for controlling the wrapper registers 32˜33. The clock signal WCRK provides the clocks necessary for the registers 32˜33, the instruction register 41, and the bypass circuit 42.
The wrapper register 32 connects to the second multiplexer 37, while the wrapper register 33 connects to the third multiplexer 38, which is connected to the fourth multiplexer 39. The test data is transferred to the multiplexer 40 and the core circuit 30 through TAM-in by TAM-source and TAM-sink of access mechanism, and the test results are outputted from TAM-out and delivered to the multiplexer 40, which then delivers the output signal TAM_sink. The test signal passes through the bypass circuit 37 and the control signal changes the data in the bypass circuit 37.
Refer to FIG. 4 illustrating the timing chart for system-on-a-chip in accordance with the invention. The difference between the invention and IEEE P1500 is seen in the figure. In IEEE P1500 standard, each instruction needs to finish three operations, which are scan in, execution, and scan out, while each operation is controlled by the three control lines: ShiftWR, UpdateWR, and CaptureWR. However, the values of these control lines are determined after WSI is inputted into the instruction register. Therefore, scan in, execution, and scan out need three clocks for operation. But through the decoding logic in accordance with the invention, only one clock is needed to determine the values of the control lines. Therefore, for more test patterns the test time is reduced. For each test pattern in this embodiment, six clocks are reduced.
A plurality of instruction registers are employed to store the test instructions in the prior art. If changing the test instructions, additional time is needed to modify the test instructions, so test time is wasted. The test scheme in accordance with the invention according to SoC standard defined by IEEE may reduce the test time.
According to the embodiment of the invention, all necessary control signals are established in a signal encoding table. Thus, all control signals are generated to all the wrapper circuits in one clock. In the prior art the signals are controlled by way of one hot i.e., step by step, while the test scheme of the invention controls the signals by way of synchronization.
In the test scheme of the prior art, the wrapper circuits are controlled by WSC (Wrapper Serial Control), in which one bit is controlled at one time. However, in the test scheme of the invention, multiple bits are controlled at one time. Sixteen instructions are generated at most after the test signals are decoded by the decoding logic. Compared with control by way of one bit, the test scheme of the invention reduces test time.
The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.

Claims

1. A wrapper testing circuit of system-on-a-chip for electrical tests of a core circuit of an integrated circuit, the core having input ports and output ports, the circuit comprising:

a decoding logic having a signal encoding table, for receiving a test signal and thereby

issuing a control signal according to the signal encoding table;

a plurality of Wrapper Boundary registers for temporarily storing the control signal and delivering the control to the core circuit;

a bypass circuit for transferring the test signal from the decoding logic; and

an instruction register for temporarily storing the test signal from the bypass circuit, and changing data in the Wrapper Boundary registers and the bypass circuit after the control signal is issued by the decoding logic, thereby testing the core circuit.

2. The wrapper testing circuit of claim 1, wherein the decoding logic issues the control signal in one clock after receiving the test signal.

3. The wrapper testing circuit of claim 1 further comprises a plurality of multiplexers connected to the plurality of Wrapper Boundary registers.

4. The wrapper testing circuit of claim 1, wherein the instruction register is a one-bit register.

5. A wrapper testing circuit of system-on-a-chip for electrical tests of a core circuit of a integrated circuit, the core having input ports and output ports, the circuit comprising:

a decoding logic having a signal encoding table, for receiving a test signal and thereby issuing a control signal according to the signal encoding table;

a plurality of first multiplexers for receiving the test signal and the control signal, and outputting the control signal to the Wrapper Boundary register;

a bypass circuit for transferring the test signal from the decoding logic; and

6. The wrapper testing circuit of claim 5, wherein the decoding logic issues the control signal in one clock after receiving the test signal.

7. The wrapper testing circuit of claim 5 further comprises a second multiplexer and a third multiplexer connected to the plurality of Wrapper Boundary registers respectively.

8. The wrapper testing circuit of claim 5, wherein the instruction register is a one-bit register.

9. A wrapper testing method of system-on-a-chip for electrical tests of a core circuit of a integrated circuit, the core having input ports and output ports, the method comprising steps of:

providing an encoding table;

inputting a test signal and thereby issuing a control signal according to the encoding table;

storing the control signal temporarily and delivering the control signal to the core circuit; and

storing the test signal temporarily and changing the test signal and the control signal stored temporarily for testing the core circuit after the control signal is issued.

10. The wrapper testing method of claim 9, wherein the control signal is outputted within one clock after the control signal is received.