+

US20060049464A1 - Semiconductor devices with graded dopant regions - Google Patents

Semiconductor devices with graded dopant regions Download PDF

Info

Publication number
US20060049464A1
US20060049464A1 US10/934,915 US93491504A US2006049464A1 US 20060049464 A1 US20060049464 A1 US 20060049464A1 US 93491504 A US93491504 A US 93491504A US 2006049464 A1 US2006049464 A1 US 2006049464A1
Authority
US
United States
Prior art keywords
dopant concentration
semiconductor device
graded
graded dopant
carrier movement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/934,915
Inventor
G.R. Mohan Rao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GREENTHREAD LLC
Original Assignee
GREENTHREAD LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=35995339&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=US20060049464(A1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Priority to US10/934,915 priority Critical patent/US20060049464A1/en
Application filed by GREENTHREAD LLC filed Critical GREENTHREAD LLC
Assigned to GREENTHREAD, LLC reassignment GREENTHREAD, LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: RAO, G.R. MOHAN
Publication of US20060049464A1 publication Critical patent/US20060049464A1/en
Priority to US11/622,496 priority patent/US8421195B2/en
Priority to US12/549,283 priority patent/US8106481B2/en
Priority to US13/854,319 priority patent/US20130221488A1/en
Priority to US14/515,584 priority patent/US9190502B2/en
Assigned to GREENTHREAD, LLC reassignment GREENTHREAD, LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: RAO, G.R. MOHAN
Priority to US14/931,636 priority patent/US9647070B2/en
Priority to US15/590,282 priority patent/US10510842B2/en
Priority to US16/717,950 priority patent/US10734481B2/en
Priority to US16/947,294 priority patent/US11121222B2/en
Priority to US17/371,839 priority patent/US11316014B2/en
Priority to US17/728,588 priority patent/US20220246725A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/60—Impurity distributions or concentrations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/18—Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/211—Design considerations for internal polarisation

Definitions

  • This present invention relates to all semiconductor devices and systems. Particularly it applies to diffused diodes, avalanche diodes, Schottky devices, power MOS transistors, JFET's, RF bipolar transistors, IGBTs (Insulated Gate Bipolar Transistors), varactors, digital VLSI, mixed signal circuits and sensor devices including camera ICs employing CCD (Charge Coupled Device) as well as CMOS technologies.
  • CCD Charge Coupled Device
  • BJT Bipolar Junction transistors
  • majority carriers also a small yet finite role in modulating the conductivity in BJTs. Consequently, both carriers (electrons and holes) play a role in the switching performance of BJTs.
  • the maximum frequency of operation in BJTs is limited by the base transit time as well as the quick recombination of the majority carriers when the device is switched off (prior to beginning the next cycle).
  • the dominant carrier mechanism in BJTs is carrier diffusion. Carrier drift current component is fairly small, especially in uniformly doped base BJTs. Efforts have been made in graded base transistors to create an ‘aiding drift field’, to enhance the diffusing minority carrier's speed from emitter to collector.
  • FIG. 1 shows the relative doping concentration versus distance in a BJT.
  • FIG. 2 shows the ‘uniformly doped epi region’ in a IGBT.
  • MOS devices are majority carrier devices for conduction. The conduction is channel dominated. The channel can be a surface in one plane in planar devices. The surface can also be on the sidewalls in a vertical device. Other device architectures to combine planar and vertical conductions are also possible.
  • the maximum frequency of operation is dictated primarily by source-drain separation distance. Most MOS devices use a uniformly doped substrate (or a well region). When a MOSFET is optimillay integrated with a BJT in a monolithic fashion, an IGBT results.
  • the IGBT inherits the advantages of both MOSFET and BJT. It also brings new challenges because the required characteristics (electron transit and hole recombination as fast as possible in the case of an n-channel IGBT) require different dopant gradients either in the same layer at different positions, or at the interfaces of similar or dissimilar layers.
  • FIG. 3 ( a ) shows a typical CMOS VLSI device employing a twin well substrate, on which active devices are subsequently fabricated.
  • FIGS. 3 ( b ), 3 ( c ), and 3 ( d ) illustrate device cross sections, as practiced today.
  • ‘Retrograde’ and ‘halo’ wells have also been attempted to improve refresh time in DRAM's (dynamic random access memories), as well as, reducing dark current (background noise) and enhance RGB (Red, Green, Blue) color resolution in digital camera Ics. Most of these techniques either divert the minority carriers away form the active regions of critical charge storage nodes at the surface, or, increase minority carrier density locally as the particular application requires.
  • FIG. 1 illustrates the relative doping profiles of emitter, base, and collector, for the two most popular bipolar junction transistors: namely, A—uniform base, and B—graded base;
  • FIG. 2 illustrates the cross section of a commercial IGBT with a uniform epitaxial drift region (base);
  • FIGS. 3 ( a ), 3 ( b ), 3 ( c ), 3 ( d ) illustrate cross sections commonly used CMOS silicon substrate with two wells (one n-well in which p-channel transistors are subsequently fabricated, and, one p-well in which n-channel transistors are subsequently fabricated)—typical IC, EEPROM using tunnel insulator, DRAM and NAND flash;
  • FIG. 4 illustrates the cross section of a IGBT, using one embodiment of the invention described here, where the dopant is optimally graded in the eptaxial drift region;
  • FIGS. 5 ( a ), 5 ( b ), 5 ( c ) illustrate the cross sections of a MOS silicon substrate with two wells, and, an underlying layer using embodiments of the invention to improve performance in each application—VLSI logic, DRAM/image IC, nonvolatile memory IC.
  • the relative doping concentrations of emitter and collector regions varies from 10 18 to 10 20 /cm 3 , where as the base region is 10 14 to 10 16 /cm 3 depending on the desired characteristics of the BJT.
  • the donor dopant concentration may be 10 to 100 ⁇ at the emitter-base junction, relative to the base-collector junction (1 ⁇ ).
  • the gradient can be linear, quasi linear, exponential or complimentary error function.
  • the relative slope of the donor concentration throughout the base creates a suitable aiding drift electric field, to help the holes (p-n-p transistor) transverse from emitter to collector.
  • cut-off frequency or, frequency at unity gain, f T
  • Similar performance improvements are also applicable to n-p-n transistors.
  • a donor gradient is established from the emitter-drift epitaxial base region junction of the punch-through IGBT, to the drift epitaxial base region—n t buffer layer boundary (electrons in this case are accelerated in their transit from emitter to collector).
  • the ‘average’ base resistance is optimized, so that conductivity modulation and lifetime (for minority carriers) in base region are not compromised.
  • drift region can also be a non-epitaxial silicon substrate. Epitaxy enhances lifetime, but, epitaxy is not mandatory. Different layers of dopan regions can be transferred through wafer to wafer bonding (or other similar transfer mechanisms) for eventual device fabrication.
  • the “reverse recovery time” for an IGBT is significantly improved due to the optimized graded dopant in the so called “drift region” as well as at the interfaces of the drift region.
  • Graded dopants can also be implemented in the n+ buffer layer as well as other regions adjacent to the respective layers. Two important performance enhancements are the result of dopant gradients. For example, in an n-channel IGBT, electrons can be swept from source to drain rapidly, while at the same time holes can be recombined closer to the n+ buffer layer. This can improve t(on) and t(off) in the same device.
  • donor gradient is also of benefit to very large scale integrated circuits (VLSI)—VLSI logic, DRAM, nonvolatile memory like NAND flash.
  • VLSI very large scale integrated circuits
  • Spurious minority carriers can be generated by clock switching in digital VLSI logic and memory IC'S. These unwanted carriers can discharge dynamically-held ‘actively held high’ nodes.
  • Statically held nodes (with V cc ) can not be affected, in most cases.
  • Degradation of refresh time in DRAM's is one of the results, because the capacitor holds charge dynamically.
  • degradation of CMOS digital images, in digital imaging IC's is another result of the havoc caused by minority carriers.
  • the subterrain n-layer has a graded donor concentration to sweep the minority carriers deep into the substrate.
  • One or more of such layers can also be implemented through wafer to wafer bonding or similar “transfer” mechanisms.
  • This n-layer can be a deeply-implanted layer. It can also be an epitaxial layer.
  • the n-well and p-well also can be graded or retrograded in dopants, as desired, to sweep those carriers away from the surface as well.
  • the graded dopant can also be implemented in surface channel MOS devices to accelerate majority carriers towards the drain. In nonvolatile memory devices, to decrease programming time, carriers should be accelerated towards the surface when programming of memory cells is executed.
  • the graded dopant can also be used to fabricate superior Junction field-effect transistors where the “channel pinchoff” is controlled by a graded channel instead of a uniformly doped channel (as practiced in prior art).

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

Most semiconductor devices manufactured today, have uniform dopant concentration, either in the lateral or vertical device active (and isolation) regions. By grading the dopant concentration, the performance in various semiconductor devices can be significantly improved. Performance improvements can be obtained in application specific areas like increase in frequency of operation for digital logic, various power MOSFET and IGBT ICS, improvement in refresh time for DRAM's, decrease in programming time for nonvolatile memory, better visual quality including pixel resolution and color sensitivity for imaging ICs, better sensitivity for varactors in tunable filters, higher drive capabilities for JFET's, and a host of other applications.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This application is not related to any pending application.
    • FIELD OF INVENTION
  • This present invention relates to all semiconductor devices and systems. Particularly it applies to diffused diodes, avalanche diodes, Schottky devices, power MOS transistors, JFET's, RF bipolar transistors, IGBTs (Insulated Gate Bipolar Transistors), varactors, digital VLSI, mixed signal circuits and sensor devices including camera ICs employing CCD (Charge Coupled Device) as well as CMOS technologies.
    • BACKGROUND OF INVENTION
  • Bipolar Junction transistors (BJT) are minority carrier devices as the principle device conduction mechanism. However, majority carriers also a small yet finite role in modulating the conductivity in BJTs. Consequently, both carriers (electrons and holes) play a role in the switching performance of BJTs. The maximum frequency of operation in BJTs is limited by the base transit time as well as the quick recombination of the majority carriers when the device is switched off (prior to beginning the next cycle). The dominant carrier mechanism in BJTs is carrier diffusion. Carrier drift current component is fairly small, especially in uniformly doped base BJTs. Efforts have been made in graded base transistors to create an ‘aiding drift field’, to enhance the diffusing minority carrier's speed from emitter to collector. However, most semiconductor devices, including various power MOSFETs (traditional, DMOS, lateral, vertical and a host of other configurations), IGBT's (Insulated Gated Base Transistors), still use a uniformly doped ‘drift epitaxial’ region in the base. FIG. 1 shows the relative doping concentration versus distance in a BJT. FIG. 2 shows the ‘uniformly doped epi region’ in a IGBT. In contrast to BJTs, MOS devices are majority carrier devices for conduction. The conduction is channel dominated. The channel can be a surface in one plane in planar devices. The surface can also be on the sidewalls in a vertical device. Other device architectures to combine planar and vertical conductions are also possible. The maximum frequency of operation is dictated primarily by source-drain separation distance. Most MOS devices use a uniformly doped substrate (or a well region). When a MOSFET is optimillay integrated with a BJT in a monolithic fashion, an IGBT results. The IGBT inherits the advantages of both MOSFET and BJT. It also brings new challenges because the required characteristics (electron transit and hole recombination as fast as possible in the case of an n-channel IGBT) require different dopant gradients either in the same layer at different positions, or at the interfaces of similar or dissimilar layers.
  • ‘Retrograde’ wells have been attempted, with little success, to help improve soft error immunity in SRAM's and visual quality in imaging circuits. FIG. 3(a) shows a typical CMOS VLSI device employing a twin well substrate, on which active devices are subsequently fabricated. FIGS. 3(b), 3(c), and 3(d) illustrate device cross sections, as practiced today. ‘Retrograde’ and ‘halo’ wells have also been attempted to improve refresh time in DRAM's (dynamic random access memories), as well as, reducing dark current (background noise) and enhance RGB (Red, Green, Blue) color resolution in digital camera Ics. Most of these techniques either divert the minority carriers away form the active regions of critical charge storage nodes at the surface, or, increase minority carrier density locally as the particular application requires.
    • BRIEF DESCRIPTION OF DRAWINGS
  • For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
  • FIG. 1 illustrates the relative doping profiles of emitter, base, and collector, for the two most popular bipolar junction transistors: namely, A—uniform base, and B—graded base;
  • FIG. 2 illustrates the cross section of a commercial IGBT with a uniform epitaxial drift region (base);
  • FIGS. 3(a), 3(b), 3(c), 3(d) illustrate cross sections commonly used CMOS silicon substrate with two wells (one n-well in which p-channel transistors are subsequently fabricated, and, one p-well in which n-channel transistors are subsequently fabricated)—typical IC, EEPROM using tunnel insulator, DRAM and NAND flash;
  • FIG. 4 illustrates the cross section of a IGBT, using one embodiment of the invention described here, where the dopant is optimally graded in the eptaxial drift region; and
  • FIGS. 5(a), 5(b), 5(c) illustrate the cross sections of a MOS silicon substrate with two wells, and, an underlying layer using embodiments of the invention to improve performance in each application—VLSI logic, DRAM/image IC, nonvolatile memory IC.
    • DETAILED DESCRIPTION OF THE INVENTION
  • The relative doping concentrations of emitter and collector regions varies from 1018 to 1020/cm3, where as the base region is 1014 to 1016/cm3 depending on the desired characteristics of the BJT. In graded base p-n-p transistors, the donor dopant concentration may be 10 to 100× at the emitter-base junction, relative to the base-collector junction (1×). The gradient can be linear, quasi linear, exponential or complimentary error function. The relative slope of the donor concentration throughout the base, creates a suitable aiding drift electric field, to help the holes (p-n-p transistor) transverse from emitter to collector. Since the aiding drift field helps hole conduction, the current gain at a given frequency is enhanced, relative to a uniformly-doped-(base) BJT. The improvement in cut-off frequency (or, frequency at unity gain, fT) can be as large as 2×-5×. Similar performance improvements are also applicable to n-p-n transistors.
  • As illustrated in FIG. 4, in one embodiment according to the invention, a donor gradient is established from the emitter-drift epitaxial base region junction of the punch-through IGBT, to the drift epitaxial base region—nt buffer layer boundary (electrons in this case are accelerated in their transit from emitter to collector). The ‘average’ base resistance is optimized, so that conductivity modulation and lifetime (for minority carriers) in base region are not compromised. By sweeping the carriers towards the nt buffer region two advantages are obtained—the frequency of operation (combination of ton and toff as is known in the IGBT commercial nomenclature) can be enhanced. More importantly, during toff, holes can be recombined much quicker at the nt buffer layer, compared to a uniformly doped n− epitaxial drift region by establishing a different dopant gradient near the n+ buffer layer. It should be noted that the drift region can also be a non-epitaxial silicon substrate. Epitaxy enhances lifetime, but, epitaxy is not mandatory. Different layers of dopan regions can be transferred through wafer to wafer bonding (or other similar transfer mechanisms) for eventual device fabrication. The “reverse recovery time” for an IGBT is significantly improved due to the optimized graded dopant in the so called “drift region” as well as at the interfaces of the drift region. Graded dopants can also be implemented in the n+ buffer layer as well as other regions adjacent to the respective layers. Two important performance enhancements are the result of dopant gradients. For example, in an n-channel IGBT, electrons can be swept from source to drain rapidly, while at the same time holes can be recombined closer to the n+ buffer layer. This can improve t(on) and t(off) in the same device.
  • As illustrated in FIGS. 5(a), 5(b), 5(c), donor gradient is also of benefit to very large scale integrated circuits (VLSI)—VLSI logic, DRAM, nonvolatile memory like NAND flash. Spurious minority carriers can be generated by clock switching in digital VLSI logic and memory IC'S. These unwanted carriers can discharge dynamically-held ‘actively held high’ nodes. Statically held nodes (with Vcc) can not be affected, in most cases. Degradation of refresh time in DRAM's is one of the results, because the capacitor holds charge dynamically. Similarly, degradation of CMOS digital images, in digital imaging IC's is another result of the havoc caused by minority carriers. Pixel and color resolution can be significantly enhanced in imaging IC's with the embodiments described here. Creating ‘Sub Terrain’ recombination centers underneath the wells (gold doping, platinum doping) as is done in some high-voltage diodes is not practical for VLSI circuits. Hence, a novel technique has been described here by creating a drift field to sweep these unwanted minority carriers into the substrate as quickly as possible, from the active circuitry at the surface. In a preferred embodiment, the subterrain n-layer has a graded donor concentration to sweep the minority carriers deep into the substrate. One or more of such layers can also be implemented through wafer to wafer bonding or similar “transfer” mechanisms. This n-layer can be a deeply-implanted layer. It can also be an epitaxial layer. The n-well and p-well also can be graded or retrograded in dopants, as desired, to sweep those carriers away from the surface as well. The graded dopant can also be implemented in surface channel MOS devices to accelerate majority carriers towards the drain. In nonvolatile memory devices, to decrease programming time, carriers should be accelerated towards the surface when programming of memory cells is executed. The graded dopant can also be used to fabricate superior Junction field-effect transistors where the “channel pinchoff” is controlled by a graded channel instead of a uniformly doped channel (as practiced in prior art).
  • One of ordinary skill and familiarity in the art will recognize that the concepts taught herein can be customized and tailored to a particular application in many advantageous ways. For instance, minority carriers can be channeled to the surface, to aid programming in nonvolatile memory devices (NOR, NAND, multivalued-cell). Moreover, single well, as well triple-well CMOS fabrication techniques can also be optimized to incorporate these embodiments, individually and collectively. Any modifications of such embodiments (described here) fall within the spirit and scope of the invention. Hence, they fall within the scope of the claims described below
  • Although the invention has been described with reference to specific embodiments, these descriptions are not meant to be construed in a limiting sense. Various modifications of the disclosed embodiments, as well as alternative embodiments of the invention will become apparent to persons skilled in the art upon reference to the description of the invention. It should be appreciated by those skilled in the art that the conception and the specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.
  • It is therefore, contemplated that the claims will cover any such modifications or embodiments that fall within the true scope of the invention.

Claims (9)

1. A semiconductor device with graded dopant concentration in the active region, to aid carrier movement from emitter to collector.
2. A semiconductor device with graded dopant concentration in the active region, to aid carrier movement from source to drain.
3. A semiconductor device with graded dopant concentration in the well regions, to aid carrier movement away from the active surface regions, towards the substrate.
4. A semiconductor device with graded dopant concentration in the substrate region to aid carrier movement away from the active surface regions, deeper towards the substrate.
5. A semiconductor device with at least one graded dopant concentration of donor or acceptor, to aid or impede carrier movement in selected regions in the monolithic die.
6. A semiconductor device with at least one each of dopant concentration of both donor and acceptor, to optimize the operating performance of the device.
7. A semiconductor device with at least one graded dopant concentration fabricated with ion implantation, to provide an aiding or retarding electric field locally in a monolithic integrated circuit.
8. A semiconductor device with at least one graded dopant concentration in an epitaxial layer.
9. A semiconductor device where one layer of dopant from one wafer, is transferred to another wafer having either same polarity or different polarity dopant through wafer bonding or similar processes.
US10/934,915 2004-09-03 2004-09-03 Semiconductor devices with graded dopant regions Abandoned US20060049464A1 (en)

Priority Applications (11)

Application Number Priority Date Filing Date Title
US10/934,915 US20060049464A1 (en) 2004-09-03 2004-09-03 Semiconductor devices with graded dopant regions
US11/622,496 US8421195B2 (en) 2004-09-03 2007-01-12 Semiconductor devices with graded dopant regions
US12/549,283 US8106481B2 (en) 2004-09-03 2009-08-27 Semiconductor devices with graded dopant regions
US13/854,319 US20130221488A1 (en) 2004-09-03 2013-04-01 Semiconductor devices with graded dopant regions
US14/515,584 US9190502B2 (en) 2004-09-03 2014-10-16 Semiconductor devices with graded dopant regions
US14/931,636 US9647070B2 (en) 2004-09-03 2015-11-03 Semiconductor devices with graded dopant regions
US15/590,282 US10510842B2 (en) 2004-09-03 2017-05-09 Semiconductor devices with graded dopant regions
US16/717,950 US10734481B2 (en) 2004-09-03 2019-12-17 Semiconductor devices with graded dopant regions
US16/947,294 US11121222B2 (en) 2004-09-03 2020-07-27 Semiconductor devices with graded dopant regions
US17/371,839 US11316014B2 (en) 2004-09-03 2021-07-09 Semiconductor devices with graded dopant regions
US17/728,588 US20220246725A1 (en) 2004-09-03 2022-04-25 Semiconductor devices with graded dopant regions

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/934,915 US20060049464A1 (en) 2004-09-03 2004-09-03 Semiconductor devices with graded dopant regions

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US11/622,496 Division US8421195B2 (en) 2004-09-03 2007-01-12 Semiconductor devices with graded dopant regions
US12/549,283 Continuation-In-Part US8106481B2 (en) 2004-09-03 2009-08-27 Semiconductor devices with graded dopant regions

Publications (1)

Publication Number Publication Date
US20060049464A1 true US20060049464A1 (en) 2006-03-09

Family

ID=35995339

Family Applications (10)

Application Number Title Priority Date Filing Date
US10/934,915 Abandoned US20060049464A1 (en) 2004-09-03 2004-09-03 Semiconductor devices with graded dopant regions
US11/622,496 Expired - Fee Related US8421195B2 (en) 2004-09-03 2007-01-12 Semiconductor devices with graded dopant regions
US13/854,319 Abandoned US20130221488A1 (en) 2004-09-03 2013-04-01 Semiconductor devices with graded dopant regions
US14/515,584 Expired - Lifetime US9190502B2 (en) 2004-09-03 2014-10-16 Semiconductor devices with graded dopant regions
US14/931,636 Expired - Fee Related US9647070B2 (en) 2004-09-03 2015-11-03 Semiconductor devices with graded dopant regions
US15/590,282 Expired - Lifetime US10510842B2 (en) 2004-09-03 2017-05-09 Semiconductor devices with graded dopant regions
US16/717,950 Expired - Lifetime US10734481B2 (en) 2004-09-03 2019-12-17 Semiconductor devices with graded dopant regions
US16/947,294 Expired - Fee Related US11121222B2 (en) 2004-09-03 2020-07-27 Semiconductor devices with graded dopant regions
US17/371,839 Expired - Lifetime US11316014B2 (en) 2004-09-03 2021-07-09 Semiconductor devices with graded dopant regions
US17/728,588 Abandoned US20220246725A1 (en) 2004-09-03 2022-04-25 Semiconductor devices with graded dopant regions

Family Applications After (9)

Application Number Title Priority Date Filing Date
US11/622,496 Expired - Fee Related US8421195B2 (en) 2004-09-03 2007-01-12 Semiconductor devices with graded dopant regions
US13/854,319 Abandoned US20130221488A1 (en) 2004-09-03 2013-04-01 Semiconductor devices with graded dopant regions
US14/515,584 Expired - Lifetime US9190502B2 (en) 2004-09-03 2014-10-16 Semiconductor devices with graded dopant regions
US14/931,636 Expired - Fee Related US9647070B2 (en) 2004-09-03 2015-11-03 Semiconductor devices with graded dopant regions
US15/590,282 Expired - Lifetime US10510842B2 (en) 2004-09-03 2017-05-09 Semiconductor devices with graded dopant regions
US16/717,950 Expired - Lifetime US10734481B2 (en) 2004-09-03 2019-12-17 Semiconductor devices with graded dopant regions
US16/947,294 Expired - Fee Related US11121222B2 (en) 2004-09-03 2020-07-27 Semiconductor devices with graded dopant regions
US17/371,839 Expired - Lifetime US11316014B2 (en) 2004-09-03 2021-07-09 Semiconductor devices with graded dopant regions
US17/728,588 Abandoned US20220246725A1 (en) 2004-09-03 2022-04-25 Semiconductor devices with graded dopant regions

Country Status (1)

Country Link
US (10) US20060049464A1 (en)

Cited By (61)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006019940B3 (en) * 2006-04-28 2007-12-27 Qimonda Ag Memory cell field of non volatile semiconductor memory cells, comprises semiconductor body with semiconductor zone of conductivity type, extending up to surface of body, where bit line is formed and buried in semiconductor zone
US20080087800A1 (en) * 2006-10-04 2008-04-17 Sony Corporation Solid-state image capturing device, image capturing device, and manufacturing method of solid-state image capturing device
US20080277717A1 (en) * 2007-05-10 2008-11-13 Qimonda Ag Minority carrier sink for a memory cell array comprising nonvolatile semiconductor memory cells
US20090224355A1 (en) * 2007-03-23 2009-09-10 Siliconix Technology C. V. Ir Semiconductor device with buffer layer
US20100032713A1 (en) * 2008-08-06 2010-02-11 Texas Instruments Incorporated Lateral insulated gate bipolar transistor
US20110074498A1 (en) * 2009-09-30 2011-03-31 Suvolta, Inc. Electronic Devices and Systems, and Methods for Making and Using the Same
US20110079861A1 (en) * 2009-09-30 2011-04-07 Lucian Shifren Advanced Transistors with Threshold Voltage Set Dopant Structures
US20110121404A1 (en) * 2009-09-30 2011-05-26 Lucian Shifren Advanced transistors with punch through suppression
US20110140176A1 (en) * 2009-12-10 2011-06-16 International Rectifier Corporation Monolithic integrated composite group III-V and group IV semiconductor device and method for fabricating same
US8377783B2 (en) 2010-09-30 2013-02-19 Suvolta, Inc. Method for reducing punch-through in a transistor device
US8400219B2 (en) 2011-03-24 2013-03-19 Suvolta, Inc. Analog circuits having improved transistors, and methods therefor
US8404551B2 (en) 2010-12-03 2013-03-26 Suvolta, Inc. Source/drain extension control for advanced transistors
US8461875B1 (en) 2011-02-18 2013-06-11 Suvolta, Inc. Digital circuits having improved transistors, and methods therefor
US8525271B2 (en) 2011-03-03 2013-09-03 Suvolta, Inc. Semiconductor structure with improved channel stack and method for fabrication thereof
US8530286B2 (en) 2010-04-12 2013-09-10 Suvolta, Inc. Low power semiconductor transistor structure and method of fabrication thereof
US8569156B1 (en) 2011-05-16 2013-10-29 Suvolta, Inc. Reducing or eliminating pre-amorphization in transistor manufacture
US8569128B2 (en) 2010-06-21 2013-10-29 Suvolta, Inc. Semiconductor structure and method of fabrication thereof with mixed metal types
US8599623B1 (en) 2011-12-23 2013-12-03 Suvolta, Inc. Circuits and methods for measuring circuit elements in an integrated circuit device
US8614128B1 (en) 2011-08-23 2013-12-24 Suvolta, Inc. CMOS structures and processes based on selective thinning
US8629016B1 (en) 2011-07-26 2014-01-14 Suvolta, Inc. Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer
US8637955B1 (en) 2012-08-31 2014-01-28 Suvolta, Inc. Semiconductor structure with reduced junction leakage and method of fabrication thereof
US8645878B1 (en) 2011-08-23 2014-02-04 Suvolta, Inc. Porting a circuit design from a first semiconductor process to a second semiconductor process
US8713511B1 (en) 2011-09-16 2014-04-29 Suvolta, Inc. Tools and methods for yield-aware semiconductor manufacturing process target generation
US8735987B1 (en) 2011-06-06 2014-05-27 Suvolta, Inc. CMOS gate stack structures and processes
US8748270B1 (en) 2011-03-30 2014-06-10 Suvolta, Inc. Process for manufacturing an improved analog transistor
US8748986B1 (en) 2011-08-05 2014-06-10 Suvolta, Inc. Electronic device with controlled threshold voltage
US8759872B2 (en) 2010-06-22 2014-06-24 Suvolta, Inc. Transistor with threshold voltage set notch and method of fabrication thereof
US8796048B1 (en) 2011-05-11 2014-08-05 Suvolta, Inc. Monitoring and measurement of thin film layers
US8811068B1 (en) 2011-05-13 2014-08-19 Suvolta, Inc. Integrated circuit devices and methods
US8816754B1 (en) 2012-11-02 2014-08-26 Suvolta, Inc. Body bias circuits and methods
US8819603B1 (en) 2011-12-15 2014-08-26 Suvolta, Inc. Memory circuits and methods of making and designing the same
US8863064B1 (en) 2012-03-23 2014-10-14 Suvolta, Inc. SRAM cell layout structure and devices therefrom
US8877619B1 (en) 2012-01-23 2014-11-04 Suvolta, Inc. Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom
US8883600B1 (en) 2011-12-22 2014-11-11 Suvolta, Inc. Transistor having reduced junction leakage and methods of forming thereof
US8895327B1 (en) 2011-12-09 2014-11-25 Suvolta, Inc. Tipless transistors, short-tip transistors, and methods and circuits therefor
US8970289B1 (en) 2012-01-23 2015-03-03 Suvolta, Inc. Circuits and devices for generating bi-directional body bias voltages, and methods therefor
US8976575B1 (en) 2013-08-29 2015-03-10 Suvolta, Inc. SRAM performance monitor
US8988153B1 (en) 2013-03-09 2015-03-24 Suvolta, Inc. Ring oscillator with NMOS or PMOS variation insensitivity
US8995204B2 (en) 2011-06-23 2015-03-31 Suvolta, Inc. Circuit devices and methods having adjustable transistor body bias
US8994415B1 (en) 2013-03-01 2015-03-31 Suvolta, Inc. Multiple VDD clock buffer
US8999861B1 (en) 2011-05-11 2015-04-07 Suvolta, Inc. Semiconductor structure with substitutional boron and method for fabrication thereof
US9041126B2 (en) 2012-09-21 2015-05-26 Mie Fujitsu Semiconductor Limited Deeply depleted MOS transistors having a screening layer and methods thereof
US9054219B1 (en) 2011-08-05 2015-06-09 Mie Fujitsu Semiconductor Limited Semiconductor devices having fin structures and fabrication methods thereof
US9070477B1 (en) 2012-12-12 2015-06-30 Mie Fujitsu Semiconductor Limited Bit interleaved low voltage static random access memory (SRAM) and related methods
US9093997B1 (en) 2012-11-15 2015-07-28 Mie Fujitsu Semiconductor Limited Slew based process and bias monitors and related methods
US9093550B1 (en) 2012-01-31 2015-07-28 Mie Fujitsu Semiconductor Limited Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same
US9112495B1 (en) 2013-03-15 2015-08-18 Mie Fujitsu Semiconductor Limited Integrated circuit device body bias circuits and methods
US9112484B1 (en) 2012-12-20 2015-08-18 Mie Fujitsu Semiconductor Limited Integrated circuit process and bias monitors and related methods
US9112057B1 (en) 2012-09-18 2015-08-18 Mie Fujitsu Semiconductor Limited Semiconductor devices with dopant migration suppression and method of fabrication thereof
US9236466B1 (en) 2011-10-07 2016-01-12 Mie Fujitsu Semiconductor Limited Analog circuits having improved insulated gate transistors, and methods therefor
US9268885B1 (en) 2013-02-28 2016-02-23 Mie Fujitsu Semiconductor Limited Integrated circuit device methods and models with predicted device metric variations
US9299801B1 (en) 2013-03-14 2016-03-29 Mie Fujitsu Semiconductor Limited Method for fabricating a transistor device with a tuned dopant profile
US9299698B2 (en) 2012-06-27 2016-03-29 Mie Fujitsu Semiconductor Limited Semiconductor structure with multiple transistors having various threshold voltages
US9319013B2 (en) 2014-08-19 2016-04-19 Mie Fujitsu Semiconductor Limited Operational amplifier input offset correction with transistor threshold voltage adjustment
US9406567B1 (en) 2012-02-28 2016-08-02 Mie Fujitsu Semiconductor Limited Method for fabricating multiple transistor devices on a substrate with varying threshold voltages
US9431068B2 (en) 2012-10-31 2016-08-30 Mie Fujitsu Semiconductor Limited Dynamic random access memory (DRAM) with low variation transistor peripheral circuits
US9449967B1 (en) 2013-03-15 2016-09-20 Fujitsu Semiconductor Limited Transistor array structure
US9478571B1 (en) 2013-05-24 2016-10-25 Mie Fujitsu Semiconductor Limited Buried channel deeply depleted channel transistor
US9710006B2 (en) 2014-07-25 2017-07-18 Mie Fujitsu Semiconductor Limited Power up body bias circuits and methods
TWI800105B (en) * 2020-11-23 2023-04-21 加拿大商萬國半導體國際有限合夥公司 Gas dopant doped deep trench super junction high voltage mosfet
US20250148983A1 (en) * 2023-11-06 2025-05-08 Canon Kabushiki Kaisha Light emitting device, display device, photoelectric conversion device, electronic apparatus, illumination device, and moving body

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060049464A1 (en) 2004-09-03 2006-03-09 Rao G R Mohan Semiconductor devices with graded dopant regions
US8598637B2 (en) * 2009-09-18 2013-12-03 Monolithic Power Systems, Inc. High voltage junction field effect transistor with spiral field plate
US9147690B2 (en) * 2012-03-08 2015-09-29 Ememory Technology Inc. Erasable programmable single-ploy nonvolatile memory
US8941167B2 (en) 2012-03-08 2015-01-27 Ememory Technology Inc. Erasable programmable single-ploy nonvolatile memory
US9379259B2 (en) * 2012-11-05 2016-06-28 International Business Machines Corporation Double layered transparent conductive oxide for reduced schottky barrier in photovoltaic devices
CN103151371A (en) * 2013-03-05 2013-06-12 矽力杰半导体技术(杭州)有限公司 Wafer structure and power device by using same
TWI514590B (en) * 2013-05-14 2015-12-21 Ememory Technology Inc Erasable programmable single-ploy nonvolatile memory
CN103441143B (en) * 2013-07-10 2015-09-09 电子科技大学 Latch-up resistant IGBT with variable composition mixed crystal emitter
KR20230013704A (en) 2021-07-19 2023-01-27 삼성전자주식회사 Image sensor

Citations (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4001864A (en) * 1976-01-30 1977-01-04 Gibbons James F Semiconductor p-n junction solar cell and method of manufacture
US4347654A (en) * 1980-06-18 1982-09-07 National Semiconductor Corporation Method of fabricating a high-frequency bipolar transistor structure utilizing permeation-etching
US4866000A (en) * 1987-09-16 1989-09-12 Oki Electric Industry Co., Ltd. Fabrication method for semiconductor integrated circuits
US5130262A (en) * 1989-12-26 1992-07-14 Masquelier Michael P Internal current limit and overvoltage protection method
US5213988A (en) * 1990-02-07 1993-05-25 Kabushiki Kaisha Toshiba Method of manufacturing bipolar transistor with self-aligned base regions
US5329144A (en) * 1993-04-23 1994-07-12 At&T Bell Laboratories Heterojunction bipolar transistor with a specific graded base structure
US5480816A (en) * 1992-02-17 1996-01-02 Mitsubishi Denki Kabushiki Kaisha Method of fabricating a bipolar transistor having a link base
US5496746A (en) * 1991-10-23 1996-03-05 Microsystems Engineering, Inc. Method for fabricating a bipolar junction transistor exhibiting improved beta and punch-through characteristics
US5569612A (en) * 1993-06-28 1996-10-29 Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno Process for manufacturing a bipolar power transistor having a high breakdown voltage
US5575862A (en) * 1993-11-30 1996-11-19 Canon Kabushiki Kaisha Polycrystalline silicon photoelectric conversion device and process for its production
US5797999A (en) * 1995-09-08 1998-08-25 Sharp Kabushiki Kaisha Solar cell and method for fabricating the same
US6211028B1 (en) * 1999-02-05 2001-04-03 Taiwan Semiconductor Manufacturing Company Twin current bipolar device with hi-lo base profile
USRE37441E1 (en) * 1982-08-24 2001-11-13 Semiconductor Energy Laboratory Co., Ltd. Photoelectric conversion device
US20020074585A1 (en) * 1988-05-17 2002-06-20 Advanced Power Technology, Inc., Delaware Corporation Self-aligned power MOSFET with enhanced base region
US6452086B1 (en) * 1998-10-05 2002-09-17 Astrium Gmbh Solar cell comprising a bypass diode
US6472715B1 (en) * 2000-09-28 2002-10-29 Lsi Logic Corporation Reduced soft error rate (SER) construction for integrated circuit structures
US6670544B2 (en) * 2000-12-08 2003-12-30 Daimlerchrysler Ag Silicon-germanium solar cell having a high power efficiency
US6683343B2 (en) * 2001-02-28 2004-01-27 Kabushiki Kaisha Toshiba High voltage semiconductor device having two buffer layer
US6696314B2 (en) * 2001-08-30 2004-02-24 Micron Technology, Inc. CMOS imager and method of formation
US6706550B2 (en) * 1998-06-27 2004-03-16 Hyundai Electronics Industries Co, Ltd. Photodiode having a plurality of PN injections and image sensor having the same
US6713813B2 (en) * 2001-01-30 2004-03-30 Fairchild Semiconductor Corporation Field effect transistor having a lateral depletion structure
US20040063288A1 (en) * 2002-09-18 2004-04-01 Danny Kenney System and method for reducing soft error rate utilizing customized epitaxial layers
US6737722B2 (en) * 2001-04-25 2004-05-18 Sanken Electric Co., Ltd. Lateral transistor having graded base region, semiconductor integrated circuit and fabrication method thereof
US6744117B2 (en) * 2002-02-28 2004-06-01 Motorola, Inc. High frequency semiconductor device and method of manufacture
US6747883B2 (en) * 2002-02-15 2004-06-08 Sony Corporation Switching power supply circuit
US6753202B2 (en) * 2001-05-03 2004-06-22 Texas Instruments Incorporated CMOS photodiode having reduced dark current and improved light sensitivity and responsivity
US6754093B2 (en) * 2002-06-06 2004-06-22 Integrated Device Technology, Inc. CAM circuit with radiation resistance
US6756616B2 (en) * 2001-08-30 2004-06-29 Micron Technology, Inc. CMOS imager and method of formation

Family Cites Families (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4078947A (en) * 1976-08-05 1978-03-14 International Business Machines Corporation Method for forming a narrow channel length MOS field effect transistor
US4160985A (en) * 1977-11-25 1979-07-10 Hewlett-Packard Company Photosensing arrays with improved spatial resolution
US4684971A (en) 1981-03-13 1987-08-04 American Telephone And Telegraph Company, At&T Bell Laboratories Ion implanted CMOS devices
US4481522A (en) * 1982-03-24 1984-11-06 Rca Corporation CCD Imagers with substrates having drift field
US4688063A (en) 1984-06-29 1987-08-18 International Business Machines Corporation Dynamic ram cell with MOS trench capacitor in CMOS
JPS6410656A (en) 1987-07-03 1989-01-13 Hitachi Ltd Complementary type semiconductor device
JPS6482563A (en) 1987-09-24 1989-03-28 Mitsubishi Electric Corp Semiconductor device
US4994887A (en) 1987-11-13 1991-02-19 Texas Instruments Incorporated High voltage merged bipolar/CMOS technology
US5262345A (en) 1990-01-25 1993-11-16 Analog Devices, Inc. Complimentary bipolar/CMOS fabrication method
US5029277A (en) * 1990-02-28 1991-07-02 Motorola, Inc. Optically compensated bipolar transistor
US5448087A (en) 1992-04-30 1995-09-05 Trw Inc. Heterojunction bipolar transistor with graded base doping
TW226478B (en) * 1992-12-04 1994-07-11 Semiconductor Energy Res Co Ltd Semiconductor device and method for manufacturing the same
US5532177A (en) * 1993-07-07 1996-07-02 Micron Display Technology Method for forming electron emitters
US5517052A (en) * 1994-06-24 1996-05-14 General Electric Company Deep-diffused phototransistor
JPH0897163A (en) * 1994-07-28 1996-04-12 Hitachi Ltd Semiconductor wafer manufacturing method, semiconductor wafer, semiconductor integrated circuit device manufacturing method, and semiconductor integrated circuit device
US5637898A (en) * 1995-12-22 1997-06-10 North Carolina State University Vertical field effect transistors having improved breakdown voltage capability and low on-state resistance
JP3958388B2 (en) * 1996-08-26 2007-08-15 株式会社ルネサステクノロジ Semiconductor device
EP0859457B1 (en) 1997-02-14 2003-08-27 Nippon Telegraph And Telephone Corporation A voltage controlled oscillator
KR100225411B1 (en) 1997-03-24 1999-10-15 김덕중 Ldmos transistor device and method of manufacturing the same
US5835402A (en) 1997-03-27 1998-11-10 Xilinx, Inc. Non-volatile storage for standard CMOS integrated circuits
JP3691963B2 (en) 1998-05-28 2005-09-07 株式会社東芝 Semiconductor device and manufacturing method thereof
US6310366B1 (en) 1999-06-16 2001-10-30 Micron Technology, Inc. Retrograde well structure for a CMOS imager
US6465862B1 (en) 1999-10-05 2002-10-15 Brannon Harris Method and apparatus for implementing efficient CMOS photo sensors
JP4164962B2 (en) 1999-10-08 2008-10-15 株式会社デンソー Insulated gate bipolar transistor
JP2001296599A (en) * 2000-04-12 2001-10-26 Olympus Optical Co Ltd Camera used for silver halide photography and also for electronic image pickup
US6743972B2 (en) * 2000-09-18 2004-06-01 Chris Macris Heat dissipating IC devices
JP5046452B2 (en) * 2000-10-26 2012-10-10 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
US6515740B2 (en) * 2000-11-09 2003-02-04 Canesta, Inc. Methods for CMOS-compatible three-dimensional image sensing using quantum efficiency modulation
AU2002230482A1 (en) * 2000-11-16 2002-05-27 Silicon Wireless Corporation Discrete and packaged power devices for radio frequency (rf) applications and methods of forming same
DE10062026A1 (en) 2000-12-13 2002-07-04 Siemens Ag Electronic switching device
JP2002305304A (en) 2001-04-05 2002-10-18 Toshiba Corp Power semiconductor device
DE10131705B4 (en) 2001-06-29 2010-03-18 Atmel Automotive Gmbh Method for producing a DMOS transistor
DE10131706B4 (en) 2001-06-29 2005-10-06 Atmel Germany Gmbh Method for producing a DMOS transistor
DE10131704A1 (en) 2001-06-29 2003-01-16 Atmel Germany Gmbh Method for doping a semiconductor body
JP2003051551A (en) 2001-08-03 2003-02-21 Hitachi Ltd Semiconductor device manufacturing method and semiconductor device
JP2003051184A (en) 2001-08-06 2003-02-21 Nec Corp Memory device
GB0119215D0 (en) * 2001-08-07 2001-09-26 Koninkl Philips Electronics Nv Trench bipolar transistor
AU2002349881A1 (en) * 2001-09-21 2003-04-01 Amberwave Systems Corporation Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
JP2003218356A (en) 2002-01-21 2003-07-31 Sony Corp Method for manufacturing and designing soi type semiconductor device, and soi type semiconductor device
DE10214066B4 (en) 2002-03-28 2007-02-01 Advanced Micro Devices, Inc., Sunnyvale Semiconductor device having a retrograde doping profile in a channel region and method of making the same
US6720622B1 (en) * 2002-07-05 2004-04-13 Taiwan Semiconductor Manufacturing Company SCR-ESD structures with shallow trench isolation
AU2003259111A1 (en) 2002-11-26 2004-06-18 Advanced Micro Devices, Inc. Retrograde channel doping to improve short channel effect
US6921946B2 (en) 2002-12-16 2005-07-26 Koninklijke Philips Electronics N.V. Test structure for electrical well-to-well overlay
US7285466B2 (en) * 2003-08-05 2007-10-23 Samsung Electronics Co., Ltd. Methods of forming metal oxide semiconductor (MOS) transistors having three dimensional channels
DE10345347A1 (en) 2003-09-19 2005-04-14 Atmel Germany Gmbh Method of making a lateral drift region dopant profile DMOS transistor
DE102004005948B4 (en) 2004-02-02 2009-04-02 Atmel Germany Gmbh MOS transistor and method of manufacturing a MOS transistor structure
US7238986B2 (en) * 2004-05-03 2007-07-03 Texas Instruments Incorporated Robust DEMOS transistors and method for making the same
US20060049464A1 (en) 2004-09-03 2006-03-09 Rao G R Mohan Semiconductor devices with graded dopant regions
US7115925B2 (en) 2005-01-14 2006-10-03 Omnivision Technologies, Inc. Image sensor and pixel having an optimized floating diffusion
US7307327B2 (en) 2005-08-04 2007-12-11 Micron Technology, Inc. Reduced crosstalk CMOS image sensors
US20070045682A1 (en) * 2005-08-31 2007-03-01 Hong Sungkwon C Imager with gradient doped EPI layer
DE102005042827A1 (en) 2005-09-09 2007-03-22 Atmel Germany Gmbh High-voltage FET with source drain gate and channel has doped drift region having potential barrier spaced from the body region
US20080142899A1 (en) 2006-08-04 2008-06-19 Silicon Space Technology Corporation Radiation immunity of integrated circuits using backside die contact and electrically conductive layers
US8164124B2 (en) 2007-04-04 2012-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. Photodiode with multi-epi films for image sensor
US8704292B2 (en) * 2010-02-23 2014-04-22 Donald R. Disney Vertical capacitive depletion field effect transistor
US8293629B2 (en) 2010-04-06 2012-10-23 Omnivision Technologies, Inc. High full-well capacity pixel with graded photodetector implant
KR101729717B1 (en) * 2010-08-31 2017-04-25 삼성디스플레이 주식회사 A mask for sealant hardening and the flat display device manufacturing method using the same
KR101798273B1 (en) * 2011-04-06 2017-11-15 에이비비 슈바이쯔 아게 Bipolar punch-through semiconductor device and method for manufacturing such a semiconductor device
US9331116B2 (en) 2014-01-15 2016-05-03 Omnivision Technologies, Inc. Back side illuminated single photon avalanche diode imaging sensor with high short wavelength detection efficiency

Patent Citations (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4001864A (en) * 1976-01-30 1977-01-04 Gibbons James F Semiconductor p-n junction solar cell and method of manufacture
US4347654A (en) * 1980-06-18 1982-09-07 National Semiconductor Corporation Method of fabricating a high-frequency bipolar transistor structure utilizing permeation-etching
USRE37441E1 (en) * 1982-08-24 2001-11-13 Semiconductor Energy Laboratory Co., Ltd. Photoelectric conversion device
US4866000A (en) * 1987-09-16 1989-09-12 Oki Electric Industry Co., Ltd. Fabrication method for semiconductor integrated circuits
US20020074585A1 (en) * 1988-05-17 2002-06-20 Advanced Power Technology, Inc., Delaware Corporation Self-aligned power MOSFET with enhanced base region
US5130262A (en) * 1989-12-26 1992-07-14 Masquelier Michael P Internal current limit and overvoltage protection method
US5213988A (en) * 1990-02-07 1993-05-25 Kabushiki Kaisha Toshiba Method of manufacturing bipolar transistor with self-aligned base regions
US5496746A (en) * 1991-10-23 1996-03-05 Microsystems Engineering, Inc. Method for fabricating a bipolar junction transistor exhibiting improved beta and punch-through characteristics
US5480816A (en) * 1992-02-17 1996-01-02 Mitsubishi Denki Kabushiki Kaisha Method of fabricating a bipolar transistor having a link base
US5329144A (en) * 1993-04-23 1994-07-12 At&T Bell Laboratories Heterojunction bipolar transistor with a specific graded base structure
US5569612A (en) * 1993-06-28 1996-10-29 Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno Process for manufacturing a bipolar power transistor having a high breakdown voltage
US5575862A (en) * 1993-11-30 1996-11-19 Canon Kabushiki Kaisha Polycrystalline silicon photoelectric conversion device and process for its production
US5797999A (en) * 1995-09-08 1998-08-25 Sharp Kabushiki Kaisha Solar cell and method for fabricating the same
US6706550B2 (en) * 1998-06-27 2004-03-16 Hyundai Electronics Industries Co, Ltd. Photodiode having a plurality of PN injections and image sensor having the same
US6452086B1 (en) * 1998-10-05 2002-09-17 Astrium Gmbh Solar cell comprising a bypass diode
US6211028B1 (en) * 1999-02-05 2001-04-03 Taiwan Semiconductor Manufacturing Company Twin current bipolar device with hi-lo base profile
US6472715B1 (en) * 2000-09-28 2002-10-29 Lsi Logic Corporation Reduced soft error rate (SER) construction for integrated circuit structures
US6670544B2 (en) * 2000-12-08 2003-12-30 Daimlerchrysler Ag Silicon-germanium solar cell having a high power efficiency
US6713813B2 (en) * 2001-01-30 2004-03-30 Fairchild Semiconductor Corporation Field effect transistor having a lateral depletion structure
US6683343B2 (en) * 2001-02-28 2004-01-27 Kabushiki Kaisha Toshiba High voltage semiconductor device having two buffer layer
US6737722B2 (en) * 2001-04-25 2004-05-18 Sanken Electric Co., Ltd. Lateral transistor having graded base region, semiconductor integrated circuit and fabrication method thereof
US6753202B2 (en) * 2001-05-03 2004-06-22 Texas Instruments Incorporated CMOS photodiode having reduced dark current and improved light sensitivity and responsivity
US6696314B2 (en) * 2001-08-30 2004-02-24 Micron Technology, Inc. CMOS imager and method of formation
US6756616B2 (en) * 2001-08-30 2004-06-29 Micron Technology, Inc. CMOS imager and method of formation
US6747883B2 (en) * 2002-02-15 2004-06-08 Sony Corporation Switching power supply circuit
US6744117B2 (en) * 2002-02-28 2004-06-01 Motorola, Inc. High frequency semiconductor device and method of manufacture
US6754093B2 (en) * 2002-06-06 2004-06-22 Integrated Device Technology, Inc. CAM circuit with radiation resistance
US20040063288A1 (en) * 2002-09-18 2004-04-01 Danny Kenney System and method for reducing soft error rate utilizing customized epitaxial layers

Cited By (138)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006019940B3 (en) * 2006-04-28 2007-12-27 Qimonda Ag Memory cell field of non volatile semiconductor memory cells, comprises semiconductor body with semiconductor zone of conductivity type, extending up to surface of body, where bit line is formed and buried in semiconductor zone
US8035067B2 (en) * 2006-10-04 2011-10-11 Sony Corporation Solid-state image capturing device, image capturing device, and manufacturing method of solid-state image capturing device
US20080087800A1 (en) * 2006-10-04 2008-04-17 Sony Corporation Solid-state image capturing device, image capturing device, and manufacturing method of solid-state image capturing device
US20090215220A1 (en) * 2006-10-04 2009-08-27 Sony Corporation Solid-state image capturing device, image capturing device, and manufacturing method of solid-state image capturing device
US7928352B2 (en) * 2006-10-04 2011-04-19 Sony Corporation Solid-state image capturing device, image capturing device, and manufacturing method of solid-state image capturing device
US20090224355A1 (en) * 2007-03-23 2009-09-10 Siliconix Technology C. V. Ir Semiconductor device with buffer layer
US8685849B2 (en) * 2007-03-23 2014-04-01 Siliconix Technology C. V. Ir Semiconductor device with buffer layer
US8274128B2 (en) * 2007-03-23 2012-09-25 Siliconix Technology C. V. Ir Semiconductor device with buffer layer
US20080277717A1 (en) * 2007-05-10 2008-11-13 Qimonda Ag Minority carrier sink for a memory cell array comprising nonvolatile semiconductor memory cells
US7755130B2 (en) 2007-05-10 2010-07-13 Qimonda Ag Minority carrier sink for a memory cell array comprising nonvolatile semiconductor memory cells
US20100032713A1 (en) * 2008-08-06 2010-02-11 Texas Instruments Incorporated Lateral insulated gate bipolar transistor
US10224244B2 (en) 2009-09-30 2019-03-05 Mie Fujitsu Semiconductor Limited Electronic devices and systems, and methods for making and using the same
US10217668B2 (en) 2009-09-30 2019-02-26 Mie Fujitsu Semiconductor Limited Electronic devices and systems, and methods for making and using the same
US20110121404A1 (en) * 2009-09-30 2011-05-26 Lucian Shifren Advanced transistors with punch through suppression
US8273617B2 (en) 2009-09-30 2012-09-25 Suvolta, Inc. Electronic devices and systems, and methods for making and using the same
US20110074498A1 (en) * 2009-09-30 2011-03-31 Suvolta, Inc. Electronic Devices and Systems, and Methods for Making and Using the Same
US9508800B2 (en) 2009-09-30 2016-11-29 Mie Fujitsu Semiconductor Limited Advanced transistors with punch through suppression
US20110079861A1 (en) * 2009-09-30 2011-04-07 Lucian Shifren Advanced Transistors with Threshold Voltage Set Dopant Structures
US8421162B2 (en) 2009-09-30 2013-04-16 Suvolta, Inc. Advanced transistors with punch through suppression
US9263523B2 (en) 2009-09-30 2016-02-16 Mie Fujitsu Semiconductor Limited Advanced transistors with punch through suppression
US8604527B2 (en) 2009-09-30 2013-12-10 Suvolta, Inc. Electronic devices and systems, and methods for making and using the same
US11062950B2 (en) 2009-09-30 2021-07-13 United Semiconductor Japan Co., Ltd. Electronic devices and systems, and methods for making and using the same
US8604530B2 (en) 2009-09-30 2013-12-10 Suvolta, Inc. Electronic devices and systems, and methods for making and using the same
US8541824B2 (en) 2009-09-30 2013-09-24 Suvolta, Inc. Electronic devices and systems, and methods for making and using the same
US11887895B2 (en) 2009-09-30 2024-01-30 United Semiconductor Japan Co., Ltd. Electronic devices and systems, and methods for making and using the same
US8975128B2 (en) 2009-09-30 2015-03-10 Suvolta, Inc. Electronic devices and systems, and methods for making and using the same
US10325986B2 (en) 2009-09-30 2019-06-18 Mie Fujitsu Semiconductor Limited Advanced transistors with punch through suppression
US10074568B2 (en) 2009-09-30 2018-09-11 Mie Fujitsu Semiconductor Limited Electronic devices and systems, and methods for making and using same
US20140008663A1 (en) * 2009-12-10 2014-01-09 International Rectifier Corporation Integrated Composite Group III-V and Group IV Semiconductor Device
US8530938B2 (en) * 2009-12-10 2013-09-10 International Rectifier Corporation Monolithic integrated composite group III-V and group IV semiconductor device and method for fabricating same
US20130337626A1 (en) * 2009-12-10 2013-12-19 International Rectifier Corporation Monolithic Group III-V and Group IV Device
US20110140176A1 (en) * 2009-12-10 2011-06-16 International Rectifier Corporation Monolithic integrated composite group III-V and group IV semiconductor device and method for fabricating same
US9496261B2 (en) 2010-04-12 2016-11-15 Mie Fujitsu Semiconductor Limited Low power semiconductor transistor structure and method of fabrication thereof
US8530286B2 (en) 2010-04-12 2013-09-10 Suvolta, Inc. Low power semiconductor transistor structure and method of fabrication thereof
US9865596B2 (en) 2010-04-12 2018-01-09 Mie Fujitsu Semiconductor Limited Low power semiconductor transistor structure and method of fabrication thereof
US8569128B2 (en) 2010-06-21 2013-10-29 Suvolta, Inc. Semiconductor structure and method of fabrication thereof with mixed metal types
US9224733B2 (en) 2010-06-21 2015-12-29 Mie Fujitsu Semiconductor Limited Semiconductor structure and method of fabrication thereof with mixed metal types
US8759872B2 (en) 2010-06-22 2014-06-24 Suvolta, Inc. Transistor with threshold voltage set notch and method of fabrication thereof
US9418987B2 (en) 2010-06-22 2016-08-16 Mie Fujitsu Semiconductor Limited Transistor with threshold voltage set notch and method of fabrication thereof
US9922977B2 (en) 2010-06-22 2018-03-20 Mie Fujitsu Semiconductor Limited Transistor with threshold voltage set notch and method of fabrication thereof
US8377783B2 (en) 2010-09-30 2013-02-19 Suvolta, Inc. Method for reducing punch-through in a transistor device
US8563384B2 (en) 2010-12-03 2013-10-22 Suvolta, Inc. Source/drain extension control for advanced transistors
US8404551B2 (en) 2010-12-03 2013-03-26 Suvolta, Inc. Source/drain extension control for advanced transistors
US9006843B2 (en) 2010-12-03 2015-04-14 Suvolta, Inc. Source/drain extension control for advanced transistors
US8686511B2 (en) 2010-12-03 2014-04-01 Suvolta, Inc. Source/drain extension control for advanced transistors
US8461875B1 (en) 2011-02-18 2013-06-11 Suvolta, Inc. Digital circuits having improved transistors, and methods therefor
US10250257B2 (en) 2011-02-18 2019-04-02 Mie Fujitsu Semiconductor Limited Digital circuits having improved transistors, and methods therefor
US9985631B2 (en) 2011-02-18 2018-05-29 Mie Fujitsu Semiconductor Limited Digital circuits having improved transistors, and methods therefor
US9184750B1 (en) 2011-02-18 2015-11-10 Mie Fujitsu Semiconductor Limited Digital circuits having improved transistors, and methods therefor
US9838012B2 (en) 2011-02-18 2017-12-05 Mie Fujitsu Semiconductor Limited Digital circuits having improved transistors, and methods therefor
US9680470B2 (en) 2011-02-18 2017-06-13 Mie Fujitsu Semiconductor Limited Digital circuits having improved transistors, and methods therefor
US9111785B2 (en) 2011-03-03 2015-08-18 Mie Fujitsu Semiconductor Limited Semiconductor structure with improved channel stack and method for fabrication thereof
US8525271B2 (en) 2011-03-03 2013-09-03 Suvolta, Inc. Semiconductor structure with improved channel stack and method for fabrication thereof
US9231541B2 (en) 2011-03-24 2016-01-05 Mie Fujitsu Semiconductor Limited Analog circuits having improved transistors, and methods therefor
US8847684B2 (en) 2011-03-24 2014-09-30 Suvolta, Inc. Analog circuits having improved transistors, and methods therefor
US8400219B2 (en) 2011-03-24 2013-03-19 Suvolta, Inc. Analog circuits having improved transistors, and methods therefor
US9093469B2 (en) 2011-03-30 2015-07-28 Mie Fujitsu Semiconductor Limited Analog transistor
US8748270B1 (en) 2011-03-30 2014-06-10 Suvolta, Inc. Process for manufacturing an improved analog transistor
US8999861B1 (en) 2011-05-11 2015-04-07 Suvolta, Inc. Semiconductor structure with substitutional boron and method for fabrication thereof
US8796048B1 (en) 2011-05-11 2014-08-05 Suvolta, Inc. Monitoring and measurement of thin film layers
US9362291B1 (en) 2011-05-13 2016-06-07 Mie Fujitsu Semiconductor Limited Integrated circuit devices and methods
US9966130B2 (en) 2011-05-13 2018-05-08 Mie Fujitsu Semiconductor Limited Integrated circuit devices and methods
US9741428B2 (en) 2011-05-13 2017-08-22 Mie Fujitsu Semiconductor Limited Integrated circuit devices and methods
US8811068B1 (en) 2011-05-13 2014-08-19 Suvolta, Inc. Integrated circuit devices and methods
US8569156B1 (en) 2011-05-16 2013-10-29 Suvolta, Inc. Reducing or eliminating pre-amorphization in transistor manufacture
US9793172B2 (en) 2011-05-16 2017-10-17 Mie Fujitsu Semiconductor Limited Reducing or eliminating pre-amorphization in transistor manufacture
US8937005B2 (en) 2011-05-16 2015-01-20 Suvolta, Inc. Reducing or eliminating pre-amorphization in transistor manufacture
US9514940B2 (en) 2011-05-16 2016-12-06 Mie Fujitsu Semiconductor Limited Reducing or eliminating pre-amorphization in transistor manufacture
US9281248B1 (en) 2011-06-06 2016-03-08 Mie Fujitsu Semiconductor Limited CMOS gate stack structures and processes
US9508728B2 (en) 2011-06-06 2016-11-29 Mie Fujitsu Semiconductor Limited CMOS gate stack structures and processes
US8735987B1 (en) 2011-06-06 2014-05-27 Suvolta, Inc. CMOS gate stack structures and processes
US8995204B2 (en) 2011-06-23 2015-03-31 Suvolta, Inc. Circuit devices and methods having adjustable transistor body bias
US8653604B1 (en) 2011-07-26 2014-02-18 Suvolta, Inc. Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer
US8629016B1 (en) 2011-07-26 2014-01-14 Suvolta, Inc. Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer
US8916937B1 (en) 2011-07-26 2014-12-23 Suvolta, Inc. Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer
US8748986B1 (en) 2011-08-05 2014-06-10 Suvolta, Inc. Electronic device with controlled threshold voltage
US8963249B1 (en) 2011-08-05 2015-02-24 Suvolta, Inc. Electronic device with controlled threshold voltage
US9054219B1 (en) 2011-08-05 2015-06-09 Mie Fujitsu Semiconductor Limited Semiconductor devices having fin structures and fabrication methods thereof
US8614128B1 (en) 2011-08-23 2013-12-24 Suvolta, Inc. CMOS structures and processes based on selective thinning
US9117746B1 (en) 2011-08-23 2015-08-25 Mie Fujitsu Semiconductor Limited Porting a circuit design from a first semiconductor process to a second semiconductor process
US8645878B1 (en) 2011-08-23 2014-02-04 Suvolta, Inc. Porting a circuit design from a first semiconductor process to a second semiconductor process
US9391076B1 (en) 2011-08-23 2016-07-12 Mie Fujitsu Semiconductor Limited CMOS structures and processes based on selective thinning
US8806395B1 (en) 2011-08-23 2014-08-12 Suvolta, Inc. Porting a circuit design from a first semiconductor process to a second semiconductor process
US8713511B1 (en) 2011-09-16 2014-04-29 Suvolta, Inc. Tools and methods for yield-aware semiconductor manufacturing process target generation
US9236466B1 (en) 2011-10-07 2016-01-12 Mie Fujitsu Semiconductor Limited Analog circuits having improved insulated gate transistors, and methods therefor
US9953974B2 (en) 2011-12-09 2018-04-24 Mie Fujitsu Semiconductor Limited Tipless transistors, short-tip transistors, and methods and circuits therefor
US11145647B2 (en) 2011-12-09 2021-10-12 United Semiconductor Japan Co., Ltd. Tipless transistors, short-tip transistors, and methods and circuits therefor
US8895327B1 (en) 2011-12-09 2014-11-25 Suvolta, Inc. Tipless transistors, short-tip transistors, and methods and circuits therefor
US9583484B2 (en) 2011-12-09 2017-02-28 Mie Fujitsu Semiconductor Limited Tipless transistors, short-tip transistors, and methods and circuits therefor
US10573644B2 (en) 2011-12-09 2020-02-25 Mie Fujitsu Semiconductor Limited Tipless transistors, short-tip transistors, and methods and circuits therefor
US9385121B1 (en) 2011-12-09 2016-07-05 Mie Fujitsu Semiconductor Limited Tipless transistors, short-tip transistors, and methods and circuits therefor
US8819603B1 (en) 2011-12-15 2014-08-26 Suvolta, Inc. Memory circuits and methods of making and designing the same
US9368624B2 (en) 2011-12-22 2016-06-14 Mie Fujitsu Semiconductor Limited Method for fabricating a transistor with reduced junction leakage current
US9196727B2 (en) 2011-12-22 2015-11-24 Mie Fujitsu Semiconductor Limited High uniformity screen and epitaxial layers for CMOS devices
US8883600B1 (en) 2011-12-22 2014-11-11 Suvolta, Inc. Transistor having reduced junction leakage and methods of forming thereof
US8599623B1 (en) 2011-12-23 2013-12-03 Suvolta, Inc. Circuits and methods for measuring circuit elements in an integrated circuit device
US9297850B1 (en) 2011-12-23 2016-03-29 Mie Fujitsu Semiconductor Limited Circuits and methods for measuring circuit elements in an integrated circuit device
US8970289B1 (en) 2012-01-23 2015-03-03 Suvolta, Inc. Circuits and devices for generating bi-directional body bias voltages, and methods therefor
US8877619B1 (en) 2012-01-23 2014-11-04 Suvolta, Inc. Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom
US9385047B2 (en) 2012-01-31 2016-07-05 Mie Fujitsu Semiconductor Limited Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same
US9093550B1 (en) 2012-01-31 2015-07-28 Mie Fujitsu Semiconductor Limited Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same
US9406567B1 (en) 2012-02-28 2016-08-02 Mie Fujitsu Semiconductor Limited Method for fabricating multiple transistor devices on a substrate with varying threshold voltages
US9424385B1 (en) 2012-03-23 2016-08-23 Mie Fujitsu Semiconductor Limited SRAM cell layout structure and devices therefrom
US8863064B1 (en) 2012-03-23 2014-10-14 Suvolta, Inc. SRAM cell layout structure and devices therefrom
US10217838B2 (en) 2012-06-27 2019-02-26 Mie Fujitsu Semiconductor Limited Semiconductor structure with multiple transistors having various threshold voltages
US9812550B2 (en) 2012-06-27 2017-11-07 Mie Fujitsu Semiconductor Limited Semiconductor structure with multiple transistors having various threshold voltages
US9299698B2 (en) 2012-06-27 2016-03-29 Mie Fujitsu Semiconductor Limited Semiconductor structure with multiple transistors having various threshold voltages
US10014387B2 (en) 2012-06-27 2018-07-03 Mie Fujitsu Semiconductor Limited Semiconductor structure with multiple transistors having various threshold voltages
US9105711B2 (en) 2012-08-31 2015-08-11 Mie Fujitsu Semiconductor Limited Semiconductor structure with reduced junction leakage and method of fabrication thereof
US8637955B1 (en) 2012-08-31 2014-01-28 Suvolta, Inc. Semiconductor structure with reduced junction leakage and method of fabrication thereof
US9112057B1 (en) 2012-09-18 2015-08-18 Mie Fujitsu Semiconductor Limited Semiconductor devices with dopant migration suppression and method of fabrication thereof
US9041126B2 (en) 2012-09-21 2015-05-26 Mie Fujitsu Semiconductor Limited Deeply depleted MOS transistors having a screening layer and methods thereof
US9431068B2 (en) 2012-10-31 2016-08-30 Mie Fujitsu Semiconductor Limited Dynamic random access memory (DRAM) with low variation transistor peripheral circuits
US8816754B1 (en) 2012-11-02 2014-08-26 Suvolta, Inc. Body bias circuits and methods
US9154123B1 (en) 2012-11-02 2015-10-06 Mie Fujitsu Semiconductor Limited Body bias circuits and methods
US9093997B1 (en) 2012-11-15 2015-07-28 Mie Fujitsu Semiconductor Limited Slew based process and bias monitors and related methods
US9319034B2 (en) 2012-11-15 2016-04-19 Mie Fujitsu Semiconductor Limited Slew based process and bias monitors and related methods
US9070477B1 (en) 2012-12-12 2015-06-30 Mie Fujitsu Semiconductor Limited Bit interleaved low voltage static random access memory (SRAM) and related methods
US9112484B1 (en) 2012-12-20 2015-08-18 Mie Fujitsu Semiconductor Limited Integrated circuit process and bias monitors and related methods
US9276561B2 (en) 2012-12-20 2016-03-01 Mie Fujitsu Semiconductor Limited Integrated circuit process and bias monitors and related methods
US9268885B1 (en) 2013-02-28 2016-02-23 Mie Fujitsu Semiconductor Limited Integrated circuit device methods and models with predicted device metric variations
US8994415B1 (en) 2013-03-01 2015-03-31 Suvolta, Inc. Multiple VDD clock buffer
US8988153B1 (en) 2013-03-09 2015-03-24 Suvolta, Inc. Ring oscillator with NMOS or PMOS variation insensitivity
US9299801B1 (en) 2013-03-14 2016-03-29 Mie Fujitsu Semiconductor Limited Method for fabricating a transistor device with a tuned dopant profile
US9893148B2 (en) 2013-03-14 2018-02-13 Mie Fujitsu Semiconductor Limited Method for fabricating a transistor device with a tuned dopant profile
US9577041B2 (en) 2013-03-14 2017-02-21 Mie Fujitsu Semiconductor Limited Method for fabricating a transistor device with a tuned dopant profile
US9112495B1 (en) 2013-03-15 2015-08-18 Mie Fujitsu Semiconductor Limited Integrated circuit device body bias circuits and methods
US9449967B1 (en) 2013-03-15 2016-09-20 Fujitsu Semiconductor Limited Transistor array structure
US9548086B2 (en) 2013-03-15 2017-01-17 Mie Fujitsu Semiconductor Limited Integrated circuit device body bias circuits and methods
US9853019B2 (en) 2013-03-15 2017-12-26 Mie Fujitsu Semiconductor Limited Integrated circuit device body bias circuits and methods
US9991300B2 (en) 2013-05-24 2018-06-05 Mie Fujitsu Semiconductor Limited Buried channel deeply depleted channel transistor
US9478571B1 (en) 2013-05-24 2016-10-25 Mie Fujitsu Semiconductor Limited Buried channel deeply depleted channel transistor
US9786703B2 (en) 2013-05-24 2017-10-10 Mie Fujitsu Semiconductor Limited Buried channel deeply depleted channel transistor
US8976575B1 (en) 2013-08-29 2015-03-10 Suvolta, Inc. SRAM performance monitor
US9710006B2 (en) 2014-07-25 2017-07-18 Mie Fujitsu Semiconductor Limited Power up body bias circuits and methods
US9319013B2 (en) 2014-08-19 2016-04-19 Mie Fujitsu Semiconductor Limited Operational amplifier input offset correction with transistor threshold voltage adjustment
TWI800105B (en) * 2020-11-23 2023-04-21 加拿大商萬國半導體國際有限合夥公司 Gas dopant doped deep trench super junction high voltage mosfet
US20250148983A1 (en) * 2023-11-06 2025-05-08 Canon Kabushiki Kaisha Light emitting device, display device, photoelectric conversion device, electronic apparatus, illumination device, and moving body

Also Published As

Publication number Publication date
US11316014B2 (en) 2022-04-26
US11121222B2 (en) 2021-09-14
US8421195B2 (en) 2013-04-16
US20220246725A1 (en) 2022-08-04
US20130221488A1 (en) 2013-08-29
US20070158790A1 (en) 2007-07-12
US20170243876A1 (en) 2017-08-24
US20160172447A1 (en) 2016-06-16
US9190502B2 (en) 2015-11-17
US20200127095A1 (en) 2020-04-23
US10734481B2 (en) 2020-08-04
US9647070B2 (en) 2017-05-09
US10510842B2 (en) 2019-12-17
US20210359086A1 (en) 2021-11-18
US20150035004A1 (en) 2015-02-05
US20210005716A1 (en) 2021-01-07

Similar Documents

Publication Publication Date Title
US11316014B2 (en) Semiconductor devices with graded dopant regions
US8106481B2 (en) Semiconductor devices with graded dopant regions
US8563986B2 (en) Power semiconductor devices having selectively doped JFET regions and related methods of forming such devices
US6713794B2 (en) Lateral semiconductor device
US5444272A (en) Three-terminal thyristor with single MOS-gate controlled characteristics
US20060145284A1 (en) Method for manufacturing semiconductor device
JP3469967B2 (en) Power device integrated structure
US5894139A (en) Semiconductor device structure for insulated gate bipolar transistor
US5498884A (en) MOS-controlled thyristor with current saturation characteristics
US5608238A (en) Semiconductor device having two insulated gates and capable of thyristor function and method for operating the same
GB2295052A (en) Integrated circuits
US7199403B2 (en) Semiconductor arrangement having a MOSFET structure and a zener device
US5723349A (en) Process for manufacturing a high conductivity insulated gate bipolar transistor integrater structure
Ueda et al. A new vertical double diffused MOSFET—the self-aligned terraced-gate MOSFET
US7211846B2 (en) Transistor having compensation zones enabling a low on-resistance and a high reverse voltage
US6881976B1 (en) Heterojunction BiCMOS semiconductor
US7808039B2 (en) SOI transistor with merged lateral bipolar transistor
JPH11195784A (en) Insulated gate semiconductor device
JP2594296B2 (en) Insulated gate field effect transistor
JP2629434B2 (en) Semiconductor device with anode short conductivity modulation type MISFET
JPH03145163A (en) thyristor
Al-Sa'di et al. RF NMOS switch with dedicated sinks for reduced leakage current
US20020179995A1 (en) Semiconductor component on an insulation layer
JPH022157A (en) semiconductor element
JPS62224066A (en) Semiconductor integrated circuit device

Legal Events

Date Code Title Description
AS Assignment

Owner name: GREENTHREAD, LLC, TEXAS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:RAO, G.R. MOHAN;REEL/FRAME:015998/0471

Effective date: 20041026

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION

AS Assignment

Owner name: GREENTHREAD, LLC, TEXAS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:RAO, G.R. MOHAN;REEL/FRAME:035630/0391

Effective date: 20150427

点击 这是indexloc提供的php浏览器服务，不要输入任何密码和下载