US20050269206A1

US20050269206A1 - Production method of wiring substrate having ultra-fine pattern, and wiring substrate

Info

Publication number: US20050269206A1
Application number: US11/144,732
Authority: US
Inventors: Shuichi Tanaka; Kazutaka Kobayashi
Original assignee: Shinko Electric Industries Co Ltd
Current assignee: Shinko Electric Industries Co Ltd
Priority date: 2004-06-07
Filing date: 2005-06-06
Publication date: 2005-12-08
Also published as: KR20060048174A; TW200607419A; JP2006024902A

Abstract

To produce a wiring substrate by employing a semi-additive method, the invention provides a production method of a wiring substrate, and a wiring substrate, that suppress the formation of undercut of an electrolytic copper plating layer during base etching and capable of ultra-fine wiring of a line/space size of 25/25 μm or below and further 10/10 μm or below. When producing a wiring substrate, the method of the invention includes the steps of applying electroless copper plating to a surface of a substrate made of a resin having an electric insulating property to form an electroless copper plating layer; applying a resist pattern exposing a portion for forming a wiring pattern on the surface of the electroless copper plating layer; plating metals different from copper or alloys containing at least one kind of the metals to the exposed portion to form an etching barrier plating layer; plating an etching barrier metal to form an etching barrier metal plating layer; applying electrolytic copper plating to the surface of the etching barrier metal plating layer to form wiring having a conductor layer including an electroless copper plating layer, the etching barrier metal plating layer and the electrolytic copper plating layer and the electrolytic copper plating layer; removing the resist pattern; and etching and removing the electroless copper plating layer exposed on the surface to form a wiring pattern.

Description

TECHNICAL FIELD

This invention relates to a production method of a wiring substrate having a wiring pattern that has an extremely fine wiring line/space size such as 25/25 μm or below, and the wiring substrate.

BACKGROUND ART

A semi-additive method has been employed as one of the methods for forming a fine pattern in a high density wiring substrate used for a semiconductor package (refer to Japanese Unexamined Patent Publication (Kokai) No. 2003-218516), for example). This method involves the steps of forming an electroless copper plating layer on a surface of a substrate made of an insulating resin, applying a resist for forming a pattern to the surface of the former, forming a pattern by electrolytic copper plating by using the electroless copper plating layer as a feed layer, removing the plating resist, and etching and removing the electroless copper plating layer to form a wiring pattern.
FIG. 8 shows production steps for forming a wiring substrate by the semi-additive method according to the prior art. FIG. 8A shows a substrate 1 made of an electrically insulating resin and FIG. 8B shows the state where an electroless copper plating layer (plating seed layer) 2 is formed by electroless copper plating on the surface of the substrate 1.
FIG. 8C shows the state where the electroless copper plating layer 2 is covered with a photosensitive plating resist (DFR: Dry Film Resist) 7 after the electroless copper plating layer 2 is formed.
FIG. 8D shows the state where the photosensitive plating resist 7 is exposed and developed and a resist pattern 7 a exposing a portion for forming a wiring pattern is formed on the surface of the electroless copper plating layer 2.
FIG. 8E shows the state where electrolytic copper plating is applied by using the electroless copper plating layer 2 as a feed layer, and the electrolytic copper plating layer 3 as a conductor layer is formed on the surface of the exposed electroless copper plating layer 2.
FIG. 8F shows the state where the plating resist is removed and the electroless copper plating layer 2 and the electrolytic copper plating layer 3 are exposed at the surface of the substrate 1.
Next, FIG. 8G shows the state where the portion of the electroless copper plating layer 2 exposed at the surface of the substrate 1 is etched away and an independent wiring pattern 9 of the electrolytic plating layer (conductor layer) 3 is formed.
The thickness of the electroless copper plating layer 2 functioning as the feed layer is far smaller than that of the electrolytic copper plating layer (conductor layer) 3. Therefore, when etching is carried out under the state shown in FIG. 8G, it is possible to selectively remove only the electroless copper plating layer 2 exposed on the surface of the substrate 1 and to leave only the electrolytic copper plating layer (conductor layer) 3.
As described above, after the electrolytic copper plating layer (conductor layer) 3 is formed, the portion of the electroless copper plating layer 2 exposed on the surface of the substrate 1 is etched and removed, that is, base etched, to form the independent wiring pattern 9. However, the electrolytic copper plating layer (conductor layer) forming the wiring pattern is allowed to adhere and is fixed to the substrate through the electroless copper plating layer and its adhesion becomes a problem in obtaining a stable wiring substrate.
FIGS. 9A and 9B show the state of base etching of the electroless copper plating layer by the conventional production method described above. FIG. 9A shows the state where the electrolytic copper plating layer (conductor layer) is formed and the plating resist is removed but base etching is not made. FIG. 9B shows the state after base etching is carried out. The widths of both electrolytic copper plating layer 3 and electroless copper plating layer 2 are decreased by base etching and the width a of the electroless copper plating layer adhering to the substrate is extremely small in comparison with the width w on the electrolytic copper plating layer before base etching, and so-called “undercut” 10 develops.
In other words, when the electroless copper plating layer exposed to the surface is etched (base etched) and removed, etching is carried out by spraying a copper etching solution to the surface of the substrate on which the electroless copper plating layer and the electrolytic copper plating layer are formed. Therefore, at corner portions defined by the substrate indicated by dashed line in FIG. 9B, the electroless copper plating layer and the electrolytic copper plating layer (conductor layer), in particular, the flow velocity of the etching solution is high and an etching rate becomes high, too. Consequently, the electrolytic copper plating layer and the electroless copper plating layer are integrally etched away and a large undercut 10 occurs.
Uniform etching of the entire surface of the substrate is difficult because in-plane variance exists during base etching in the flow of the etching solution and the thickness of the electroless copper plating. To reliably carry out etching, therefore, etching is generally carried out by shifting the etching condition to a more severe side, to a certain extent. For this reason, an undercut becomes large at positions where etching is excessive and wiring defects occur because the electrolytic copper plating layer (conductor layer) is not sufficiently brought into close contact with the substrate, thereby inviting peeling or disconnection and an eventual drop in production yield.
To prevent the wiring defects resulting from such undercut, a method has been employed that estimates in advance the undercut amount and increases the width of wires, but this problem renders a great obstacle for producing a wiring substrate having a ultra-fine pattern having extremely small line/space size such as 25/25 μm or below.

SUMMARY OF THE INVENTION

In view of the problems of the prior art technologies described above, the present invention provides a production method of a wiring substrate that suppresses the occurrence of undercut of an electrolytic copper plating layer (conductor layer) during base etching when a wiring substrate is produced by using a semi-additive method, and can achieve ultra-fine wiring having line/space size of 25/25 μm or below or further 20/10 μm or below, and the wiring substrate.
To accomplish the object described above, the invention employs the following constructions.
(1) The invention provides a production method of a wiring substrate comprising the steps of applying electroless copper plating to a surface of a substrate made of a resin having an electric insulating property to form an electroless copper plating layer; applying a resist pattern exposing a portion for forming a wiring pattern on the surface of the electroless copper plating layer; plating metals different from copper or alloys containing at least one kind of the metals to the exposed portion to form an etching barrier plating layer; applying electrolytic copper plating to the surface of the etching barrier plating layer to form an electrolytic copper plating layer; removing the resist pattern; and etching and removing the electroless copper plating layer exposed on the surface to form a wiring pattern.
(2) In the method described above, the etching barrier plating layer is suitably formed by plating a member selected from the group consisting of Ni, Sn, Co, Zn, In and Ag and alloys containing at least one kind of such metals.
(3) The invention also provides a production method of a wiring substrate comprising the steps of applying electroless copper plating to a surface of a substrate made of a resin having an electric insulating property to form an electroless copper plating layer; applying a resist pattern exposing a portion for forming a wiring pattern on the surface of the electroless copper plating layer; plating metals different from copper or alloys containing at least one kind of such metals to the exposed portion to form an etching barrier plating layer; alloying the metals or the alloys of the etching barrier plating layer and copper of the electroless copper plating layer to form an alloy layer; applying electrolytic copper plating to the surface of the alloy layer to form an electrolytic copper plating layer; removing the resist pattern; and etching and removing the electroless copper plating layer exposed on the surface to form the wiring pattern.
(4) In the method described above, the etching barrier plating layer is formed by plating a member selected from the group consisting of Sn, Zn and In and alloys containing at least one kind of such metals.
(5) The invention further provides a production method of a wiring substrate comprising the steps of applying electroless copper plating to a surface of a substrate made of a resin having an electric insulating property to form an electroless copper plating layer; applying a resist pattern exposing a portion for forming a wiring pattern on the surface of the electroless copper plating layer; conducting substitution plating for replacing copper of the electroless copper plating layer of the exposed portion by using metals different from copper of the electroless copper plating layer or alloys containing at least one kind of such metals to form an etching barrier substitution plating layer; applying electrolytic copper plating to the surface of the etching barrier substitution plating layer to form an electrolytic copper plating layer; removing the resist pattern; etching and removing the resist pattern exposed on the surface; and forming a wiring pattern.
(6) In the invention described above, the etching barrier substitution plating layer is suitably formed by substitution plating of a member selected from the group consisting of Sn, Ni, Co, Zn and Ag and alloys containing at least one kind of such metals.
(7) The invention further provides a wiring substrate having wiring formed into a pattern on a substrate made of a resin having an electric insulating property, wherein the wiring includes an electroless copper plating layer, an etching barrier plating layer formed of metals different from copper or alloys containing at least one kind of such metals and formed on the electroless copper plating layer, and an electrolytic copper plating layer formed on the etching barrier plating layer.
(8) In the wiring substrate described above, the etching barrier metal plating layer is suitably formed of a member selected from the group consisting of Ni, Sn, Co, Zn, In and Ag and alloys containing at least one kind of such metals.
(9) The invention further provides a wiring substrate having wiring formed into a pattern on a substrate made of a resin having an electric insulating property, wherein the wiring includes an alloy layer formed of an etching barrier metal of an alloy between copper and barrier metals different from copper or alloys containing at least one kind of such metals, and an electrolytic copper plating layer formed on said alloy layer.
(10) In the wiring substrate described above, the alloy layer is suitably formed of an alloy of copper and a member selected from the group consisting of Ni, Sn, Co, Zn and In and alloys containing at least one kind of such metals.
(11) The invention further provides a semiconductor wiring substrate having wiring formed into a pattern on a substrate made of a resin having an electric insulating property, wherein the wiring includes an etching barrier substitution plating layer formed of metals different from copper or alloys containing at least one kind of such metals, and an electrolytic copper plating layer formed on the etching barrier substitution layer.
(12) In the wiring substrate described above, the etching barrier substitution layer is suitably formed of a member selected from the group consisting of Sn, Ni, Co, Zn and Ag and alloys containing at least one kind of said metals.
When producing the wiring substrate, the method of the invention forms the wiring pattern by the steps of applying electroless copper plating to the surface of the substrate made of a resin having an electric insulating property to form an electroless copper plating layer; applying a resist pattern exposing a portion for forming the wiring pattern to the surface of the electroless copper plating layer; forming an etching barrier plating layer of metals different from copper or alloys containing at least one kind of such metals on the exposed electroless copper plating layer; applying electrolytic copper plating to this etching barrier plating layer to form an electrolytic copper layer operating as a conductor layer; removing the resist pattern; etching and removing the electroless electrolytic copper plating layer exposed on the surface, or in other words, conducting base etching; and forming the wiring pattern.
Because this etching barrier plating layer is constituted by metals different from copper or alloys containing at least one kind of such metals, the electroless copper plating layer exposed on the surface after the removal of the plating resist is hardly soluble in a base etching solution for etching away the electroless copper plating layer, operates as an etching barrier layer for at least the electrolytic copper plating layer and suppresses the occurrence of undercut.
The metal for forming the etching barrier plating layer or the alloy containing at least one kind of such a metal and copper of the electroless copper plating layer are alloyed to alloy the electroless copper plating layer and is made hardly soluble in the base etching solution. Therefore, the occurrence of undercut can be suppressed.
Because copper of the electroless copper plating layer is replaced by the etching barrier metals or the alloy containing at least one kind of such metals, the electroless copper plating layer can be replaced by the layer hardly soluble in the base etching solution. Therefore, the occurrence of undercut can be suppressed.
Because the method of the invention can suppress the occurrence of undercut as described above, it can also suppress the occurrence of the wiring defects of the wiring substrate and can improve the yield of the wiring. Therefore, the wiring substrate having a ultra-fine wiring having line/space size of 25/25 μm or below and further 10/10 μm or below can be efficiently produced. In the design of wiring, the occurrence margin of undercut can be decreased and freedom of the design width of the ultra-file wiring can be increased.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1H are explanatory views each showing a production step of a production method of a wiring substrate according to a first embodiment of the invention.
FIG. 2 is a schematic view showing a sectional structure of the wiring substrate obtained by the production method of the wiring substrate according to the first embodiment of the invention.
FIGS. 3A to 3E are explanatory views each showing a production step of a production method of a wiring substrate according to a second embodiment of the invention.
FIG. 4 is a schematic view showing a sectional structure of the wiring substrate obtained by the production method of the wiring substrate according to the second embodiment of the invention.
FIGS. 5A to 5E are explanatory views each showing a production step of a production method of a wiring substrate according to a third embodiment of the invention.
FIG. 6 is a schematic view showing a sectional structure of the wiring substrate obtained by the production method of the wiring substrate according to the third embodiment of the invention.
FIG. 7A shows a sectional structure of a wiring substrate of Example 1 of the invention.
FIG. 7B shows a sectional structure of a wiring substrate of Comparative Example.
FIGS. 8A to 8G are explanatory views each showing a production step of a production method of a wiring substrate according to the prior art.
FIG. 9A is a schematic view showing a sectional structure of the wiring substrate obtained by the production method of the wiring substrate according to the prior art and shows the state before base etching.
FIG. 9B is a schematic view showing a sectional structure of the wiring substrate obtained by the production method of the wiring substrate according to the prior art and shows the state after base etching.

THE MOST PREFERRED EMBODIMENT

Preferred embodiments of the invention will be explained in detail with reference to the accompanying drawings. FIGS. 1A to 1H are explanatory views each showing a production step of producing a wiring substrate according to a first embodiment of the invention.
FIG. 1A shows a substrate 1 made of an insulating resin having an electric insulating property.
FIG. 1B shows the state where an electroless copper plating layer 2 is formed as a seed layer by electroless copper plating on the surface of a substrate 1 made of an insulating resin having an electric insulating property. This electroless copper plating layer 2 operates also as a feed layer at the time of electrolytic plating that will be later described. The electroless copper layer can be formed by use of a known electroless copper plating bath and is generally formed to a thickness of 0.1 to 1 μm.
Incidentally, the substrate 1 in the invention includes also a build-up resin substrate that is obtained by forming a wiring pattern on an insulating substrate and further forms an electric insulating layer by a polyimide film or a polyphenylene ether resin for electrically insulating a wiring pattern on the substrate among the layers.
Examples of the insulating resin include known thermosetting resins such as an epoxy resin, a BT resin and a poyimide.
FIG. 1C shows the state where the surface of an electroless copper plating layer is covered with a photosensitive dry film resist (DFR) as a plating resist 7 for forming a wiring pattern. Incidentally, the plating resist is not particularly limited to this DFR and other plating resists can be used, too.
FIG. 1D shows the state where a resist pattern 7 a for forming the wiring pattern is formed on the substrate 1.
After the photosensitive resin film 7 is applied to the surface of the electroless copper plating layer, the plating resist pattern can be formed by conducting sensitization and development.
The surface of the electroless copper player layer is exposed at the portion for forming the wiring.
FIG. 1E shows the state where an etching barrier plating layer 4 is formed on the exposed electroless copper plating layer 2. This etching barrier plating layer 4 operates as an etching barrier during base etching for etching away the electroless copper plating layer at the portion at which the wiring is not formed in a subsequent step, and will be described later in detail.
FIG. 1F shows the state where the electrolytic copper plating layer 3 is formed on the etching barrier plating layer 4. The electrolytic copper plating layer 3 is formed by applying electrolytic copper plating by using the electroless copper plating layer as a feed layer and is generally formed to a thickness of 5 to 30 μm by electrolytic plating using a known electrolytic copper plating solution such as a copper sulfate plating solution or a copper pyrophosphate solution. The electrolytic copper plating layer 3 constitutes a main body of the wiring as a conductor layer.
FIG. 1G shows a state where the plating resist pattern is removed. In this state, the upper surface of the electroless copper plating layer 2 at the portion where the wiring is not formed, the upper surface of the electrolytic copper plating layer (conductor layer) 3 and its side surface and the side surface of the etching barrier plating layer 4 are exposed on the surface of the substrate 1.
FIG. 1H shows the state where the portion of the electroless plating layer 2 exposed on the surface of the substrate 1 is removed by etching (base etching) and an independent pattern 9 is formed. Known copper etching solutions such as a hydrogen peroxide/sulfuric acid solution can be used for the etching solution.
By the way, it is preferred to select metals of the etching barrier plating layer or alloys containing at least one kind of such metals in accordance with the etching solution used, as will be described later.
As the thickness of the electroless copper plating layer 2 is far smaller than that of the electrolytic copper layer (conductor layer) 3, it is possible to selectively remove only the electroless copper plating layer 2 exposed on the surface and to form the wiring pattern by conducting base etching in the state shown in FIG. 1G.
FIG. 2 schematically shows the sectional shape of the wiring substrate obtained by the production method of the embodiment described above. The occurrence of undercut of the electrolytic copper plating layer of the wiring substrate by the conventional production method shown in FIG. 9B can be almost completely suppressed and the occurrence of undercut of the electroless plating layer is extremely small. The width b of the bond surface between the substrate and the electroless copper plating layer can be remarkably increased in comparison with the width a of the bond surface between the substrate of the wiring substrate and the electroless copper plating layer by the conventional production method shown in FIG. 9(b).
According to the production method of the invention described above, the etching barrier plating layer 4 is formed between the electrolytic copper plating layer 3 and the electroless copper plating layer 2. Therefore, the occurrence of undercut of the electroless copper plating layer can be minimized during base etching.
Next, the etching barrier plating layer in the invention will be explained.
The etching barrier plating layer in the invention means the plating layer that is formed of the alloy containing those metals which are hardly soluble in the copper etching solution used for base etching of the electroless copper plating layer in the semi-additive method, or an alloy containing at least one kind of such metals, and is formed of metals different from copper or alloys containing at least one kind of such metals.
Copper etching solutions of a non-chloride type such as an ammonium persulfate solution, a hydrogen peroxide/sulfuric acid solution, an alkali etching solution containing copper ammonia complex ions, etc, are generally used as the copper etching solutions.
Generally, therefore, those metals which are difficult to dissolve in copper etching solutions such as Ni, Co, Sn, Zn, In, etc, or alloys containing at least one kind of these metals such as solder (Sn—Pb alloy), Ni—Co alloy and Sn—Zn alloy, are suitable as the metals of the etching barrier plating layer.
Incidentally, chloride type etching solutions such as cupric chloride and ferric chloride are used sometimes as the copper etching solution. However, as these chloride type etching solutions in some cases dissolve Ni and solder, the etching barrier plating layer is preferably formed by selecting metals and alloys other than Ni and solder, that is, those metals which do not dissolve in the etching solution or alloys of such metals when the chloride type etching solutions are used.
Besides these solutions, nitric acid type etching solutions may be used.
Further, Ag can also be used as a etching barrier plating layer when the copper etching solutions are appropriately selected.
The reason why this etching barrier plating layer suppresses the occurrence of undercut during base etching has not been clarified. It is assumed, however, that this layer plays the role of cutting off impingement of the etching layer against the electrolytic copper plating layer at a high speed and consequently suppresses undercut of the electrolytic copper plating layer, with the result of the prevention of the integral growth of the electrolytic copper plating layer and the electroless copper plating layer into large undercut as shown in FIG. 9B.
Though the thickness of the etching barrier plating layer is not particularly limited, this layer is preferably and ordinarily formed to a thickness of 0.1 to 1 μm in order to stably acquire the effect described above.
To form the etching barrier plating layer, either electrolytic plating or electroless plating may be employed. Known electrolytic plating and electroless plating baths may be selected and used in accordance with the kind of the metals of the etching barrier plating layer or the alloy containing at least one kind of such metals.
In the case of electrolytic plating, it is possible to employ NiSO₄.7H₂O-sulfonic acid bath and NiSO₄.7H₂O-sulfamic acid math for Ni, CoSO₄.7H₂O—NaCl—H₃BO₃bath and CoSO₄.7H₂O-pyrophosphoric acid-KCl bath for Co, SnSO₄—H₂SO₄-cresolsulfonic acid bath, Sn(BF₄)₂—HBF₄—H₃BO₃bath and SnSO₄-phenolsulfonic acid bath for Sn, ZnSO₄.7H₂O—NH₄Cl—Al₂(SO₄)₃.18H₂O-sodium acetate bath, ZnSO₄.7H₂O—NH₄Cl-sodium acetate glucose bath and Zn(BF₄)₂—NH₄Cl—NH₄BF₄bath for Zn, and In₂(SO₄)₃—Al₂(SO₄)₃.18H₂O—Na₂SO₄.10H₂O bath, In(BF₄)₃—NH₄BF₄—H₃BO₃bath and In₂(SO₄)₃-sodium tartrate dehydrate for In. In the case of solder (Sn—Pb alloy), it is possible to use Sn(BF₄)₂—Pb(BF₄)₂—HBF₄—H₃BO₃bath and PbSiF₆—SnSiF₆—H₂SiF₆bath. In the case of the Sn—Zn alloy, it is possible to use Na₂SnO₃—Na₂ZnO₂—NaOH bath. In the case of NiCo alloy, it is possible to use CoSO₄.7H₂O—NiSO₄.7H₂O—H₃BO₃—KCl bath. In the case of Ag, it is possible to use CH₃SO₃Ag bath.
As to electroless plating, it is possible to use acidic and neutral baths such as NiSO₄.6H₂O-sodium tartrate-propionic acid-sodium hypophosphite bath, NiCl₂.6H₂O-sodium acetate-sodium citrate-sodium succinate-diethylamineboran (DEAB)-methanol bath, nickel hypophosphite-sodium acetate-boric acid-ammonium sulfate bath, and so forth for Ni. In the case of Co, it is possible to use CoCl₂.6H₂O-sodium citrate-NH₄Cl-sodium hypophosphite bath and CoCl₂.6H₂O-ammonium citrate-sodium hypophosphite bath. In the case of Sn, it is possible to use SnCl₂.2H₂O-sodium citrate-EDTA.2Na-sodium nitrylotriacetate-TiCl₃bath. In the case of In, it is possible to use In₂(SO₄).9H₂O-EDT.2Na-triethanolamine-sodium borohydride bath. Incidentally, the plating bath is not limited to those described above.
Next, FIGS. 3A to 3E show the production steps of the production method according to the second embodiment of the invention. FIG. 3A shows the state where metals different from copper or an alloy containing at least one kind of such metals are plated to the exposed electroless copper plating layer 2 to form the etching barrier plating layer 4 in the same way as in FIG. 1E after the steps of FIGS. 1A to 1D are carried out. Next, FIG. 3B shows the state where the metal or alloy of the etching barrier plating layer 4 and copper of the electroless copper plating layer 2 are alloyed to form the alloy layer 5.
The etching barrier plating layer 4 can be formed by the same method as that of the first embodiment described above. Alloying of the metal or alloy of the etching barrier layer and copper of the electroless copper plating layer can be achieved by alloying copper of the base and the plating metal or by applying annealing, that is, by conducting heat-treatment at 80° C. for 30 minutes in air or in a N₂atmosphere, for example. Alloying can be executed, too, after the formation of the etching barrier plating layer and before the application of base etching.
FIG. 3C shows the state where the electrolytic plating layer 3 is formed on this alloy layer 5. The electrolytic copper plating layer 3 is formed by conducting electrolytic copper plating by using the electroless copper plating layer 2 and the alloy layer 5 as the feed layers. The electrolytic copper plating layer 3 is generally formed by conducting electrolytic plating by using a known electrolytic copper plating solution such as a copper sulfate plating solution or a copper pyrophosphate plating solution to a thickness of 5 to 30 μm. The electrolytic copper plating layer 3 constitutes the main body of the wiring as the conductor layer.
FIG. 3D shows the state where the plating resist pattern is removed. In this state, the upper surface of the electroless copper plating layer 2, the upper surface of the electrolytic copper plating layer 3 and its side surface and a part of the side surface of the alloy layer 5 of the metal or alloy of the etching barrier plating layer and copper of the electroless copper plating layer are exposed on the surface of the substrate 1.
Next, FIG. 3E shows the state where the electroless plating layer 2 exposed on the surface of the substrate 1 is removed by etching (base etching) and an independent wiring pattern 9 is formed. The same copper etching solution as that of the first embodiment can be used as the etching solution.
FIG. 4 schematically shows the sectional shape of the wiring substrate obtained by the second embodiment described above. It can be understood that undercut hardly occurs and the width c of the bond surface between the substrate and the alloy layer is far greater than the width a of the bond surface between the substrate of the wiring substrate and the electroless copper plating layer according to the conventional production method shown in FIG. 9B.
In this embodiment, copper of the electroless copper plating layer is alloyed with the metals of the etching barrier plating layer or with the alloy containing at least one kind of these metals, and becomes less soluble in the copper etching solution of base etching than at least copper, and the occurrence of an undercut can be suppressed.
Suitable examples of the metals that are different from copper or from the alloys containing at least one kind of these metals and are less soluble in the copper etching solution include Sn, Zn, In and solder (Sn—Pb alloy).
Incidentally, when the chloride type etching solution is used for the copper etching solution as described above, the etching barrier plating layer preferably uses metals and alloys other than Ni and solder.
The thickness of the etching barrier plating layer may be a thickness sufficient for alloying the electroless copper plating layer of the portion at which the wiring pattern is formed and is preferably from 0.1 to 1 μm. The electroless copper plating layer is preferably alloyed completely but even when it is not completely alloyed and a part remains as the electroless copper plating layer, the occurrence of undercut can be suppressed in the same way as in the first embodiment because the alloyed layer operates as the barrier to the etching solution.
Next, FIG. 5 shows the production method according to the third embodiment of the invention. FIG. 5A shows the state where the plating resist pattern is formed after the steps of FIGS. 1A to 1C are carried out. FIG. 5B shows the state where an etching barrier substitution plating layer 6 is formed at a portion of the exposed electroless copper plating layer 2. In other words, this embodiment substitutes metals different from copper or the alloy containing at least one kind of these metals substitutes for the electroless copper plating layer exposed on the surface by substitution plating, and the etching barrier substitution plating layer is formed on the substrate. The etching barrier substitution plating layer can be formed by electroless plating by using a copper substitution type plating bath of the metals different from copper or the alloy containing at least one kind of these metals.
FIG. 5C shows the state where the electrolytic copper plating layer 3 is formed on this etching barrier substitution plating layer 6.
The electrolytic copper plating layer 3 is formed by executing electrolytic copper plating by using the electroless copper plating layer and the substitution copper plating layer as the feed layers. Electrolytic plating is conducted by a known electrolytic copper solution such as a copper sulfate plating solution or a copper pyrophosphate plating solution in the same way as in the first and second embodiment. This plating layer is generally formed to a thickness of 5 to 30 μm. The electrolytic copper plating layer constitutes the main body of the wiring as the conductor layer.
FIG. 5D shows the state where the plating resist pattern is removed. In this state, the upper surface of the electroless copper player layer and the upper and side surfaces of the electrolytic copper plating layer constituting the conductor layer are exposed on the surface of the substrate 1.
FIG. 5E shows the state where the portion of the electroless copper plating layer 2 exposed on the surface of the substrate 1 is removed by etching (base etching) and an independent wiring pattern 9 is formed. The same copper etching solution as those of the foregoing embodiments can be used for the etching solution.
FIG. 6 schematically shows the sectional shape of the wiring substrate obtained by the third embodiment described above. It can be understood that undercut hardly occurs and the width d of the bond surface between the substrate and the substitution plating layer is by far greater than the width a of the bond surface between the substrate of the wiring substrate and the electroless copper plating layer according to the conventional production method shown in FIG. 9B.
In this embodiment, copper of the electroless copper plating layer is replaced by the etching barrier plating layer and is less soluble in the copper etching solution during base etching. Therefore, the occurrence of undercut can be suppressed.
Suitable examples of the metals different from copper or the alloys containing at least one kind of such metals, that replace copper of the electroless copper plating layer, are Sn, Zn, Co, Ni and Ni—B alloy.
The plating bath for substitution plating is a SnCl₂—CS(NH₂)₂—HCl bath or a SnCl₂—CS(NH₂)₂—H₂SO₄bath in the case of Sn, for example.
When the chloride type etching solution is used for the copper etching solution as described above, the etching barrier substitution plating layer is preferably formed by selecting metals or alloys other than solder, Ni and their alloys.
The thickness of the etching barrier substitution plating layer may be a thickness sufficient for substituting the electroless copper plating layer of the portion at which the wiring pattern is formed, and is preferably from 0.1 to 1 μm. The electroless copper plating layer is preferably substituted completely but even when it is not completely substituted and a part remains as the electroless copper plating layer, the occurrence of undercut can be suppressed in the same way as in the first and second embodiments because the substituted plating layer operates as the barrier to the copper etching solution.
According to the production method of the first embodiment described above, the wiring substrate having the wiring pattern including the electroless copper plating layer 2 on the substrate 1, the etching barrier plating layer 4 on the former 2 and the electrolytic copper plating layer 3 on the etching barrier plating layer 4 can be obtained.
This etching barrier plating layer is formed of the metals that are different from copper or from the alloys containing at least one kind of these metals, and is the layer less soluble in the copper etching solution. Suitable examples include Ni, Co, Sn, Zn, In, Ag and solder (Sn—Pb alloy), Sn—Zn alloy and Ni—Co alloy.
According to the production method of the second embodiment described above, the wiring substrate having the wiring pattern including the alloy layer 5, that is, the alloy layer formed of copper of the electroless copper plating layer and the metals or the alloy containing at least one kind of such metals of the etching barrier plating layer on the substrate 1, and the electrolytic copper plating layer 3 formed on this alloy layer can be obtained as shown in FIG. 4.
This etching barrier plating layer is suitably formed of Sn, Zn, In or the alloy containing at least one kind of these metals such as solder (Sn—Pb alloy) with copper.
According to the production method of the third embodiment described above, the wiring substrate having the wiring pattern including the substitution plating layer 6, that is, the alloy formed of copper of the electroless copper plating layer and the metals or the alloy containing at least one kind of such metals of the etching barrier substitution plating layer on the substrate 1, and the electrolytic copper plating layer 3 formed on this substitution plating layer can be obtained as shown in FIG. 6.
This etching barrier plating layer is suitably formed of Sn, Zn, Co, Ni, Ag or the alloy containing at least one kind of these metals.
As described above, in the wiring substrate produced by using the production method of the invention, undercut almost does not occur during base etching or is suppressed to an extremely small level. Therefore, the occurrence of wiring defects resulting from undercut such as peel and breakage of wires can be suppressed and the wiring substrate is the one that has high dimensional accuracy.

EXAMPLES

Example 1

An electroless copper plating layer is formed to a thickness of 0.5 μm by electroless copper plating on a surface of a polyimide insulating resin substrate. Next, a dry film resist is applied to the surface of this electroless copper plating layer and a plating resist pattern having a line space ratio of 8/8 μm is formed by conducting sensitization and development. Electrolytic Ni plating is then applied for one minute by using the electroless copper plating layer as a feed layer and a sulfamic acid bath to form a 0.2 to 0.3 μm-thick electrolytic Ni plating layer as an etching barrier metal plating layer. Next, electrolytic copper plating is applied by using a copper sulfate bath and a 20 μm-thick electrolytic copper plating layer is formed to obtain a wiring pattern. The plating resist is thereafter removed and base etching is carried out by using a hydrogen peroxide/sulfuric acid type etching solution to etch away at least the electroless copper plating layer not having the wiring pattern formed thereon and to produce a wiring substrate. FIG. 7A shows a photo of a sectional shape of the resulting wiring substrate.

Comparative Example

A wiring substrate is produced in this Comparative Example by using the prior art method without disposing the etching barrier metal layer of the invention. In other words, an electroless copper plating layer is formed to a thickness of 0.5 μm by electroless copper plating on a surface of a polyimide insulating resin substrate in the same way as in Example 1. Next, a dry film resist is applied to the surface of this electroless copper plating layer and a plating resist pattern having a line space ratio of 8/8 μm is formed by conducting sensitization and development. Next, electrolytic copper plating is applied by using a copper sulfate bath and a 15 μm-thick electrolytic copper plating layer is formed to obtain a wiring pattern. The plating resist is thereafter removed and base etching is carried out by using a hydrogen peroxide/sulfuric acid type etching solution to etch away at least the electroless copper plating layer not having the wiring pattern formed thereon and to produce a wiring substrate. FIG. 7B shows a photo of a sectional shape of the resulting wiring substrate.
It can be understood from FIGS. 7A and 7B that a large undercut occurs in the case of Comparative Example, the adhesion surface with the substrate is small, and the possibility of peel is observed in many portions. In contrast, in Example of the invention, undercut is not observed or is extremely small even when observed, and wiring with ultra-fine wires can be stably obtained.

Example 2

An electroless copper plating layer is formed to a thickness of 0.5 μm by electroless copper plating on a surface of a polyimide insulating resin substrate. Next, a dry film resist is applied to the surface of this electroless copper plating layer and a plating resist pattern having a line space ratio of 8/8 μm is formed by conducting sensitization and development. Electrolytic Sn plating is then applied for one minute by using the electroless copper plating layer as a feed layer and a methanesulfonic acid bath to form a 0.2 μm-thick electrolytic Sn plating layer as an etching barrier metal plating layer. Next, annealing is carried out at 80° C. for 30 minutes in the atmosphere to convert the electroless copper plating layer to an alloy layer of copper and Sn. Electrolytic copper plating is applied by using a copper sulfate bath and a 20 μm-thick electrolytic copper plating layer is formed to obtain a wiring pattern. The plating resist is thereafter removed and base etching is carried out by using a hydrogen peroxide/sulfuric acid-type etching solution to etch away at least the electroless copper plating layer not having the wiring pattern formed thereon and to produce a wiring substrate. When the section of the resulting wiring substrate is observed, the occurrence of undercut is hardly observed in the same way as in Example 1.

Example 3

An electroless copper plating layer is formed to a thickness of 0.5 μm by electroless copper plating on a surface of a polyimide insulating resin substrate. Next, a dry film resist is applied to the surface of this electroless copper plating layer and a plating resist pattern having a line space ratio of 8/8 μm is formed by conducting sensitization and development. An electroless copper plating layer is allowed to replace Sn by electroless plating and a 0.5 μm-thick Sn substitution plating layer is formed.
Next, electrolytic copper plating is applied by using this electroless copper plating layer as a feed layer and a copper sulfate bath to form a 20 μm-thick electrolytic copper plating layer. The plating resist is thereafter removed and base etching is carried out by using a hydrogen peroxide/sulfuric acid type etching solution to etch away at least the electroless copper plating layer not having the wiring pattern formed thereon and to produce a wiring substrate.
When the section of the resulting wiring substrate is observed, the occurrence of undercut is hardly observed in the same way as in Example 1.
Although the production method of the wiring substrate and the wiring substrate according to the invention have thus been explained, the invention can be applied to the formation of the wiring patterns by the semi-additive method, such as a chip-size package, besides the build-up wiring substrate.

Claims

1. A production method of a wiring substrate comprising the steps of:

applying electroless copper plating to a surface of a substrate made of a resin having an electric insulating property to form an electroless copper plating layer;

applying a resist pattern exposing a portion for forming a wiring pattern on the surface of said electroless copper plating layer;

plating metals different from copper or alloys containing at least one kind of said metals to said exposed portion to form an etching barrier plating layer;

applying electrolytic copper plating to the surface of said etching barrier plating layer to form an electrolytic copper plating layer;

removing said resist pattern; and

etching and removing said electroless copper plating layer exposed on the surface to form a wiring pattern.

2. A production method of a wiring substrate according to claim 1, wherein said etching barrier plating layer is formed of a member selected from the group consisting of Ni, Sn, Co, Zn, In and Ag and alloys containing at least one kind of said metals.

3. A production method of a wiring substrate comprising the steps of:

alloying said metals or said alloys of said etching barrier plating layer and copper of said electroless copper plating layer to form an alloy layer;

applying electrolytic copper plating to the surface of said alloy layer to form an electrolytic copper plating layer;

removing said resist pattern; and

4. A production method of a wiring substrate according to claim 3, wherein said etching barrier plating layer is formed of a member selected from the group consisting of Sn, Zn and In and alloys containing at least one kind of said metals.

5. A production method of a wiring substrate comprising the steps of:

conducting substitution plating for replacing copper of said electroless copper plating layer of said exposed portion by using metals different from copper of said electroless copper plating layer or alloys containing at least one kind of said metals to form an etching barrier substitution plating layer;

applying electrolytic copper plating to the surface of said etching barrier substitution plating layer to form an electrolytic copper plating layer;

removing said resist pattern;

etching and removing said electroless copper plating layer exposed on the surface; and

forming said wiring pattern.

6. A production method of a wiring substrate according to claim 5, wherein said etching barrier substitution plating layer is formed of a member selected from the group consisting of Sn, Ni, Co, Zn and Ag and alloys containing at least one kind of said metals.

7. A wiring substrate having wiring formed into a pattern on a substrate made of a resin having an electric insulating property, wherein said wiring includes an electroless copper plating layer, an etching barrier plating layer formed by metals different from copper or alloys containing at least one kind of said metals on said electroless copper plating layer, and an electrolytic copper plating layer formed on said etching barrier plating layer.

8. A wiring substrate according to claim 7, wherein said etching barrier metal plating layer is formed of a member selected from the group consisting of Ni, Sn, Co, Zn, In and Ag and alloys containing at least one kind of said metals.

9. A wiring substrate having wiring formed into a pattern on a substrate made of a resin having an electric insulating property, wherein said wiring includes an alloy layer of an alloy between copper and metals different from copper or alloys containing at least one kind of said metals, and an electrolytic copper plating layer formed on said alloy layer.

10. A wiring substrate according to claim 9, wherein said alloy layer is formed of an alloy of copper and a member selected from the group consisting of Ni, Sn, Co, Zn and In and alloys containing at least one kind of said metals.

11. A semiconductor wiring substrate having wiring formed into a pattern on a substrate made of a resin having an electric insulating property, wherein said wiring includes an etching barrier substitution plating layer formed of metals different from copper or alloys containing at least one kind of said metals, and an electrolytic copper plating layer formed on said etching barrier substitution layer.

12. A wiring substrate according to claim 11, wherein said etching barrier substitution plating layer is formed of a member selected from the group consisting of Sn, Ni, Co, Zn, and Ag and alloys containing at least one kind of said metals.