US20050178505A1 - Electrode for dry etching a wafer - Google Patents
Electrode for dry etching a wafer Download PDFInfo
- Publication number
- US20050178505A1 US20050178505A1 US10/506,558 US50655804A US2005178505A1 US 20050178505 A1 US20050178505 A1 US 20050178505A1 US 50655804 A US50655804 A US 50655804A US 2005178505 A1 US2005178505 A1 US 2005178505A1
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- electrode
- semiconductor wafer
- protrusion
- edge
- wafer
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- 238000001312 dry etching Methods 0.000 title claims abstract description 27
- 239000000463 material Substances 0.000 claims description 23
- 239000011810 insulating material Substances 0.000 claims description 5
- 238000009413 insulation Methods 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 description 79
- 238000005530 etching Methods 0.000 description 19
- 239000007789 gas Substances 0.000 description 17
- 238000000034 method Methods 0.000 description 16
- 230000008569 process Effects 0.000 description 15
- 229920002120 photoresistant polymer Polymers 0.000 description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 12
- 238000001039 wet etching Methods 0.000 description 12
- 150000004767 nitrides Chemical class 0.000 description 11
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- VZGDMQKNWNREIO-UHFFFAOYSA-N tetrachloromethane Chemical compound ClC(Cl)(Cl)Cl VZGDMQKNWNREIO-UHFFFAOYSA-N 0.000 description 4
- 238000005406 washing Methods 0.000 description 4
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000005672 electromagnetic field Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910001936 tantalum oxide Inorganic materials 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000003504 photosensitizing agent Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- 229910015844 BCl3 Inorganic materials 0.000 description 1
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910020487 SiO3/2 Inorganic materials 0.000 description 1
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 1
- 229910003071 TaON Inorganic materials 0.000 description 1
- 239000004809 Teflon Substances 0.000 description 1
- 229920006362 Teflon® Polymers 0.000 description 1
- 229910008486 TiSix Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- RWRIWBAIICGTTQ-UHFFFAOYSA-N difluoromethane Chemical compound FCF RWRIWBAIICGTTQ-UHFFFAOYSA-N 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32532—Electrodes
- H01J37/32541—Shape
Definitions
- the present invention relates to a dry etching of a semiconductor wafer, and more particularly to an electrode for dry etching a semiconductor wafer using plasma, thereby removing foreign material deposited on the edge of the semiconductor wafer for manufactuing integrated circuit chips.
- multiple layers 110 and 120 such as a poly-silicon layer, a nitride layer, a metal layer, etc. are deposited and accumulated on the edge of a semiconductor wafer 100 , as shown in FIG. 5 . Further, as shown in FIG. 6 , particles broken off the deposited layers on the edge of the semiconductor wafer 100 are generated while transferring the semiconductor wafer 100 or by equipment 200 , and introduced into the central portion of the semiconductor wafer 100 , thereby contaminating the integrated circuit chips.
- a gate electrode of a semiconductor chip has been recently changed from tungsten silicide to tungsten, and an insulation layer of a capacitor has been changed from an ONO (oxide-nitride-oxide) structure to tantalum oxide.
- An organic bottom anti-reflective coating (hereinafter, referred to as ARC) layer and an inorganic ARC layer such as SiON have been recently used to form fine photoresist patterns, and Ti and TiN layers have been used as a barrier metal layer. Therefore, these materials contaminate the semiconductor wafer by the aforementioned route during fabrication.
- these materials act as a particle source during fabrication and contaminate the semiconductor wafer 100 .
- the diameter of the wafer increases from 200 mm to 300 mm
- the radius of the edge of the wafer also increases, thereby more increasing the contamination of the semiconductor wafer by the particles.
- a wet etching process for removing a nitride layer which comprises five steps, is described with reference to FIGS. 7 a to 7 e.
- An oxide layer 102 is deposited on the nitride layer 101 of the silicon semiconductor wafer 100 by a plasma depositing apparatus ( FIG. 7 a ).
- a photoresist layer 103 is formed on the oxide layer 102 by coating photosensitizer, and the photoresist layer 103 on the edge of the semiconductor wafer 100 is removed, thereby exposing the oxide layer 102 of the edge of the semiconductor wafer 100 ( FIG. 7 b ).
- the exposed oxide layer 102 of the edge of the semiconductor wafer 100 is removed by a chemical solution (NHF 4 +HF) using a wet etching device ( FIG. 7 c ).
- the photoresist layer 103 on the oxide layer 102 is removed using a dry etching device and residual photoresist 103 is washed by a chemical solution (H 2 SO 4 /H 2 O 2 ) using a washing apparatus ( FIG. 7 d ).
- the exposed nitride layer 101 of the edge of the semiconductor wafer 100 is removed by a phosphoric acid (H 3 PO 4 ) solution of high temperature using a wet etching device ( FIG. 7 e ).
- wet etching process of the nitride layer is complex. Further, this wet etching process of the nitride layer requires different apparatuses for performing the deposition of the oxide layer, the coating of the photoresist, the removal of the photoresist by dry etching, the removal of the oxide layer by wet etching, the full removal of the residual photoresist, the washing, and the wet etching of the nitride layer.
- the oxide layer 102 is deposited on the poly-silicon layer 104 on the silicon semiconductor wafer 100 using a plasma depositing apparatus ( FIG. 8 a ).
- a photoresist layer 103 is formed on the oxide layer 102 by coating photosensitizer, and the photoresist layer 103 on the edge of the semiconductor wafer 100 is removed, thereby exposing the oxide layer 102 on the edge of the semiconductor wafer 100 ( FIG. 8 b ).
- the exposed oxide layer 102 on the edge of the semiconductor wafer 100 is removed by a chemical solution (NHF 4 +HF) using a wet etching device ( FIG. 8 c ).
- the photoresist layer 103 on the oxide layer 102 is removed using a dry etching device and residual photoresist 103 is washed by a chemical solution (H 2 SO 4 H 2 O 2 ) using a washing apparatus ( FIG. 8 d ).
- the exposed poly-silicon layer 104 of the edge of the semiconductor wafer 100 is removed using the conventional dry etching device ( FIG. 8 e ).
- the above-described dry etching process of the poly-silicon layer is complex. Further, this dry etching process of the poly-silicon layer requires different apparatuses for performing the deposition of the oxide layer, the coating of the photoresist, the removal of the photoresist by dry etching, the removal of the oxide layer by wet etching, the washing, and the dry etching of the poly-silicon layer.
- the poly-silicon layer of the edge of the semiconductor wafer is removed using the conventional dry etching apparatus, the poly-silicon layer on the upper surface of the edge of the semiconductor wafer can be removed but the poly-silicon layer on the lower and the side surfaces of the edge of the semiconductor wafer cannot be fully removed, or can only be imperfectly removed.
- the conventional dry etching device used for forming fine circuit patterns of the semiconductor chip forms an electric field between a flat-shaped first electrode 300 and a flat-shaped second electrode 300 ′ in a reactive gas atmosphere, and generates plasma into the upper surface of the semiconductor wafer 100 , thereby etching a deposited layer on the upper surface 100 a of the semiconductor wafer 100 and forming a fine pattern 103 a
- the deposited layer on the edge of the semiconductor wafer 100 is removed.
- Reference number 400 denotes an RF (radio frequency) generator and reference number 500 denotes a matching network.
- the semiconductor wafer 100 is mounted on one electrode 300 ′ and etched, thereby not etching the side surface 100 b and the lower surface 100 c of the semiconductor wafer 100 . Therefore, the deposited layer on the side surface 100 b and the lower surface 100 c of the semiconductor wafer cannot be removed.
- the present invention has been made in view of the above problems, and it is an object of the present invention to provide an electrode for dry etching a semiconductor wafer using plasma, which can effectively remove foreign materials deposited on the lower and the sides surfaces as well as the upper surface of the edge of the semiconductor wafer without causing damage to the wafer.
- an electrode for dry etching a semiconductor wafer comprises a first electrode and a second electrode for removing foreign materials from the edge of the semiconductor wafer using plasma.
- the first electrode includes a first flat plate and a ring-shaped first protrusion corresponding to one surface of the edge of a semiconductor wafer
- the second electrode includes a second flat plate and a ring-shaped second protrusion corresponding to the other surface of the edge of the semiconductor wafer.
- the first protrusion and the second protrusion are the same size.
- an insulation layer may be deposited on or an insulating material may be attached to an inner area of the upper surface of the first electrode, which is inside of the first protrusion.
- FIG. 1 is a partial cross-sectional view of an electrode for dry etching a semiconductor wafer in accordance with the present invention
- FIG. 2 is a schematic view illustrating the etching of the upper and the side surfaces of a semiconductor wafer using the electrode of the present invention
- FIG. 3 is a schematic view illustrating the etching of the lower and the side surfaces of the semiconductor wafer using the electrode of the present invention
- FIG. 4 is a cross-sectional view of a dry etching device provided with the electrode of the present invention.
- FIG. 5 is a side view of semiconductor wafer, on which multiple layers are deposited
- FIG. 6 is a schematic view illustrating the attachment of foreign materials on the semiconductor wafer by equipment.
- FIGS. 7 a to 7 e are cross-sectional views illustrating a process for removing a nitride layer using a conventional wet etching
- FIGS. 8 a to 8 e are cross-sectional views illustrating a process for removing a poly-silicon layer using a conventional dry etching.
- FIG. 9 is a schematic view illustrating the etching of a semiconductor wafer using a conventional electrode.
- FIG. 1 is a partial cross-sectional view of an electrode for dry etching a semiconductor wafer in accordance with the present invention.
- the electrode of the present invention comprises a pair of electrodes, i.e., a first electrode 10 and a second electrode 20 .
- the first electrode 10 and the second electrode 20 are means for generating plasma for removing foreign materials deposited and accumulated on the edge of the semiconductor wafer.
- the first electrode 10 is used as an anode and the second electrode 20 is used as a cathode.
- the first electrode 10 may be used as a cathode and the second electrode 20 may be used as an anode.
- the first electrode 10 is shaped as a flat circle.
- a ring-shaped first protrusion 10 a is formed on the bottom surface of the first electrode 10 .
- a gas inlet hole 10 b is formed between the first protrusion 10 a and the circumference of the first electrode 10 .
- the gas inlet hole 10 b serves to introduce a reactive gas for generating plasma into a vacuum chamber (not shown), in which the first electrode 10 and the second electrode 20 are formed.
- the second electrode 20 is also shaped as a flat circle having the same diameter of that of the first electrode 10 .
- An opening 20 a is formed on the center of the second electrode 20 and a ring-shaped second protrusion 20 b having the same dimension as that of the first protrusion 10 a is formed between the opening 20 a and the circumference of the second electrode 20 .
- a flat portion of the outside of the first protrusion 10 a of the first electrode 10 and a flat portion of the outside of the second protrusion 20 b of the second electrode 20 are referred to as a first flat portion 10 c and a second flat portion 20 c.
- An insulation layer or an insulator 11 is deposited on or attached to an inner area of the bottom surface of the first protrusion 10 a .
- the attached insulating material 11 serves to prevent an electric field or an electromagnetic field from being formed between the first electrode 10 and the second electrode 20 , when a RF power is supplied between the first electrode 10 and the second electrode 20 .
- Polymide, Teflon, silicon, quartz, or ceramic may be used as the insulator 11 .
- FIGS. 2 and 3 illustrate the etching of a semiconductor wafer using the electrode of the present invention.
- FIGS. 2 and 3 illustrate the etching of a semiconductor wafer using the electrode of the present invention.
- an interaction between the first and the second electrodes 10 , 20 of the present invention and the semiconductor wafer 30 is described.
- the semiconductor wafer 30 is interposed between the first electrode 10 as the anode and the second electrode 20 as the cathode by an electrostatic chuck 40 .
- the electrostatic chuck 40 is installed at a lowering position via the opening 20 a of the second electrode 20 , thereby bringing the lower surface 30 c of the edge of the semiconductor wafer 30 into contact with the upper surface of the second protrusion 20 b of the second electrode 20 .
- a reactive gas is introduced via the gas inlet hole 10 b of the first electrode 10 and power is supplied from the RF generator 50 to the second electrode 20 , thereby forming an electric field or an electromagnetic field through the first protrusion 10 a and the first flat portion 10 c of the first electrode 10 and the second protrusion 20 b and the second flat portion 20 c of the second electrode 20 . Then, two types of plasma with different intensity are generated by the reactive gas between the first protrusion 10 a and the second protrusion 20 b and between the first flat portion 10 c and the second flat portion 20 c.
- plasma is formed along width of the first protrusion 10 a and the second protrusion 20 b .
- the width of the first protrusion 10 a and the second protrusion 20 b corresponds to the width B of the edge of the semiconductor wafer 30 to be etched. Therefore, an area A of the semiconductor wafer 30 , in which fine circuit pattern 31 is formed, is not affected by this plasma.
- the side surface 30 b of the semiconductor wafer 30 is etched by plasma C formed between the first flat portion 10 c and the second flat portion 20 c.
- the etching is mainly performed on the upper surface 30 a and the side surface 30 b of the semiconductor wafer 30 by RIB Reactive Ion Etching).
- the insulating material 11 attached to the inner area of the first electrode 10 an electric field or an electromagnetic field is not formed in the area A, thereby preventing plasma from being generated on the area A and improving the efficiency of the etching.
- reference number 60 denotes a matching network.
- the electrostatic chuck 40 is elevated via the opening 20 a of the second electrode 20 , thereby bringing the upper surface 30 a of the edge of the semiconductor wafer 30 into contact with the upper surface of the first protrusion 10 a of the first electrode 10 .
- the reactive gas is introduced via the gas inlet hole 10 b of the first electrode 10 and the power is supplied from the RF generator 50 , thereby generating plasma between the first protrusion 10 a and the second protrusion 20 b .
- the etching is mainly performed on the lower surface 30 c and the side surface 30 b of the semiconductor wafer 30 by plasma, thereby removing the foreign materials deposited on the area B.
- FIG. 4 is a cross-sectional view of a vacuum chamber 70 , in which the electrode of the present invention is installed.
- the vacuum chamber 70 comprises a blow pipe 71 for introducing a reactive gas for generating plasma into the first electrode 10 and the second electrode 20 , a port 70 a for entering the semiconductor wafer 30 , an outlet 70 b for exhausting the gas after the etching of the semiconductor wafer 30 , and the electrostatic chuck 40 for moving the semiconductor wafer 30 upward and downward.
- the semiconductor wafer 30 is entered into the vacuum chamber 70 via the port 70 a and mounted on the electrostatic chuck 40 .
- the RF generator 50 supplies a voltage via the second electrode 20 .
- the upper surface of the central portion of the semiconductor wafer 30 is protected by the insulating material 11 of the first electrode 10 , and plasma is generated between the first protrusion 10 a and the second protrusion 20 b and between the first flat portion 10 c and the second flat portion 20 c .
- the upper, the lower, and the side surfaces 30 a , 30 c , and 30 b of the edge of the semiconductor wafer 30 are etched through the aforementioned process.
- the foreign materials removed from the semiconductor wafer 30 and the reactive gas are pumped out via the outlet 70 b.
- Table 1 illustrates the reactive gases used in the dry etching of the edge of the semiconductor wafer using the electrode of the present invention and the foreign materials removed using the corresponding reactive gas.
- the conventional etching device has been used to remove only one type of materials, i.e., a wet etching device for removing the nitride layer or a dry etching device for forming a fine circuit pattern on a semiconductor wafer. Therefore, the process for etching the semiconductor wafer is very complex and each step of the process requires a corresponding etching device.
- the electrode of the present invention is used to remove all foreign materials shown in Table 1 by sequentially supplying appropriate reactive gases corresponding to each material without additional equipment, thereby simplifying the whole process.
- portions other than the upper, the side and the lower surfaces of the edge of the semiconductor wafer are not affected by plasma, thereby effectively etching the edge of the semiconductor wafer and not damaging the fine circuit pattern formed on the center of the semiconductor wafer.
- the present invention provides a an electrode for dry etching a semiconductor wafer, which removes foreign materials deposited on the upper, the side and the lower surfaces of the edge of the semiconductor wafer, without additional equipment or step, thereby simplifying the whole process, reducing the process cost, and improving the yield, the quality of the semiconductor wafer, and its productivity.
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Abstract
Disclosed is an electrode for dry etching a wafer. The electrode includes a first electrode and a second electrode. The first electrode includes a first flat plate and a ring-shaped first protrusion corresponding to one surface of the edge of a wafer, and the second electrode includes a second flat plate and a ring-shaped second protrusion corresponding to the other surface of the edge of the wafer. The first plate and the second flat plate are the same dimension, and the first protrusion and the second protrusion are the same dimension.
Description
- The present invention relates to a dry etching of a semiconductor wafer, and more particularly to an electrode for dry etching a semiconductor wafer using plasma, thereby removing foreign material deposited on the edge of the semiconductor wafer for manufactuing integrated circuit chips.
- As well known to those skilled in the art, during the fabrication of high integrated semiconductor chips,
multiple layers semiconductor wafer 100, as shown inFIG. 5 . Further, as shown inFIG. 6 , particles broken off the deposited layers on the edge of thesemiconductor wafer 100 are generated while transferring thesemiconductor wafer 100 or byequipment 200, and introduced into the central portion of thesemiconductor wafer 100, thereby contaminating the integrated circuit chips. - Moreover, a gate electrode of a semiconductor chip has been recently changed from tungsten silicide to tungsten, and an insulation layer of a capacitor has been changed from an ONO (oxide-nitride-oxide) structure to tantalum oxide. An organic bottom anti-reflective coating (hereinafter, referred to as ARC) layer and an inorganic ARC layer such as SiON have been recently used to form fine photoresist patterns, and Ti and TiN layers have been used as a barrier metal layer. Therefore, these materials contaminate the semiconductor wafer by the aforementioned route during fabrication.
- That is, these materials act as a particle source during fabrication and contaminate the
semiconductor wafer 100. Particularly, in case that the diameter of the wafer increases from 200 mm to 300 mm, the radius of the edge of the wafer also increases, thereby more increasing the contamination of the semiconductor wafer by the particles. - Since the materials deposited and accumulated on the edge of the
semiconductor wafer 100 reduce the yield and the reliability of the semiconductor chip, these materials need to be fully removed. - Accordingly, in order to remove the materials deposited and accumulated on the edge of the semiconductor wafer, several methods have been used as follows.
- For example, hereinafter, a wet etching process for removing a nitride layer, which comprises five steps, is described with reference to
FIGS. 7 a to 7 e. - i. An
oxide layer 102 is deposited on thenitride layer 101 of thesilicon semiconductor wafer 100 by a plasma depositing apparatus (FIG. 7 a). - ii. A
photoresist layer 103 is formed on theoxide layer 102 by coating photosensitizer, and thephotoresist layer 103 on the edge of thesemiconductor wafer 100 is removed, thereby exposing theoxide layer 102 of the edge of the semiconductor wafer 100 (FIG. 7 b). - iii. The exposed
oxide layer 102 of the edge of thesemiconductor wafer 100 is removed by a chemical solution (NHF4+HF) using a wet etching device (FIG. 7 c). - iv. The
photoresist layer 103 on theoxide layer 102 is removed using a dry etching device andresidual photoresist 103 is washed by a chemical solution (H2SO4/H2O2) using a washing apparatus (FIG. 7 d). - v. The exposed
nitride layer 101 of the edge of thesemiconductor wafer 100 is removed by a phosphoric acid (H3PO4) solution of high temperature using a wet etching device (FIG. 7 e). - The above-described wet etching process of the nitride layer is complex. Further, this wet etching process of the nitride layer requires different apparatuses for performing the deposition of the oxide layer, the coating of the photoresist, the removal of the photoresist by dry etching, the removal of the oxide layer by wet etching, the full removal of the residual photoresist, the washing, and the wet etching of the nitride layer.
- On the other hand, a dry etching process for removing the poly-silicon layer, which comprises five steps, is described with reference to
FIGS. 8 a to 8 e. - i. The
oxide layer 102 is deposited on the poly-silicon layer 104 on thesilicon semiconductor wafer 100 using a plasma depositing apparatus (FIG. 8 a). - ii. A
photoresist layer 103 is formed on theoxide layer 102 by coating photosensitizer, and thephotoresist layer 103 on the edge of thesemiconductor wafer 100 is removed, thereby exposing theoxide layer 102 on the edge of the semiconductor wafer 100 (FIG. 8 b). - iii. The exposed
oxide layer 102 on the edge of thesemiconductor wafer 100 is removed by a chemical solution (NHF4+HF) using a wet etching device (FIG. 8 c). - iv. The
photoresist layer 103 on theoxide layer 102 is removed using a dry etching device andresidual photoresist 103 is washed by a chemical solution (H2SO4H2O2) using a washing apparatus (FIG. 8 d). - v. The exposed poly-
silicon layer 104 of the edge of thesemiconductor wafer 100 is removed using the conventional dry etching device (FIG. 8 e). - Identically with the aforementioned wet etching of the nitride layer, the above-described dry etching process of the poly-silicon layer is complex. Further, this dry etching process of the poly-silicon layer requires different apparatuses for performing the deposition of the oxide layer, the coating of the photoresist, the removal of the photoresist by dry etching, the removal of the oxide layer by wet etching, the washing, and the dry etching of the poly-silicon layer.
- When the poly-silicon layer of the edge of the semiconductor wafer is removed using the conventional dry etching apparatus, the poly-silicon layer on the upper surface of the edge of the semiconductor wafer can be removed but the poly-silicon layer on the lower and the side surfaces of the edge of the semiconductor wafer cannot be fully removed, or can only be imperfectly removed.
- Further, since different conventional etching apparatuses are respectively used in each step for forming patterns on the semiconductor wafer, that is, since one etching apparatus is used only to remove one foreign material, it is impossible to use one etching apparatus to remove various materials.
- As shown in
FIG. 9 , the conventional dry etching device used for forming fine circuit patterns of the semiconductor chip forms an electric field between a flat-shapedfirst electrode 300 and a flat-shapedsecond electrode 300′ in a reactive gas atmosphere, and generates plasma into the upper surface of thesemiconductor wafer 100, thereby etching a deposited layer on theupper surface 100 a of thesemiconductor wafer 100 and forming afine pattern 103 a Herein, the deposited layer on the edge of thesemiconductor wafer 100 is removed.Reference number 400 denotes an RF (radio frequency) generator andreference number 500 denotes a matching network. - In the conventional dry etching device, the
semiconductor wafer 100 is mounted on oneelectrode 300′ and etched, thereby not etching theside surface 100 b and thelower surface 100 c of thesemiconductor wafer 100. Therefore, the deposited layer on theside surface 100 b and thelower surface 100 c of the semiconductor wafer cannot be removed. - Therefore, the present invention has been made in view of the above problems, and it is an object of the present invention to provide an electrode for dry etching a semiconductor wafer using plasma, which can effectively remove foreign materials deposited on the lower and the sides surfaces as well as the upper surface of the edge of the semiconductor wafer without causing damage to the wafer.
- In accordance with the present invention, the above and other objects can be accomplished by the provision of an electrode for dry etching a semiconductor wafer. The electrode comprises a first electrode and a second electrode for removing foreign materials from the edge of the semiconductor wafer using plasma. The first electrode includes a first flat plate and a ring-shaped first protrusion corresponding to one surface of the edge of a semiconductor wafer, and the second electrode includes a second flat plate and a ring-shaped second protrusion corresponding to the other surface of the edge of the semiconductor wafer. Herein, the first protrusion and the second protrusion are the same size.
- Preferably, an insulation layer may be deposited on or an insulating material may be attached to an inner area of the upper surface of the first electrode, which is inside of the first protrusion.
- The above and other objects, features and other advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
-
FIG. 1 is a partial cross-sectional view of an electrode for dry etching a semiconductor wafer in accordance with the present invention; -
FIG. 2 is a schematic view illustrating the etching of the upper and the side surfaces of a semiconductor wafer using the electrode of the present invention; -
FIG. 3 is a schematic view illustrating the etching of the lower and the side surfaces of the semiconductor wafer using the electrode of the present invention; -
FIG. 4 is a cross-sectional view of a dry etching device provided with the electrode of the present invention; -
FIG. 5 is a side view of semiconductor wafer, on which multiple layers are deposited; -
FIG. 6 is a schematic view illustrating the attachment of foreign materials on the semiconductor wafer by equipment. -
FIGS. 7 a to 7 e are cross-sectional views illustrating a process for removing a nitride layer using a conventional wet etching; -
FIGS. 8 a to 8 e are cross-sectional views illustrating a process for removing a poly-silicon layer using a conventional dry etching; and -
FIG. 9 is a schematic view illustrating the etching of a semiconductor wafer using a conventional electrode. -
FIG. 1 is a partial cross-sectional view of an electrode for dry etching a semiconductor wafer in accordance with the present invention. The electrode of the present invention comprises a pair of electrodes, i.e., afirst electrode 10 and asecond electrode 20. Thefirst electrode 10 and thesecond electrode 20 are means for generating plasma for removing foreign materials deposited and accumulated on the edge of the semiconductor wafer. - Herein, the
first electrode 10 is used as an anode and thesecond electrode 20 is used as a cathode. However, thefirst electrode 10 may be used as a cathode and thesecond electrode 20 may be used as an anode. - The same as the conventional electrode, the
first electrode 10 is shaped as a flat circle. A ring-shapedfirst protrusion 10 a is formed on the bottom surface of thefirst electrode 10. Agas inlet hole 10 b is formed between thefirst protrusion 10 a and the circumference of thefirst electrode 10. Thegas inlet hole 10 b serves to introduce a reactive gas for generating plasma into a vacuum chamber (not shown), in which thefirst electrode 10 and thesecond electrode 20 are formed. - The
second electrode 20 is also shaped as a flat circle having the same diameter of that of thefirst electrode 10. Anopening 20 a is formed on the center of thesecond electrode 20 and a ring-shapedsecond protrusion 20 b having the same dimension as that of thefirst protrusion 10 a is formed between the opening 20 a and the circumference of thesecond electrode 20. - A flat portion of the outside of the
first protrusion 10 a of thefirst electrode 10 and a flat portion of the outside of thesecond protrusion 20 b of thesecond electrode 20 are referred to as a firstflat portion 10 c and a secondflat portion 20 c. - An insulation layer or an
insulator 11 is deposited on or attached to an inner area of the bottom surface of thefirst protrusion 10 a. The attached insulatingmaterial 11 serves to prevent an electric field or an electromagnetic field from being formed between thefirst electrode 10 and thesecond electrode 20, when a RF power is supplied between thefirst electrode 10 and thesecond electrode 20. Polymide, Teflon, silicon, quartz, or ceramic may be used as theinsulator 11. -
FIGS. 2 and 3 illustrate the etching of a semiconductor wafer using the electrode of the present invention. Hereinafter, with reference toFIGS. 2 and 3 , an interaction between the first and thesecond electrodes semiconductor wafer 30 is described. - As shown in
FIG. 2 , thesemiconductor wafer 30 is interposed between thefirst electrode 10 as the anode and thesecond electrode 20 as the cathode by anelectrostatic chuck 40. Theelectrostatic chuck 40 is installed at a lowering position via theopening 20 a of thesecond electrode 20, thereby bringing thelower surface 30 c of the edge of thesemiconductor wafer 30 into contact with the upper surface of thesecond protrusion 20 b of thesecond electrode 20. - A reactive gas is introduced via the
gas inlet hole 10 b of thefirst electrode 10 and power is supplied from theRF generator 50 to thesecond electrode 20, thereby forming an electric field or an electromagnetic field through thefirst protrusion 10 a and the firstflat portion 10 c of thefirst electrode 10 and thesecond protrusion 20 b and the secondflat portion 20 c of thesecond electrode 20. Then, two types of plasma with different intensity are generated by the reactive gas between thefirst protrusion 10 a and thesecond protrusion 20 b and between the firstflat portion 10 c and the secondflat portion 20 c. - Herein, plasma is formed along width of the
first protrusion 10 a and thesecond protrusion 20 b. The width of thefirst protrusion 10 a and thesecond protrusion 20 b corresponds to the width B of the edge of thesemiconductor wafer 30 to be etched. Therefore, an area A of thesemiconductor wafer 30, in whichfine circuit pattern 31 is formed, is not affected by this plasma. Theside surface 30 b of thesemiconductor wafer 30 is etched by plasma C formed between the firstflat portion 10 c and the secondflat portion 20 c. - Since the
lower surface 30 c of thesemiconductor wafer 30 is in contact with the upper surface of thesecond protrusion 20 b of thesecond electrode 20, the etching is mainly performed on theupper surface 30 a and theside surface 30 b of thesemiconductor wafer 30 by RIB Reactive Ion Etching). - Further, since the insulating
material 11 attached to the inner area of thefirst electrode 10, an electric field or an electromagnetic field is not formed in the area A, thereby preventing plasma from being generated on the area A and improving the efficiency of the etching. - Herein,
reference number 60 denotes a matching network. - As shown in
FIG. 3 , theelectrostatic chuck 40 is elevated via theopening 20 a of thesecond electrode 20, thereby bringing theupper surface 30 a of the edge of thesemiconductor wafer 30 into contact with the upper surface of thefirst protrusion 10 a of thefirst electrode 10. Then, the reactive gas is introduced via thegas inlet hole 10 b of thefirst electrode 10 and the power is supplied from theRF generator 50, thereby generating plasma between thefirst protrusion 10 a and thesecond protrusion 20 b. Herein, the etching is mainly performed on thelower surface 30 c and theside surface 30 b of thesemiconductor wafer 30 by plasma, thereby removing the foreign materials deposited on the area B. -
FIG. 4 is a cross-sectional view of avacuum chamber 70, in which the electrode of the present invention is installed. Thevacuum chamber 70 comprises ablow pipe 71 for introducing a reactive gas for generating plasma into thefirst electrode 10 and thesecond electrode 20, aport 70 a for entering thesemiconductor wafer 30, anoutlet 70 b for exhausting the gas after the etching of thesemiconductor wafer 30, and theelectrostatic chuck 40 for moving thesemiconductor wafer 30 upward and downward. - The
semiconductor wafer 30 is entered into thevacuum chamber 70 via theport 70 a and mounted on theelectrostatic chuck 40. Under a reactive gas atmosphere, theRF generator 50 supplies a voltage via thesecond electrode 20. At this time, the upper surface of the central portion of thesemiconductor wafer 30 is protected by the insulatingmaterial 11 of thefirst electrode 10, and plasma is generated between thefirst protrusion 10 a and thesecond protrusion 20 b and between the firstflat portion 10 c and the secondflat portion 20 c. Then, the upper, the lower, and the side surfaces 30 a, 30 c, and 30 b of the edge of thesemiconductor wafer 30 are etched through the aforementioned process. - During the etching process, the same as the conventional case, the foreign materials removed from the
semiconductor wafer 30 and the reactive gas are pumped out via theoutlet 70 b. - Hereinafter, Table 1 illustrates the reactive gases used in the dry etching of the edge of the semiconductor wafer using the electrode of the present invention and the foreign materials removed using the corresponding reactive gas.
TABLE 1 Material Reactive Gas Organic ARC (SiON) CF4, SF6 Inorganic ARC (CxSiy) CF4, O2 Oxide layer (SiO2) CF4, CHF3, C4F8, C2F6, Ar, O2, CH2F2 Nitride layer (Si3N4) CF4, SF6, CHF3, Ar, O2 Poly-silicon (Si) HBr, Cl2, CCl4, SF6, O2 Tungsten silicide (WSix) SF6, Cl2 Tungsten (W) SF6, CF4, Ar, O2 Aluminum (Al) Cl2, CCl4, BCl3 Copper (Cu) Cl2 Tantalum oxide (TaO2) SF6, Cl2, CF4 Tantalum (TaON) SF6, Cl2, CF4 Titanium (Ti) CF4, SF6 Titanium silicide (TiSix) SF6, CF4, O2 SOG, [RxSiOySiO2]n, H(SiO3/2)n SF6, CF4, O2 - As described above, the conventional etching device has been used to remove only one type of materials, i.e., a wet etching device for removing the nitride layer or a dry etching device for forming a fine circuit pattern on a semiconductor wafer. Therefore, the process for etching the semiconductor wafer is very complex and each step of the process requires a corresponding etching device.
- Further, with the structure of the electrode of the conventional etching device, foreign materials deposited on the upper surface and the side surface of the edge of the semiconductor wafer can be removed. However, foreign materials deposited on the lower surface of the edge of the semiconductor wafer cannot be removed.
- However, the electrode of the present invention is used to remove all foreign materials shown in Table 1 by sequentially supplying appropriate reactive gases corresponding to each material without additional equipment, thereby simplifying the whole process.
- Moreover, portions other than the upper, the side and the lower surfaces of the edge of the semiconductor wafer are not affected by plasma, thereby effectively etching the edge of the semiconductor wafer and not damaging the fine circuit pattern formed on the center of the semiconductor wafer.
- Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.
- As apparent from the above description, the present invention provides a an electrode for dry etching a semiconductor wafer, which removes foreign materials deposited on the upper, the side and the lower surfaces of the edge of the semiconductor wafer, without additional equipment or step, thereby simplifying the whole process, reducing the process cost, and improving the yield, the quality of the semiconductor wafer, and its productivity.
Claims (2)
1. An electrode for dry etching a wafer, said electrode comprising a first electrode and a second electrode for removing foreign materials from the edge of the wafer by plasma, said first electrode including a first flat plate and a ring-shaped first protrusion corresponding to one surface of the edge of a wafer, and said second electrode including a second flat plate and a ring-shaped second protrusion corresponding to the other surface of the edge of the wafer, wherein said first protrusion and said second protrusion are the same size.
2. The electrode for dry etching a wafer as set forth in claim 1 , wherein an insulation layer is deposited on or an insulating material is attached to an inner area of the upper surface of the first electrode, which is inside of the first protrusion.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2002-0011395A KR100442194B1 (en) | 2002-03-04 | 2002-03-04 | Electrodes For Dry Etching Of Wafer |
KR2002-0011395 | 2002-03-04 | ||
PCT/KR2002/000715 WO2003075333A1 (en) | 2002-03-04 | 2002-04-19 | Electrode for dry etching a wafer |
Publications (1)
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US20050178505A1 true US20050178505A1 (en) | 2005-08-18 |
Family
ID=36083977
Family Applications (1)
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US10/506,558 Abandoned US20050178505A1 (en) | 2002-03-04 | 2002-04-19 | Electrode for dry etching a wafer |
Country Status (6)
Country | Link |
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US (1) | US20050178505A1 (en) |
JP (1) | JP4152895B2 (en) |
KR (1) | KR100442194B1 (en) |
AU (1) | AU2002253689A1 (en) |
TW (1) | TWI230415B (en) |
WO (1) | WO2003075333A1 (en) |
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TWI230415B (en) | 2005-04-01 |
JP2005519469A (en) | 2005-06-30 |
KR100442194B1 (en) | 2004-07-30 |
JP4152895B2 (en) | 2008-09-17 |
TW200304183A (en) | 2003-09-16 |
AU2002253689A1 (en) | 2003-09-16 |
KR20030072520A (en) | 2003-09-15 |
WO2003075333A1 (en) | 2003-09-12 |
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