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US20040099961A1 - Semiconductor package substrate having bonding pads with plated layer thereon and process of manufacturing the same - Google Patents

Semiconductor package substrate having bonding pads with plated layer thereon and process of manufacturing the same Download PDF

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Publication number
US20040099961A1
US20040099961A1 US10/683,814 US68381403A US2004099961A1 US 20040099961 A1 US20040099961 A1 US 20040099961A1 US 68381403 A US68381403 A US 68381403A US 2004099961 A1 US2004099961 A1 US 2004099961A1
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Prior art keywords
bonding pads
conductive film
substrate
nickel
gold
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Abandoned
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US10/683,814
Inventor
Chih-Liang Chu
E-Tung Chou
Lin-Yin Wong
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Phoenix Precision Technology Corp
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Phoenix Precision Technology Corp
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Priority claimed from TW091134161A external-priority patent/TW571372B/en
Priority claimed from TW091135386A external-priority patent/TW569360B/en
Application filed by Phoenix Precision Technology Corp filed Critical Phoenix Precision Technology Corp
Assigned to PHOENIX PRECISION TECHNOLOGY CORPORATION reassignment PHOENIX PRECISION TECHNOLOGY CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHOU, E-TUNG, CHU, CHIH-LIANG, WONG, LIN-YIN
Publication of US20040099961A1 publication Critical patent/US20040099961A1/en
Priority to US11/223,740 priority Critical patent/US7396753B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/243—Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/01022—Titanium [Ti]
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    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0361—Stripping a part of an upper metal layer to expose a lower metal layer, e.g. by etching or using a laser
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0502—Patterning and lithography
    • H05K2203/0542—Continuous temporary metal layer over metal pattern

Definitions

  • the invention relates to a semiconductor package substrate having a plurality of bonding pads with a plated layer thereon, and a process of manufacturing the substrate. More particularly, the invention relates to a semiconductor package substrate in which a Ni/Au plated layer is formed on an exposed surface of a bonding pad, and a process of forming the Ni/Au plated layer on the exposed surface of the bonding pad of the semiconductor package substrate.
  • a plurality of conductive traces are formed on a substrate of a semiconductor package, and respectively extend to a plurality of bonding pads for signal and electrical current transmission.
  • a Ni/Au layer is usually formed over the exposed surface of each bonding pad to improve electrical connection between gold wires, bumps or solder balls, chips or printed circuit board elements, and to further prevent oxidation of the bonding pads.
  • the bonding pads are the electrical contacts, for example, bump pads or presolder pads used to electrically connect a flip-chip package substrate to the chip, or a ball pad used to electrically connect the package substrate to the printed circuit board.
  • a Ni/Au layer is usually formed over exposed surfaces of the bonding pads to prevent the bonding pads, which are usually made of copper, from oxidizing in the atmosphere. Therefore, electrical connection of the bumps, presolder or solder balls to chips or the printed circuit board is improved.
  • the process of forming the Ni/Au layer over the bonding pads includes either chemically forming Ni/Au or electroplating Ni/Au.
  • the chemical formation of a Ni/Au layer includes a non-electrical process such as the Nickel/Immersion Gold (EN/IG) process, which comprises electroless plating of the substrate in a Nickel bath to form a nickel layer on the bonding pad and immersion of the substrate in a gold bath to deposit a gold layer on the nickel layer.
  • EN/IG Nickel/Immersion Gold
  • This process usually has disadvantages such as poor solderability and insufficient soldering strength, and further may form black pads and soldering with non-uniform-thickness. Soldering with non-uniform-thickness occurs when the nickel bath varies between temperature cycles.
  • the Gold layer often does not fully cover the nickel layer and thus the underlying copper layer may be externally exposed.
  • Black pads are typically formed when the substrate is dipped in a gold bath while excessive oxidation is occurring. Specifically, gold atoms irregularly deposit on the nickel surface, resulting in a porous structure of a gold plated layer that, owing to a chemical battery effect on the underlying Nickel layer, causes continuous oxidation and aging of the underlying nickel layer. Problems such as non-uniform thickness and black pads deteriorate the connection and bonding of gold wires, solder bumps, presolder or solder balls to the bonding pads. Therefore, the reliability of the semiconductor package is reduced.
  • a conventional process forms a plurality of plating wires 11 respectively on a plurality of bonding pads 10 of a semiconductor package substrate 1 .
  • a Ni/Au layer 12 is plated on the bonding pads 10 by means of the plating wires 11 .
  • the plating wires 11 undesirably occupy a portion of the routing area of the substrate 1 , and further may generate noise due to an antenna effect when used at high frequency.
  • a conductive layer 21 is formed on either side of a substrate 2 , being used to carry a semiconductor chip.
  • a plurality of plated through holes (PTH) or blind vias (not shown) are formed through the substrate 2 .
  • a photoresist layer 22 is formed to cover a portion of the conductive layer 21 so that traces can be formed.
  • the conductive layer serves as a path for electrical current.
  • the conductive layer 21 not covered by the photoresist layer 22 is plated with a Ni/Au layer 23 , as shown in FIG. 2B. Then, the photoresist layer 22 is removed, leaving the Ni/Au layer 23 , as shown in FIG.
  • the conductive layer 21 is patterned to form a trace layer 24 by using the Ni/Au layer 23 as an etching mask. Thereby, an exposed surface of the trace layer 24 is plated with a Ni/Au layer 23 , as shown in FIG. 2D.
  • the Ni/Au layer is necessary to form the whole trace layer over the bonding pads and the trace layer of the substrate. Since the material cost of the Ni/Au layer is expensive, material wastage of the Ni/Au layer increase the total production cost. Also, the solder mask subsequently formed to cover the substrate is not very compatible with the Ni/Au layer, which further reduces the reliability.
  • a process of manufacturing a semiconductor package substrate of the invention includes the following steps: providing a package substrate having a plurality of bonding pads on at least one surface thereof; plating the bonding pads and then forming a solder mask having a plurality of openings over the substrate to expose the bonding pads with the plated layer thereon.
  • the process of the invention provides a package substrate having a plurality of bonding pads on at least one surface thereof.
  • a conductive film is formed over the substrate.
  • a photoresist layer having a plurality of first openings is formed over the conductive film to expose the conductive film on the bonding pads.
  • the photoresist layer optionally has an extension portion extending from an inner wall of each first opening to cover a portion of the conductive film on each bonding pad.
  • the portion of the conductive film not covered by the photoresist layer is removed to expose the bonding pads respectively through the first openings.
  • An electroplating process is performed to plate the exposed bonding pads to form a metal layer such as a Ni/Au layer.
  • the solder mask has a plurality of second openings to expose the bonding pads with the plated layer thereon. Each second opening has a diameter that may be either smaller or larger than the size of each bonding pad.
  • the plated layer (such as a Ni/Au layer) covering the exposed surface of the bonding pads of the package substrate improves the electrical connection to other devices, and protects the bonding pads from oxidizing in the ambient environment. Problems such as non-uniform plating thickness and black pads thereby are overcome, and the reliability of the semiconductor package is improved.
  • the conductive film serves as a path for electrical current to electrically connect the bonding pads on the package substrate, without the need of plating wires on the package substrate. Thereby, the available routing area is greatly increased and noise interference induced by the plating wires is avoided.
  • formation of a Ni/Au layer over the whole trace layer of the substrate which is necessary in the prior art, is not required in the invention. Thus the production cost thereby is significantly reduced.
  • FIG. 1 is a cross-sectional view of a conventional substrate having a bonding pad with a Ni/Au layer thereon;
  • FIG. 2A to FIG. 2D are cross-sectional views of another conventional substrate having a bonding pad with a Ni/Au layer thereon;
  • FIG. 3 is a cross-sectional view of a package substrate having a bonding pad with a plated layer thereon according to the invention
  • FIG. 4A to FIG. 4H are cross-sectional views of a package substrate having a bonding pad with a plated layer thereon according to a first embodiment of the invention
  • FIG. 5A to FIG. 51 are cross-sectional views of a package substrate having a bonding pad with a plated layer thereon according to a second embodiment of the invention.
  • FIG. 6A is a perspective view of a package substrate having a photoresist layer to cover a conductive film thereon according to a second embodiment of the invention
  • FIG. 6B is a perspective view of a package substrate having a bonding pad that is covered by a plated layer according to a second embodiment of the invention.
  • FIG. 6C and FIG. 6D are perspective views of a package substrate having a solder mask thereon according to a second embodiment of the invention.
  • FIG. 3 is a cross-sectional view of a bonding pad electrically connecting to a semiconductor package substrate according to one embodiment of the invention.
  • a semiconductor package substrate 3 is a flip-chip ball grid array (BGA) package substrate, including a plurality of insulating layers 31 alternated with trace layers 32 , conductive vias 33 formed through the insulating layers to electrically connect the trace layers 32 , and a solder mask 38 covering the substrate 3 .
  • BGA ball grid array
  • the insulating layers 31 are made of an organic material, a fiber-reinforced organic material or a particle-reinforced organic material, for example, epoxy resin, polyimide, bismaleimide triazine-based resin, or cyanate ester.
  • Each trace layer 32 is formed by depositing a metal layer, for example copper, on one insulating layer 31 , and then patterning the metal layer. An electroplating process can be optionally performed to pattern the metal layer and form the trace layer 32 .
  • a plurality of bonding pads 35 are respectively formed on the trace layers 32 on a first surface 3 a and a second surface 3 b of the semiconductor package substrate 3 .
  • the bonding pads 35 electrically connect at least one flip-chip semiconductor chip 40 to the first surface 3 a of the substrate 3 through a plurality of solder bumps 39 a .
  • the bonding pads 35 on the second surface 3 b of the substrate 3 can be, for example, ball pads on which a solder ball 39 b is formed to electrically connect the chip 40 , bonded to the substrate 3 by flip chip technology, to the printed circuit board.
  • a metal layer 35 c is usually formed over an exposed surface of each bonding pad 35 as metallic barrier layer to protect the bonding pads 35 , being made of copper, from oxidation due to being exposed to the ambient environment, and further to increase the bondability of the solder bumps 39 a and the solder balls 39 b with the bonding pads.
  • the metallic barrier layer includes a Nickel adhesive layer and a gold protective layer over each bonding pad 35 .
  • the barrier layer can be formed by, for example, electroplating, electroless plating or physical vapor deposition (PVD) of a metal material such as gold, nickel, palladium, silver, tin, nickel/palladium, chromium/titanium, palladium/gold or nickel/palladium/gold.
  • PVD physical vapor deposition
  • a solder mask 38 having a plurality of openings 38 a is formed to cover the substrate 3 , the openings 38 a exposing the underlying bonding pads 35 .
  • FIG. 4A to FIG. 4H are cross-sectional views of a bonding pad electrically connecting to a semiconductor package substrate according to a first embodiment of the invention.
  • a semiconductor package substrate 3 is provided.
  • the substrate 3 can be, for example, the flip-chip package substrate as shown in FIG. 3, or a wire-bonding package substrate.
  • the substrate 3 has been previously subjected to a front-end process. For example, a plurality of plated through holes or blind vias have been formed through the substrate 3 .
  • the trace layers 32 have been formed on the substrate 3 .
  • the trace layers 32 further may include a plurality of bonding pads 35 . The process of forming the above parts is well known in the art, and its description is omitted herein.
  • a conductive film 36 is formed over the substrate 3 .
  • the conductive film 36 serves as electric current paths for electroplating the metal layer 35 c .
  • the conductive film 36 is made of a metal selected from the group consisting of copper, tin, nickel, chromium, titanium, copper-chromium and tin-lead alloy.
  • the conductive film 36 is made of copper or palladium particles.
  • the conductive film 36 forming methods include physical vapor deposition (PVD), chemical vapor deposition (CVD), electroless plating, or chemical deposition.
  • a photoresist layer 37 is formed through printing or coating on the substrate 3 on top of the conductive film 36 thereon, through printing or coating.
  • the photoresist layer 37 can be, for example, a dry film or liquid photoresist.
  • the photoresist layer 37 is further formed with a plurality of opening 37 a to expose the conductive film 36 a on the bonding pads 35 .
  • the exposed conductive film 36 is removed by etching or laser ablation to expose the bonding pads 35 .
  • a metal layer such as gold, nickel, palladium, silver, tin, nickel/palladium, chromium/titanium, nickel/gold, palladium/gold or nickel/palladium/gold is plated on the bonding pads 35 .
  • the conductive film 36 is used as a path for electrical current during plating.
  • the conductive film 36 is preferably formed by plating a nickel layer and then a gold layer.
  • the nickel/gold layer can be formed to cover the exposed surface of each bonding pad 35 as a plated layer 35 c .
  • the material used in the plating process of the invention is not limited to nickel and gold. Other suitable materials used, individually or combined with one another, may also be plated directly on the exposed surface of the bonding pads 35 .
  • FIG. 4F after the plated layer 35 c is formed on the exposed surface of the bonding pads 35 , the photoresist layer 37 and the conductive film 36 covered by the photoresist layer 37 are removed.
  • FIG. 4G illustrates the plated layer 35 c that has been formed on the exposed surface of the bonding pads 35 .
  • a solder mask 38 such as an electrically insulating layer, is formed over the substrate 3 for protection against contamination from the ambient environment.
  • the solder mask 38 has a plurality of openings 38 a to expose the bonding pads 35 having the plated layer 35 c thereon.
  • Each opening 38 a has a diameter that may be either smaller or larger than the size of each bonding pad 35 .
  • the exposed bonding pads 35 having the plated layer 35 c thereon serve as external electrical connections of the chip or circuit board.
  • FIG. 5A to FIG. 5I are cross-sectional views of a bonding pad formed on a semiconductor package substrate according to a second embodiment of the invention.
  • a package substrate 3 is provided.
  • the substrate 3 can be a flip-chip package substrate 3 or a wire-bonding package substrate.
  • the substrate 3 has been subjected to a front-end process. For example, a plurality of through holes or blind holes (not shown) are formed through the substrate 3 , and at least one trace layer 32 is formed on/inside the substrate 3 .
  • a conductive film 36 as illustrated in the first embodiment of the invention is formed over the substrate 3 .
  • the conductive film 36 serves as electric current paths for the electroplating metal layer 35 c.
  • a photoresist layer 37 is formed by printing or coating over the substrate 3 on top of the conductive film 36 thereon.
  • the photoresist layer 37 can be, for example a dry film or a liquid photoresist.
  • the photoresist layer 37 has a plurality of openings 37 a , and each of the openings 37 a has an extension portion extending from an inner wall of each opening 37 a to cover a portion of the conductive film 36 on each bonding pad.
  • the remaining portion 36 a of each bonding pad 35 is exposed trough the corresponding opening 37 a , as shown in FIG. 6A.
  • the exposed conductive film 36 a that is not covered by the photoresist layer 37 is removed by etching or laser ablation. That is, the conductive film 36 a covering the bonding pads 35 in the openings 37 a is removed to expose the bonding pads 35 not covered by the photoresist layer 37 .
  • a metal layer such as gold, nickel, palladium, silver, tin, nickel/palladium, chromium/titanium, nickel/gold, palladium/gold or nickel/palladium/gold is plated on the substrate 3 .
  • the conductive film 36 is used as a path for electrical current during plating.
  • the conductive film 36 is preferably formed through plating a nickel layer and then a gold layer.
  • the nickel/gold layer can be formed to cover the exposed surface of each bonding pad 35 as a plated layer 35 c .
  • the material used in this plating process is not limited to nickel and Gold. Other suitable materials used, individually or combined with one another, may be directly plated on the exposed surface of the bonding pads 35 .
  • FIG. 5F after the plated layer 35 c has been formed on the exposed surface of the bonding pad 35 , the photoresist layer 37 and the conductive film 36 covered by the photoresist layer 37 are removed.
  • FIG. 5G illustrates the plated layer 35 c that has been formed on the exposed surface of the bonding pad 35 .
  • FIG. 6B is a schematic perspective view of the plated layer 35 c.
  • a solder mask 38 is formed over the substrate 3 for protection against contamination in the ambient environment.
  • the solder mask 38 has a plurality of openings 38 a to expose the bonding pads 35 having the plated layer 35 c thereon.
  • Each opening 38 a has a diameter that is smaller than the size of the bonding pad 35 to form a so-called solder mask defined (SMD) configuration.
  • SMD solder mask defined
  • the exposed bonding pads 35 having the plated layer 35 c thereon serve as external electrical connections of the chip or circuit board.
  • FIG. 6C is a schematic, perspective view of the bonding pad 35 .
  • the solder mask 38 is formed over the substrate 3 .
  • the solder mask 38 has a plurality of openings 38 a to expose the bonding pads 35 having the plated layer 35 c thereon.
  • Each opening 38 a has a diameter larger than the size of the bonding pad 35 to form a so-called non-solder mask defined (NSMD) configuration.
  • NSMD non-solder mask defined
  • the exposed bonding pads 35 having the plated layer 35 c thereon serve as external electrical connections of the chip or circuit board.
  • FIG. 6D a schematic, perspective view of the bonding pad 35 is shown.
  • the plated layer such as a Ni/Au layer
  • the conductive film serves as a path for electrical current to electrically connect the bonding pads on the package substrate, without the need of a plating wire on the package substrate.
  • the available outing area is greatly increased and noise interference induced by the plating wires is voided.
  • formation of the Ni/Au layer over the whole trace layer of the substrate is no longer required, which reduces the production cost of the package substrate.
  • the bonding pad of the invention can be of any type, such as a wire bonding pad, a bump pad, a presolder pad, or a ball pad.
  • a wire bonding pad such as a wire bonding pad, a bump pad, a presolder pad, or a ball pad.
  • the number of bonding pad is not limited to one.
  • the actual number of bonding pads, electrical current paths and photoresist layers depend on the circuit design requirement.
  • the bonding pads, the electrical current paths and the photoresist layers can be formed on one or both surfaces of the substrate.

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  • Computer Hardware Design (AREA)
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Abstract

A semiconductor package substrate is provided having a plurality of bonding pads on at least one surface thereof and covered by a conductive film. A photoresist layer formed over the conductive film has a plurality of first openings for exposing portions of the conductive film corresponding to the bonding pads. The exposed portions of the conductive film is removed to expose the bonding pads respectively via the first openings. The exposed bonding pads are plated with a metal layer respectively. Then, the photoresist layer and the remainder of the conductive film covered by the photoresist layer are removed. A solder mask having a plurality of second openings may be formed on the surface of the substrate, and allows the plated metal layer on the bonding pads respectively to be exposed via the second openings.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • The invention relates to a semiconductor package substrate having a plurality of bonding pads with a plated layer thereon, and a process of manufacturing the substrate. More particularly, the invention relates to a semiconductor package substrate in which a Ni/Au plated layer is formed on an exposed surface of a bonding pad, and a process of forming the Ni/Au plated layer on the exposed surface of the bonding pad of the semiconductor package substrate. [0002]
  • 2. Description of the Related Art [0003]
  • Semiconductor package manufacturers have confronted great challenges to satisfy the requirements of product size reduction. A plurality of conductive traces, made of copper, for example, are formed on a substrate of a semiconductor package, and respectively extend to a plurality of bonding pads for signal and electrical current transmission. A Ni/Au layer is usually formed over the exposed surface of each bonding pad to improve electrical connection between gold wires, bumps or solder balls, chips or printed circuit board elements, and to further prevent oxidation of the bonding pads. [0004]
  • The bonding pads are the electrical contacts, for example, bump pads or presolder pads used to electrically connect a flip-chip package substrate to the chip, or a ball pad used to electrically connect the package substrate to the printed circuit board. A Ni/Au layer is usually formed over exposed surfaces of the bonding pads to prevent the bonding pads, which are usually made of copper, from oxidizing in the atmosphere. Therefore, electrical connection of the bumps, presolder or solder balls to chips or the printed circuit board is improved. [0005]
  • In the prior art, the process of forming the Ni/Au layer over the bonding pads includes either chemically forming Ni/Au or electroplating Ni/Au. The chemical formation of a Ni/Au layer includes a non-electrical process such as the Nickel/Immersion Gold (EN/IG) process, which comprises electroless plating of the substrate in a Nickel bath to form a nickel layer on the bonding pad and immersion of the substrate in a gold bath to deposit a gold layer on the nickel layer. This process usually has disadvantages such as poor solderability and insufficient soldering strength, and further may form black pads and soldering with non-uniform-thickness. Soldering with non-uniform-thickness occurs when the nickel bath varies between temperature cycles. Even if the optimal operating conditions have been satisfied, the Gold layer often does not fully cover the nickel layer and thus the underlying copper layer may be externally exposed. Black pads are typically formed when the substrate is dipped in a gold bath while excessive oxidation is occurring. Specifically, gold atoms irregularly deposit on the nickel surface, resulting in a porous structure of a gold plated layer that, owing to a chemical battery effect on the underlying Nickel layer, causes continuous oxidation and aging of the underlying nickel layer. Problems such as non-uniform thickness and black pads deteriorate the connection and bonding of gold wires, solder bumps, presolder or solder balls to the bonding pads. Therefore, the reliability of the semiconductor package is reduced. [0006]
  • In order to avoid the above problems of chemical formation of the Nickel/Gold layer, another approach is to use the electroplating method. Referring to FIG. 1, a conventional process forms a plurality of [0007] plating wires 11 respectively on a plurality of bonding pads 10 of a semiconductor package substrate 1. A Ni/Au layer 12 is plated on the bonding pads 10 by means of the plating wires 11. However, the plating wires 11 undesirably occupy a portion of the routing area of the substrate 1, and further may generate noise due to an antenna effect when used at high frequency.
  • In order to solve the above problems, gold pattern plating has been proposed in the art. Referring to FIG. 2A, a [0008] conductive layer 21 is formed on either side of a substrate 2, being used to carry a semiconductor chip. A plurality of plated through holes (PTH) or blind vias (not shown) are formed through the substrate 2. A photoresist layer 22 is formed to cover a portion of the conductive layer 21 so that traces can be formed. The conductive layer serves as a path for electrical current. The conductive layer 21 not covered by the photoresist layer 22 is plated with a Ni/Au layer 23, as shown in FIG. 2B. Then, the photoresist layer 22 is removed, leaving the Ni/Au layer 23, as shown in FIG. 2C. The conductive layer 21 is patterned to form a trace layer 24 by using the Ni/Au layer 23 as an etching mask. Thereby, an exposed surface of the trace layer 24 is plated with a Ni/Au layer 23, as shown in FIG. 2D.
  • Although plating wires are not required in this case, the Ni/Au layer is necessary to form the whole trace layer over the bonding pads and the trace layer of the substrate. Since the material cost of the Ni/Au layer is expensive, material wastage of the Ni/Au layer increase the total production cost. Also, the solder mask subsequently formed to cover the substrate is not very compatible with the Ni/Au layer, which further reduces the reliability. [0009]
  • Therefore, there is a need for a simple process of manufacturing a semiconductor package substrate with a reduced cost which can avoid the problems of the prior art such as non-uniform thickness and black pads. [0010]
    • SUMMARY OF THE INVENTION
  • It is therefore an objective of the invention to provide a package substrate having a plurality of bonding pads with a plated layer thereon and a process of manufacturing the package substrate, through which a metal layer such as Ni/Au layer is plated on the exposed bonding pads to improve electrical connection of gold wires, solder bumps or solder balls to chips or printed circuit board elements and to prevent the bonding pads from oxidizing in an ambient environment. [0011]
  • It is another objective of the invention to provide a package substrate having a plurality of bonding pads with a plated layer thereon and a process of manufacturing the package substrate, through which problems such as non-uniform plating thickness and black pads are overcome, and the reliability of the semiconductor package is increased. [0012]
  • It is another objective of the invention to provide a package substrate having a plurality of bonding pads with a plated layer thereon and a process of manufacturing the package substrate in which formation of a plurality of additional plating wires on the package substrate is not required. Thereby, the available routing area is greatly increased and noise interference induced by the plating wires can be prevented. [0013]
  • It is another object of the invention to provide a package substrate having a plurality of bonding pads with a plated layer thereon and a process of manufacturing the package substrate in which formation of a Ni/Au layer over the whole trace layer of the substrate is not required, so that the production cost can be significantly reduced. [0014]
  • To achieve the above objectives, a process of manufacturing a semiconductor package substrate of the invention includes the following steps: providing a package substrate having a plurality of bonding pads on at least one surface thereof; plating the bonding pads and then forming a solder mask having a plurality of openings over the substrate to expose the bonding pads with the plated layer thereon. [0015]
  • The process of the invention provides a package substrate having a plurality of bonding pads on at least one surface thereof. A conductive film is formed over the substrate. A photoresist layer having a plurality of first openings is formed over the conductive film to expose the conductive film on the bonding pads. The photoresist layer optionally has an extension portion extending from an inner wall of each first opening to cover a portion of the conductive film on each bonding pad. The portion of the conductive film not covered by the photoresist layer is removed to expose the bonding pads respectively through the first openings. An electroplating process is performed to plate the exposed bonding pads to form a metal layer such as a Ni/Au layer. Then, the photoresist layer and the conductive film covered by the photoresist layer are removed. Afterwards, a solder mask is formed over the substrate. The solder mask has a plurality of second openings to expose the bonding pads with the plated layer thereon. Each second opening has a diameter that may be either smaller or larger than the size of each bonding pad. [0016]
  • According to the package substrate and the manufacturing process of the invention, the plated layer (such as a Ni/Au layer) covering the exposed surface of the bonding pads of the package substrate improves the electrical connection to other devices, and protects the bonding pads from oxidizing in the ambient environment. Problems such as non-uniform plating thickness and black pads thereby are overcome, and the reliability of the semiconductor package is improved. During plating a Ni/Au layer on the bonding pads, the conductive film serves as a path for electrical current to electrically connect the bonding pads on the package substrate, without the need of plating wires on the package substrate. Thereby, the available routing area is greatly increased and noise interference induced by the plating wires is avoided. Furthermore, formation of a Ni/Au layer over the whole trace layer of the substrate, which is necessary in the prior art, is not required in the invention. Thus the production cost thereby is significantly reduced. [0017]
  • To provide a further understanding of the invention, the following detailed description illustrates embodiments and examples of the invention, this detailed description being provided only for illustration of the invention.[0018]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The present invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings wherein: [0019]
  • FIG. 1 (PRIOR ART) is a cross-sectional view of a conventional substrate having a bonding pad with a Ni/Au layer thereon; [0020]
  • FIG. 2A to FIG. 2D (PRIOR ART) are cross-sectional views of another conventional substrate having a bonding pad with a Ni/Au layer thereon; [0021]
  • FIG. 3 is a cross-sectional view of a package substrate having a bonding pad with a plated layer thereon according to the invention; [0022]
  • FIG. 4A to FIG. 4H are cross-sectional views of a package substrate having a bonding pad with a plated layer thereon according to a first embodiment of the invention; [0023]
  • FIG. 5A to FIG. 51 are cross-sectional views of a package substrate having a bonding pad with a plated layer thereon according to a second embodiment of the invention; [0024]
  • FIG. 6A is a perspective view of a package substrate having a photoresist layer to cover a conductive film thereon according to a second embodiment of the invention; [0025]
  • FIG. 6B is a perspective view of a package substrate having a bonding pad that is covered by a plated layer according to a second embodiment of the invention; and [0026]
  • FIG. 6C and FIG. 6D are perspective views of a package substrate having a solder mask thereon according to a second embodiment of the invention.[0027]
    • DETAILED DESCRIPTION OF THE EMBODIMENTS
  • Wherever possible in the following description, like reference numerals will refer to like elements and parts unless otherwise illustrated. [0028]
  • FIG. 3 is a cross-sectional view of a bonding pad electrically connecting to a semiconductor package substrate according to one embodiment of the invention. [0029]
  • A [0030] semiconductor package substrate 3 is a flip-chip ball grid array (BGA) package substrate, including a plurality of insulating layers 31 alternated with trace layers 32, conductive vias 33 formed through the insulating layers to electrically connect the trace layers 32, and a solder mask 38 covering the substrate 3.
  • The insulating layers [0031] 31 are made of an organic material, a fiber-reinforced organic material or a particle-reinforced organic material, for example, epoxy resin, polyimide, bismaleimide triazine-based resin, or cyanate ester. Each trace layer 32 is formed by depositing a metal layer, for example copper, on one insulating layer 31, and then patterning the metal layer. An electroplating process can be optionally performed to pattern the metal layer and form the trace layer 32. A plurality of bonding pads 35 are respectively formed on the trace layers 32 on a first surface 3 a and a second surface 3 b of the semiconductor package substrate 3. The bonding pads 35, for example, bump pads or presolder pads, electrically connect at least one flip-chip semiconductor chip 40 to the first surface 3 a of the substrate 3 through a plurality of solder bumps 39 a. The bonding pads 35 on the second surface 3 b of the substrate 3 can be, for example, ball pads on which a solder ball 39 b is formed to electrically connect the chip 40, bonded to the substrate 3 by flip chip technology, to the printed circuit board.
  • A [0032] metal layer 35 c is usually formed over an exposed surface of each bonding pad 35 as metallic barrier layer to protect the bonding pads 35, being made of copper, from oxidation due to being exposed to the ambient environment, and further to increase the bondability of the solder bumps 39 a and the solder balls 39 b with the bonding pads. The metallic barrier layer includes a Nickel adhesive layer and a gold protective layer over each bonding pad 35. The barrier layer can be formed by, for example, electroplating, electroless plating or physical vapor deposition (PVD) of a metal material such as gold, nickel, palladium, silver, tin, nickel/palladium, chromium/titanium, palladium/gold or nickel/palladium/gold. A solder mask 38 having a plurality of openings 38 a is formed to cover the substrate 3, the openings 38 a exposing the underlying bonding pads 35.
  • FIG. 4A to FIG. 4H are cross-sectional views of a bonding pad electrically connecting to a semiconductor package substrate according to a first embodiment of the invention. [0033]
  • Referring to FIG. 4A, a [0034] semiconductor package substrate 3 is provided. The substrate 3 can be, for example, the flip-chip package substrate as shown in FIG. 3, or a wire-bonding package substrate. The substrate 3 has been previously subjected to a front-end process. For example, a plurality of plated through holes or blind vias have been formed through the substrate 3. The trace layers 32 have been formed on the substrate 3. The trace layers 32 further may include a plurality of bonding pads 35. The process of forming the above parts is well known in the art, and its description is omitted herein.
  • Referring to FIG. 4B, a [0035] conductive film 36 is formed over the substrate 3. The conductive film 36 serves as electric current paths for electroplating the metal layer 35 c. The conductive film 36 is made of a metal selected from the group consisting of copper, tin, nickel, chromium, titanium, copper-chromium and tin-lead alloy. Preferably, the conductive film 36 is made of copper or palladium particles. The conductive film 36 forming methods include physical vapor deposition (PVD), chemical vapor deposition (CVD), electroless plating, or chemical deposition. In particular, processing methods such as sputtering, evaporation, arc vapor deposition, ion beam sputtering, laser ablation deposition or plasma enhanced chemical vapor deposition are often used to form the conductive film 36. Referring to FIG. 4C, a photoresist layer 37 is formed through printing or coating on the substrate 3 on top of the conductive film 36 thereon, through printing or coating. The photoresist layer 37 can be, for example, a dry film or liquid photoresist. The photoresist layer 37 is further formed with a plurality of opening 37 a to expose the conductive film 36 a on the bonding pads 35.
  • Referring to FIG. 4D, the exposed [0036] conductive film 36 is removed by etching or laser ablation to expose the bonding pads 35.
  • Referring to FIG. 4E, a metal layer such as gold, nickel, palladium, silver, tin, nickel/palladium, chromium/titanium, nickel/gold, palladium/gold or nickel/palladium/gold is plated on the [0037] bonding pads 35. The conductive film 36 is used as a path for electrical current during plating. The conductive film 36 is preferably formed by plating a nickel layer and then a gold layer. The nickel/gold layer can be formed to cover the exposed surface of each bonding pad 35 as a plated layer 35 c. The material used in the plating process of the invention is not limited to nickel and gold. Other suitable materials used, individually or combined with one another, may also be plated directly on the exposed surface of the bonding pads 35.
  • Referring to FIG. 4F, after the plated [0038] layer 35 c is formed on the exposed surface of the bonding pads 35, the photoresist layer 37 and the conductive film 36 covered by the photoresist layer 37 are removed. FIG. 4G illustrates the plated layer 35 c that has been formed on the exposed surface of the bonding pads 35.
  • Referring to FIG. 4H, a [0039] solder mask 38, such as an electrically insulating layer, is formed over the substrate 3 for protection against contamination from the ambient environment. The solder mask 38 has a plurality of openings 38 a to expose the bonding pads 35 having the plated layer 35 c thereon. Each opening 38 a has a diameter that may be either smaller or larger than the size of each bonding pad 35. The exposed bonding pads 35 having the plated layer 35 c thereon serve as external electrical connections of the chip or circuit board.
  • FIG. 5A to FIG. 5I are cross-sectional views of a bonding pad formed on a semiconductor package substrate according to a second embodiment of the invention. [0040]
  • Referring to FIG. 5A, a [0041] package substrate 3 is provided. The substrate 3, as describe above, can be a flip-chip package substrate 3 or a wire-bonding package substrate. The substrate 3 has been subjected to a front-end process. For example, a plurality of through holes or blind holes (not shown) are formed through the substrate 3, and at least one trace layer 32 is formed on/inside the substrate 3.
  • Referring to FIG. 5B, a [0042] conductive film 36 as illustrated in the first embodiment of the invention is formed over the substrate 3. The conductive film 36 serves as electric current paths for the electroplating metal layer 35 c.
  • Referring to FIG. 5C, a [0043] photoresist layer 37 is formed by printing or coating over the substrate 3 on top of the conductive film 36 thereon. The photoresist layer 37 can be, for example a dry film or a liquid photoresist. The photoresist layer 37 has a plurality of openings 37 a, and each of the openings 37 a has an extension portion extending from an inner wall of each opening 37 a to cover a portion of the conductive film 36 on each bonding pad. The remaining portion 36 a of each bonding pad 35 is exposed trough the corresponding opening 37 a, as shown in FIG. 6A.
  • Referring to FIG. 5D, the exposed [0044] conductive film 36 a that is not covered by the photoresist layer 37 is removed by etching or laser ablation. That is, the conductive film 36 a covering the bonding pads 35 in the openings 37 a is removed to expose the bonding pads 35 not covered by the photoresist layer 37.
  • Referring to FIG. 5E, a metal layer such as gold, nickel, palladium, silver, tin, nickel/palladium, chromium/titanium, nickel/gold, palladium/gold or nickel/palladium/gold is plated on the [0045] substrate 3. The conductive film 36 is used as a path for electrical current during plating. The conductive film 36 is preferably formed through plating a nickel layer and then a gold layer. The nickel/gold layer can be formed to cover the exposed surface of each bonding pad 35 as a plated layer 35 c. The material used in this plating process is not limited to nickel and Gold. Other suitable materials used, individually or combined with one another, may be directly plated on the exposed surface of the bonding pads 35.
  • Referring to FIG. 5F, after the plated [0046] layer 35 c has been formed on the exposed surface of the bonding pad 35, the photoresist layer 37 and the conductive film 36 covered by the photoresist layer 37 are removed. FIG. 5G illustrates the plated layer 35 c that has been formed on the exposed surface of the bonding pad 35. FIG. 6B is a schematic perspective view of the plated layer 35 c.
  • Referring to FIG. 5H, a [0047] solder mask 38 is formed over the substrate 3 for protection against contamination in the ambient environment. The solder mask 38 has a plurality of openings 38 a to expose the bonding pads 35 having the plated layer 35 c thereon. Each opening 38 a has a diameter that is smaller than the size of the bonding pad 35 to form a so-called solder mask defined (SMD) configuration. The exposed bonding pads 35 having the plated layer 35 c thereon serve as external electrical connections of the chip or circuit board. FIG. 6C is a schematic, perspective view of the bonding pad 35.
  • Referring to FIG. 5I, the [0048] solder mask 38 is formed over the substrate 3. The solder mask 38 has a plurality of openings 38 a to expose the bonding pads 35 having the plated layer 35 c thereon. Each opening 38 a has a diameter larger than the size of the bonding pad 35 to form a so-called non-solder mask defined (NSMD) configuration. The exposed bonding pads 35 having the plated layer 35 c thereon serve as external electrical connections of the chip or circuit board. With reference to FIG. 6D, a schematic, perspective view of the bonding pad 35 is shown.
  • According to the package substrate and the process of manufacturing the package substrate of the invention, the plated layer, such as a Ni/Au layer, covering the exposed surface of the bonding pads of the package substrate increases electrical connection to other devices, and protects the bonding pads from oxidizing in the ambient environment. Prior problems such as non-uniform plating thickness and black pads are also overcome to increase the reliability of the semiconductor package. During plating of a Ni/Au layer on the bonding pad, the conductive film serves as a path for electrical current to electrically connect the bonding pads on the package substrate, without the need of a plating wire on the package substrate. Thereby, the available outing area is greatly increased and noise interference induced by the plating wires is voided. Furthermore, formation of the Ni/Au layer over the whole trace layer of the substrate is no longer required, which reduces the production cost of the package substrate. [0049]
  • The bonding pad of the invention can be of any type, such as a wire bonding pad, a bump pad, a presolder pad, or a ball pad. Although the above embodiment is exemplified by illustration of one bonding pad, the number of bonding pad is not limited to one. The actual number of bonding pads, electrical current paths and photoresist layers depend on the circuit design requirement. The bonding pads, the electrical current paths and the photoresist layers can be formed on one or both surfaces of the substrate. [0050]
  • The invention has been described using exemplary preferred embodiments. However, it is to be understood that the scope of the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements. The scope of the claims, therefore, should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements. [0051]

Claims (17)

What is claimed is:
1. A process of manufacturing a semiconductor package substrate having bonding pads with a plated metal layer thereon, comprising:
providing a substrate having a plurality of bonding pads on at least one surface thereof, and forming a conductive film over the surface of the substrate;
forming a photoresist layer over the conductive film, wherein the photoresist layer has a plurality of first openings for exposing predetermined portions of the conductive film corresponding in position to the bonding pads;
removing the exposed portions of the conductive film, so as to expose the bonding pads respectively via the first openings;
performing a plating process to form a plated metal layer on the exposed bonding pads respectively; and
removing the photoresist layer and the remainder of the conductive film covered by the photoresist layer.
2. The process of claim 1, further comprising:
forming a solder mask on the surface of the substrate, wherein the solder mask has a plurality of second openings for exposing the plated metal layer on the bonding pads respectively.
3. The process of claim 1, wherein the substrate is a flip-chip type package substrate or a wire-bonding type package substrate.
4. The process of claim 1, wherein the bonding pads are selected from the group consisting of wire-bonding pads, bump pads, presolder pads, and ball pads.
5. The process of claim 1, wherein the metal layer is made of a material selected from the group consisting of gold, nickel, palladium, silver, tin, nickel/palladium, chromium/titanium, nickel/gold, palladium/gold, and nickel/palladium/gold.
6. The process of claim 1, wherein the conductive film is made of a material selected from the group consisting of copper, tin, nickel, chromium, titanium, copper-chromium alloy, and tin-lead alloy.
7. The process of claim 1, wherein the conductive film is formed by a technique selected from the group consisting of sputtering, electroless plating, physical vapor deposition, and chemical vapor deposition.
8. A process of manufacturing a semiconductor package substrate having bonding pads with a plated metal layer thereon, comprising:
providing a substrate having a plurality of bonding pads on at least one surface thereof, and forming a conductive film over the surface of the substrate;
forming a photoresist layer over the conductive film, wherein the photoresist layer has a plurality of first openings corresponding in position to the bonding pads, and an extension portion extending from an inner wall of each of the first openings to partly cover a portion of the conductive film exposed via the corresponding first opening;
removing the part of the conductive film not covered by the photoresist layer, so as to expose the bonding pads respectively via the first openings;
performing a plating process to form a plated metal layer on the exposed bonding pads respectively; and
removing the photoresist layer and the remainder of the conductive film covered by the photoresist layer.
9. The process of claim 8, further comprising:
forming a solder mask on the surface of the substrate, wherein the solder mask has a plurality of second openings for exposing the plated metal layer on the bonding pads respectively.
10. The process of claim 8, wherein the substrate is a flip-chip type package substrate or a wire-bonding type package substrate.
11. The process of claim 8, wherein the bonding pads are selected from the group consisting of wire-bonding pads, bump pads, presolder pads, and ball pads.
12. The process of claim 8, wherein the metal layer is made of a material selected from the group consisting of gold, nickel, palladium, silver, tin, nickel/palladium, chromium/titanium, nickel/gold, palladium/gold, and nickel/palladium/gold.
13. The process of claim 8, wherein the conductive film is made of a material selected from the group consisting of copper, tin, nickel, chromium, titanium, copper-chromium alloy, and tin-lead alloy.
14. The process of claim 8, wherein the conductive film is formed by a technique selected from the group consisting of sputtering, electroless plating, physical vapor deposition, and chemical vapor deposition.
15. A semiconductor package substrate, comprising:
a plurality of bonding pads formed on at least one surface of the substrate;
a plated metal layer deposited on the bonding pads respectively; and
a solder mask formed over the surface of the substrate, wherein the solder mask has a plurality of openings for exposing the plated metal layer on the bonding pads respectively; wherein the bonding pads are free of electrical connection with a plating wire.
16. The semiconductor package substrate of claim 15, wherein the bonding pads are selected from the group consisting of wire-bonding pads, bump pads, presolder pads, and ball pads.
17. The semiconductor package substrate of claim 15, wherein the metal layer is made of a material selected from the group consisting of gold, nickel, palladium, silver, tin, nickel/palladium, chromium/titanium, nickel/gold, palladium/gold, and nickel/palladium/gold.
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US20060049516A1 (en) * 2004-09-07 2006-03-09 Siliconware Precision Industries Co., Ltd. Nickel/gold pad structure of semiconductor package and fabrication method thereof
US20060054350A1 (en) * 2004-09-13 2006-03-16 Toshio Sugawa Circuit board and method of manufacturing the same
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