US20040079643A1

US20040079643A1 - Method for manufacturing wiring substrates

Info

Publication number: US20040079643A1
Application number: US10/283,378
Authority: US
Inventors: Noritaka Ban
Original assignee: Individual
Current assignee: Niterra Co Ltd
Priority date: 2002-10-29
Filing date: 2002-10-29
Publication date: 2004-04-29

Abstract

A method is provided for manufacturing a wiring substrate having via conductors. The method includes the steps of providing a substrate having via holes which open at a surface of the substrate, and completely immersing the substrate, together with an electrode, into an electroplating solution in such a manner that the substrate extends vertically. Bubbles are generated in the solution at a position below the substrate such that the generated bubbles rise along the surface of the substrate, from a lower end to an upper end thereof, while striking the surface. Electric current is caused to flow between the electrode and the substrate to thereby form via conductors in the via holes.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method for manufacturing wiring substrates and, more particularly, to a method for manufacturing wiring substrates including via conductors.

2. Description of the Related Art

Wiring substrates including via conductors are well known. The via conductors are conventionally formed by the following steps. A substrate having via holes formed therein is first fabricated and then is subjected to electroless plating so as to form an electroless plating layer on the wall surface of each via hole. Subsequently, the substrate is immersed in an electroplating solution and subjected to electroplating to thereby form an electroplated conductor on the electroless plating layer of each via hole.

A disadvantage of this method is that, in some cases, a via conductor having a predetermined desired shape is not formed in each via hole even after the electroplating operation. More specifically, in some via holes, the electroplating fails to form a complete electroplated conductor on the wall surface. In particular, in a case in which via conductors to be formed are not cup-shaped via conductors, i.e., wherein each conductor assumes a shape conforming to that of the wall surface of the corresponding via hole, but rather are filled vias formed by completely filling the via holes with an electroplated conductor, the electroplating operation frequently fails to form via conductors that fill via holes to a sufficient, desired degree.

Possible reasons for the failure are as follows. Because the via holes are indented or depressed relative to the surface of a substrate, when the substrate is immersed in a plating solution, air remains within some of the via holes, or air bubbles adhere to the wall surfaces of some via holes. In particular, in the case in which filled vias are formed, the shape of each via hole changes as an electroplated conductor is formed in the via hole, and, depending on the changed shape, air bubbles adhering to the wall surfaces of the via holes become difficult to remove. Since such air bubbles prevent plating of a sufficient supply of the plating solution on the wall surfaces of the via holes, it is difficult to provide uniform growth of the electroplated conductor. As a result, the electroplated conductor is not fully formed on the wall surfaces of some of the via holes.

SUMMARY OF THE INVENTION

The present invention is concerned with overcoming the problems discussed above, and one object of the invention is to provide an improved method for manufacturing a wiring substrate including via conductors which can be used to reliably form via conductors of desired shapes irrespective of the locations thereof within the substrate.

In order to achieve this and other objects, according to the present invention, there is provided a method of manufacturing a wiring substrate including via conductors, the method comprising the steps of: providing a substrate having via holes opening at a surface of the substrate; immersing the substrate, together with an electrode, completely into an electroplating solution in such a manner that the substrate extends vertically; generating bubbles at a position below the substrate in such a manner that the bubbles rise along the surface of the substrate, from a lower end thereof to an upper end thereof, while striking the surface; and providing electric current flow between the electrode and the substrate to thereby form via conductors in the via holes.

In general, as indicated above, when a wiring substrate having via conductors is to be manufactured, a substrate having via holes is prepared and electroplating is then carried out in order to form via conductors in the via holes. In the present invention, electroplating is effected not only through mere immersion of the substrate into an electroplating solution as is conventional. Rather, the substrate is immersed in an electroplating solution so as to extend vertically, so that the surfaces of the substrate are parallel to the vertical. Further, bubbling is performed in such a manner that bubbles generated at a position below the substrate rise along the substrate, while uniformly striking or otherwise contacting the entire substrate surface to be subjected to electroplating, from a lower end of the substrate to an upper end thereof, and thereafter rise further to a position above the substrate.

When electroplating is performed with bubbling, the bubbles successively strike the substrate surface as described above with the consequence that any bubbles remaining within the via holes of the immersed substrate are removed together with bubbles generated by means of the bubbling operation. Moreover, even when air bubbles adhere to the via holes of the substrate after immersion thereof, the air bubbles are removed together with the generated bubbles. As result, the electroplating solution is supplied to the entire wall surface of each via hole, and an electroplated conductor is formed which covers the entire wall surface of each via hole. Therefore, the present invention enables reliable formation of via conductors of a desired shape.

It is also noted that, in accordance with the present invention, because the bubbles successively strike the entire substrate surface, from the lower end thereof to the upper end thereof, via conductors of a desired shape can be formed in the via holes irrespective of the positions of the via holes on the substrate surface.

After the formation of via conductors, the formation of wiring layers is carried out and other processes are performed by known methods to thereby complete the wiring substrate.

According to a further aspect of the invention, the bubbles are generated as follows. A pipe having a large number of holes is disposed below the substrate and a gas, such as air, is fed to the pipe. As a result, bubbles are generated, i.e., released through the holes in the pipe.

When via holes are to be formed on each of the opposite surfaces of the substrate, bubbling is performed in such a manner than bubbles strike both of the opposite surfaces of the substrate. In this case, in accordance with a preferred embodiment, two pipes capable of generating bubbles are disposed with an appropriate separation therebetween such that bubbles generated from one pipe strike one surface of the substrate, whereas bubbles generated from the other pipe strike the other surface of the substrate.

In an important application, the manufacturing method of the present invention is applied to the manufacture of a wiring substrate in which via conductors assume the form of a filled via.

In the case in which the via conductors to be formed by the electroplating process are not cup-shaped via conductors, i.e., are conductors assuming a shape conforming to that of the wall surface of a corresponding via hole, but rather are filled vias formed by filling the via holes with an electroplated conductor, the electroplating frequently fails to produce via conductors of the desired shape, i.e., conductors that fill the via holes to a sufficient degree. Since the via holes are gradually filled with the electroplated conductor, the shapes of the holes (depressions) change accordingly, as the electroplating proceeds. Therefore, depending on the changed via-hole shape, air bubbles adhering to the wall surfaces of the via holes may be difficult to remove.

However, in accordance with the present invention, the substrate is oriented in the plating solution so as to extend vertically, and electroplating is performed while bubbles are generated in such a manner that as the bubbles rise they strike or contact the complete substrate, i.e. both opposite facing surfaces of the substrate. As a consequence, even in the case in which the filled vias are formed in the via holes, electroplating can be properly performed because continuous adhesion of the bubbles to the via holes is prevented. As a result, the via holes can be completely filled with the electroplated conductor and filled vias of the desired shape are always formed.

Needless to say, when filled vias are formed in the via holes, i.e., when the via holes are to be completely filled, a plating solution and plating conditions are employed which differ from those employed for formation of cup-shaped via conductors.

In one advantageous implementation, the substrate used in the manufacturing method of the present invention includes an underlying layer, and a plating resist layer which forms the substrate surface and has openings for exposure of the underlying layer. The above-described via holes may then be formed in the underlying layer and exposed by the openings in the plating resist layer.

In this case, the depth of each via hole, as measured from the substrate surface (the surface of the corresponding plating resist layer), is greater than is the case wherein such a plating resist layer is not provided. Therefore, when the substrate is immersed in the electroplating solution, air frequently remains within the via holes, with the resultant formation of air bubbles therein. Moreover, if these air bubbles adhere to the via holes after immersion of the substrate, removal of such air bubbles becomes more difficult. As a result, via conductors which are not of a desired shape may be formed in a greater number of cases than occur when such a plating resist layer is not provided.

However, in accordance with the present invention, as described above, the substrate is disposed in the plating solution in a vertical orientation, and electroplating is performed while air bubbles are generated in such a manner that the bubbles strike the entire substrate surface(s) as they rise and, therefore, even in the case in which the via holes have an increased depth by virtue of the presence of the plating resist layer, electroplating can be performed and air bubbles adhering to the via holes can be effectively removed. Therefore, via conductors of a desired shape are universally formed.

It is also noted that electroplating is often performed for a substrate carrying a plating resist layer, for example, in the case in which a wiring layer or other layer is formed on the surface of the underlying layer by a semi-additive method. More specifically, by electroless plating, an electroless plated layer is formed on the surface of the underlying layer having via holes so as to cover the entire surface of the underlying layer and the wall surfaces of the via holes. Subsequently, a plating resist layer is formed having an opening that assumes a shape corresponding to that of a wiring layer. The substrate in this state is the substrate which is used in the present invention, i.e., the substrate to be subjected to electroplating. When the substrate undergoes electroplating, via conductors are formed, and electroplating conductors are formed at portions corresponding to the wiring layer or a like layer. After completion of the electroplating, the plating resist layer is removed, and etching is performed so as to remove the thin electroless plating layer, so that a wiring layer, or a like layer of a desired pattern is formed.

Further features and advantages of the present invention will be set forth in, or apparent from, the detailed description of preferred embodiments thereof which follows.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a partially broken away, cross sectional view of a wiring substrate according to one embodiment of the present invention; [0024]
FIG. 2 is a view similar to that of FIG. 1, relating to a method of manufacturing a wiring substrate according to the embodiment of FIG. 1 and showing a substrate used in a copper electroplating step; [0025]
FIG. 3 is a cross sectional view relating to the method of manufacturing a wiring substrate according to the embodiment of FIG. 1 and showing a copper electroplating step for forming filled vias; and [0026]
FIG. 4 is a view similar to that of FIG. 1, relating to the method of manufacturing a wiring substrate according to the embodiment of FIG. 1 and showing the state of the substrate after formation of filled vias by means of copper electroplating.[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS

One preferred embodiment of the present invention will next be described in detail with reference to the drawings. [0028]
As indicated above, FIG. 1 is a partially broken away, cross sectional view of a wiring substrate, denoted [0029] 1, which is to be manufactured by a method according to a preferred embodiment of the present invention. The wiring substrate 1 has the general shape of a rectangular plate (400 mm×400 mm) and includes a main face 3 and a reverse face 5. The wiring substrate 1 includes a plate-shaped core substrate (e.g., an insulating resin layer) 7 (having a typical thickness of about 800 μm) located at the center of the substrate as referenced relative to the thickness thereof. An insulating resin layer 9 (having a typical thickness of about 35 μm) made of, for example, epoxy resin is formed on opposite sides of the insulating resin layer 7. Further, a solder resist layer (insulating resin layer) 11 (having a typical thickness of about 25 μm) made of, for example, epoxy resin is formed on each of the insulating resin layers 9.
A plurality of through-holes [0030] 13 (having a typical diameter of about 350 μm) is formed in the core substrate 7 at predetermined positions, as shown. A substantially cylindrical through-hole conductor 15 (having a typical thickness of about 25 μm) is formed on the wall surface of each through hole 13. A substantially columnar or cylindrical resin plug 17 fills the interior of the through-hole conductor 15. In addition, a plurality of via holes 19, each typically having an opening diameter of about 85 μm, are formed in the insulating resin layers 9 at predetermined positions and in such a manner that the via holes 19 completely penetrate through the insulating resin layers 9. A filled via 21 is formed in each of the via holes 19. Further, plural pad openings 23 are formed in each of the solder resist layers 11 at predetermined positions, and in such a manner that the pad openings 23 completely penetrate through the solder resist layers 11.
A first wiring layer [0031] 25 (having a typical thickness-of about 25 μm) is formed between the core substrate 7 and each of the respective insulating resin layers 9. Each first wiring layer 25 is connected to the through hole conductor 15 and the corresponding filled vias 21. In addition, a second wiring layer 27 (having a typical thickness of about 15 μm) is formed between each of the insulating resin layers 9 and the corresponding solder resist layer 11. Each second wiring layer 27 is connected to the corresponding filled via 21. Further, pads 27 p, which are portions of the second wiring layers 27, are exposed within pad openings 23 of the solder resist layers 11. In order to prevent oxidation of the pads 27 p, a nickel plating layer and a gold plating layer (not shown) are formed, in this particular sequence, on each of the pads 27 p.
The wiring substrate [0032] 1 having the above-described structure, is manufactured in a manner which will now be described.
First, as shown in FIG. 2, a double-sided copper-clad substrate is prepared as the core substrate [0033] 7, and a plurality of through-holes 13 are formed in the core substrate 7 at predetermined positions.
Subsequently, the core substrate [0034] 7 is subjected to copper electroless plating and then copper electroplating. Plating layers are thus formed on the opposite sides of the core substrate 7 in such a manner as to cover substantially the entire surface of the copper film on each side, and the substantially cylindrical through-hole conductor 15 (see FIG. 1 and FIG. 2) is formed on the wall surface of each of the through-holes 13.
Subsequently, the [0035] resin plug 17 is formed in each of the through-hole conductors 15. More specifically, by use of a mask (not shown) of a predetermined pattern having holes which correspond in position and diameter to the positions and diameter of the through hole conductors 15, a resin paste is charged, through printing, into the interiors of the through-hole conductors 15. Subsequently, the resin paste is cured through the application of heat to thereby produce the resin plugs 17. The opposite ends of each resin plug 17 are polished so as to be flush with the corresponding surfaces of the core substrate 7.
After formation of the resin plugs [0036] 17, each copper layer, consisting of a copper film and a copper plating layer, is patterned so as to form the first wiring layers 25 on opposite sides of the core substrate 7. More specifically, a semi-hardened etching resist layer is formed on the copper layer, exposed to light through a mask (not shown) having a predetermined pattern corresponding to that of the first wiring layer 25, and then subjected to development. Subsequently, the etching resist layer is hardened through the application of heat, so as to produce a hardened etching resist layer having a predetermined pattern. Subsequently, exposed portions of the copper layer, i.e., portions not covered by the resist layer, are removed through etching. After completion of the etching operation, the etching resist layer is removed.
In the next step, the insulating [0037] resin layers 9 having the via holes 19 (having a typical opening diameter of about 85 μm) are formed on the first wiring layer 25 and the core substrate 7. More specifically, semi-hardened insulating resin layers are formed on the first wiring layer 25 and the core substrate 7, exposed to light through a mask (not shown) having a predetermined pattern corresponding to that of the via holes 19, and then subjected to development. Subsequently, the insulating resin layers are hardened through application of heat, thereby forming the insulating resin layers 9 having the via holes 19 at predetermined positions. It is noted that the via holes 19 may be formed by means of laser machining.
Next, an electroless copper plating operation is performed, whereby, as represented by the bold line in FIG. 2, an electroless copper plating layer [0038] 31 (having a typical thickness of about 0.7 μm) is formed on the surface of each of the first resin dielectric layers 9 and on the wall surfaces of the via holes 19.
Subsequently, a plating resist [0039] layer 33 of a predetermined pattern having a plurality of openings 35 is formed on each of the electroless copper plating layers 31. More specifically, a semi-hardened plating resist layer is formed on each of the electroless copper plating layers 31, exposed to light through a mask (not shown) having a predetermined pattern corresponding to the second wiring layer 27 and the via holes 19, and then subjected to development. Subsequently, through hardening upon application of heat, the plating resist layer 33, having the openings 35 at predetermined positions, is formed. It is noted that the openings 35 have various shapes corresponding to those of the second wiring layer 27 and the via holes 19.
As a result of the steps just described, a [0040] substrate 51 shown in FIG. 2 is obtained.
Next, in a copper electroplating step, the [0041] substrate 51 is subjected to copper electroplating. Before considering the copper electroplating step, a plating apparatus 101 used in the electroplating step will be described with reference to FIG. 3. The plating apparatus 101 is equipped with a non-illustrated moving unit for moving the substrate 51 while holding the same. The moving unit includes a rack (not shown) for holding the substrate 51, and a moving mechanism (not shown) for moving the rack in horizontal and vertical directions.
The [0042] plating apparatus 101 also includes a copper plating bath 103 for forming copper electroplated conductors on the substrate 51. The copper plating bath 103 stores a copper electroplating solution 105 for forming the filled vias 21. Further, two pipes 107 are disposed in the vicinity of the bottom surface 103 t of the copper plating bath 103. Each of the pipes 107 typically has a length of about 800 mm and includes a large number of holes formed therein for generating bubbles 109. The pipes 107 are disposed parallel to each other, with a distance H (typically of about 60 mm) therebetween, and extend parallel to the bottom surface 103 t of the copper plating bath 103. Accordingly, when air is fed to the pipes 107, a large number of bubbles 109 are generated from the holes in the pipes 107, and move upwardly to the surface of the copper electroplating solution 105.
With this background, the copper electroplating step will be described. [0043]
First, by means of the moving unit described above, the [0044] substrate 51, placed on the rack of the moving unit, is moved horizontally to a position above the copper plating bath 103.
Subsequently, the rack is moved downward in order to immerse the [0045] substrate 51 into the copper electroplating solution 105 stored in the copper plating bath 103. At this time, the substrate 51 is oriented in a vertical position or posture such that the opposite surfaces 53 of the substrate 51 face horizontally, as shown in FIG. 3. Further, an electrode 110 made of copper is immersed in the copper electroplating solution 105 such that the electrode 110 extends vertically. The substrate 51 (and, more specifically, the electroless copper plating layers 31 of the substrate 51 shown in FIG. 2) and the electrode 110 are connected to a power supply PS, and the power supply PS is turned on in order to cause current to flow between the substrate 51 and the electrode 110. After immersion over a predetermined period of time, a copper electroplating conductor is formed on each of the opposite surfaces 53 of the substrate 51, as shown in FIG. 4. Thus, the filled vias 21 and the second wiring layers 27 are formed on the substrate surfaces 53.
In the copper electroplating step, copper electroplating is effected not only through mere immersion of the [0046] substrate 51 into the copper electroplating solution 105. Air is fed to the pipes 107 disposed below the substrate 51 to thereby generate the large number of bubbles 109 (see FIG. 3). Specifically, in an exemplary embodiment, air is fed to the pipes 107 at a rate of 40 to 60 l/min, so that air flows out each pipe 107 in the form of bubbles 109 at a rate of 20 to 30 l/min.
The [0047] bubbles 109 rise along the substrate surfaces 53, from their lower end portions 53 d to upper end portions 53 u, while striking or hitting the surfaces 53, and rise further to a position above the substrate 51. In other words, when copper electroplating is performed, bubbles 109 are generated in such a manner that the bubbles 109 strike or contact the substrate surfaces 53 in a uniform manner irrespective of the location thereon, and the bubbles 109 ultimately rise to a position above the substrate 51 without remaining at the upper end portions 53 u.
It is noted that the via holes [0048] 19 are formed on each of the opposite substrate surfaces 53. Therefore, the bubbling is performed in such a manner that bubbles 109 strike both the opposite substrate surfaces 53. Since the two pipes 107 are disposed within the copper plating bath 103 with the space H formed therebetween, bubbles 109 generated from one pipe 107B strike or hit one substrate surface 53B, whereas bubbles 109 generated from the other pipe 107C strike or hit the opposite substrate surface 53C. Since the length (about 800 mm) of the pipes 107 is set to be about two times the length (400 mm) of the sides of the substrate 51, about one half (10 to 15 l/min) of the bubbles 109 generated from the pipes 107 (20 to 30 l/min) come into contact with each substrate surface 53.
When copper electroplating is performed with the associated bubbling described above, any air bubbles remaining within the via holes [0049] 19 of the immersed substrate 51 are removed together with the generated bubbles 109. Moreover, even when air bubbles adhere to the via holes 19 of the substrate 51 after immersion thereof, the air bubbles are removed together with the generated bubbles 109. As result, the copper electroplating solution 105 is supplied to the entire wall surface of each via hole 19, and a copper electroplating conductor is formed which covers the entire wall surface of each via hole 19. Therefore, the filled vias 21 are uniformly of a desired shape.
Moreover, since the [0050] bubbles 109 successively strike or come into contact with the entire substrate surfaces 53, from their lower end portions 53 d to their upper end portions 53 u, the filled vias 21 of a desired shape can be formed in the via holes 19 irrespective of their positions on the substrate surfaces 53.
In the present embodiment, the vias to be formed through copper electroplating are the filled vias [0051] 21 each formed of a copper electroplated conductor that fills the corresponding via hole 19. In general, the vias are difficult to form in such a manner that the via holes 19 are completely filled with the copper electroplated conductor. Since the via holes 19 are gradually filled with the copper electroplated conductor, the shapes of the holes (depressions) change accordingly. Therefore, depending on the resultant via-hole shape, air bubbles adhering to the wall surfaces of the via holes 19 may be difficult to remove.
However, in the present embodiment, as indicated above, the [0052] substrate 51 is oriented in the plating solution 105 so as to extend vertically, and the copper electroplating is performed while air bubbles 109 are generated in such a manner that they rise while striking the entire substrate surfaces 53. Therefore, even in the case in which the filled vias 21 are formed in the via holes 19, the copper electroplating can be properly performed, while continuous adhesion of the bubbles 109 to the via holes 19 is prevented. As a result, the via holes 19 can always be filled with the copper electroplated conductor as desired, and thus filled vias 21 of a desired shape are formed.
In the present embodiment, the [0053] substrate 51 to be subjected to copper electroplating includes the insulating resin layers (underlying layers) 9 and the plating resist layers 33, which form the substrate surfaces 53 and have openings 35 for exposure of the insulating resin layers 9. The via holes 19 in which the filled via 21 are to be formed are formed in the insulating resin layers 9 and exposed within the openings 35 of the plating resist layers 33. Therefore, the depth of each via hole 19, as measured from the corresponding substrate surface 53 (the surface of the corresponding plating resist layer 33), is greater as compared with the case in which the plating resist layers 33 are not provided. Therefore, when the substrate 51 is immersed in the copper electroplating solution 105, air more frequently remains within the via holes 19, with the resultant formation of air bubbles therein. Further, if air bubbles adhere to the via holes 19 after immersion of the substrate 51, removal of such air bubbles is more difficult. As a result, the filled via 21 of a desired shape may not be formed in a larger number of cases as compared with the case in which the plating resist layers 33 are not provided.
However, in the present embodiment, as described above, the [0054] substrate 51 is immersed in the plating solution 105 in a vertical orientation or posture, and copper electroplating is performed, while air bubbles 109 are generated in such a manner that they rise while striking the entire substrate surfaces 53. Therefore, even in the case in which the via holes 19 have an increased depth by virtue of the presence of the plating resist layers 33, the copper electroplating can be properly performed, while continuous adhesion of the bubbles 109 to the via holes 19 is prevented. As a result, the filled vias 21 are always of the desired shape.
When a predetermined period of time has elapsed after completion of the copper electroplating (i.e., after formation of the filled vias [0055] 21), by means of the moving mechanism described above, the rack is pulled upwardly from the copper plating bath 103 and is then moved horizontally to a next stage. The copper electroplating stage is thus completed.
Next, the plating resist [0056] layers 33 are removed from the substrate 51 in order to expose the electroless copper plating layer 31 which has been previously covered by the plating resist layers 33.
Subsequently, a so-called quick etching is performed in order to remove the exposed electroless [0057] copper plating layer 31.
Next, the solder resist [0058] layers 11 having the pad openings 23 are formed on the insulating resin layers 9 and the second wiring layers 27. Specifically, a semi-hardened solder resist layer is formed on each of the insulating resin layers 9 and the corresponding second wiring layer 27, is exposed to light through a mask having a predetermined pattern corresponding to the pad openings 23, and is then subjected to development. Subsequently, through hardening upon application of heat, the solder resist layers 11 of a predetermined pattern are formed.
Subsequently, a nickel plating layer and a gold plating layer are formed, in this sequence, on the exposed pads [0059] 27 p not covered by the solder resist layers 11.
Thus, the wiring substrate [0060] 1 shown in FIG. 1 is completed.
It will be understood by those skilled in this art that, while the present invention has been described with reference to a preferred embodiment, the present invention is not limited thereto, but may be modified as appropriate without departing from the spirit or scope of the invention. [0061]
It is also noted that the above embodiment is described in reference to a method of manufacturing a multi-layer resin wiring substrate [0062] 1 in which a plurality of insulating resin layers 7, 9, and 11 and a plurality of wiring layers 25 and 27 are stacked one upon another. However, it will be appreciated that the present invention can be applied to other types of wiring substrates, including ceramic wiring substrates, so long as via conductors are formed in their via holes by means of electroplating. Further, the core substrate may be a multi-layer core substrate having wiring layers therein.
Further, in the above-described embodiment, the via [0063] conductors 21 assume the form of a filled via. However, the via conductors 21 may assume the form of a conformal via in which each via hole 19 is not filled completely with a plating material.
In addition, in the above-described embodiment, the via conductors (filled vias) [0064] 21 are formed through copper plating. However, the present invention can also be applied to cases where the via conductors (filled vias) 21 are formed through plating of another, different metal.

Claims

What is claimed:

1. A method of manufacturing a wiring substrate including via conductors, said method comprising the steps of:

providing a substrate having via holes opening at a surface of the substrate;

immersing the substrate, together with an electrode, completely into an electroplating solution in such a manner that the substrate extends vertically;

generating bubbles at a position below the substrate such that the bubbles rise along the surface of the substrate, from a lower end thereof to an upper end thereof, while striking the surface of the substrate; and

producing electric current flow between the electrode and the substrate to thereby form via conductors in the via holes.

2. A method of manufacturing a wiring substrate according to claim 1, wherein the via conductors are caused to assume the form of a filled via.

3. A method of manufacturing a wiring substrate according to claim 1, wherein the substrate includes an underlying layer and a plating resist layer, said plating resist layer forming the substrate surface and having openings therein for exposure of the underlying layer; and

the via holes are formed in the underlying layer and exposed by the openings in the plating resist layer.

4. A method of manufacturing a wiring substrate according to claim 2, wherein the substrate includes an underlying layer and a plating resist layer, said plating resist layer forming the substrate surface and having openings therein for exposure of the underlying layer; and